From nobody Thu Nov 14 06:41:38 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED4C0C77B60 for ; Mon, 3 Apr 2023 09:16:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231913AbjDCJQV (ORCPT ); Mon, 3 Apr 2023 05:16:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231426AbjDCJQM (ORCPT ); Mon, 3 Apr 2023 05:16:12 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88C1810264; Mon, 3 Apr 2023 02:15:50 -0700 (PDT) X-UUID: 1cdeff98d20011eda9a90f0bb45854f4-20230403 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ikbJp6d90IXVw0sxspdPpFbtjqXNe1M7Eau6Eu2D3DM=; b=anu/e93vtTmVrExRX0KTvCV0YMOuu8AH9hwJmUqaOQHvqMiscCbfJmxHGlo7H8Lsp2QiMK57zrGk1Na3Pu4pxGTqkvNoswWvL/eRaXrJv2qnULSGtL1R0FiTt/TObxHsg7Jqv1EDPort2Je9sDrgwHzvCSxVwJdGRJhYvYwonh0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:37b1632b-69aa-4127-ba58-959018233d05,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.22,REQID:37b1632b-69aa-4127-ba58-959018233d05,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:120426c,CLOUDID:f2db23b5-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230403171547O6H131CU,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 1cdeff98d20011eda9a90f0bb45854f4-20230403 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 319230404; Mon, 03 Apr 2023 17:15:44 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 3 Apr 2023 17:15:43 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 3 Apr 2023 17:15:42 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Mauro Carvalho Chehab , Rob Herring CC: Will Deacon , Robin Murphy , Krzysztof Kozlowski , Hans Verkuil , , , , , , , , AngeloGioacchino Del Regno , , , , Yunfei Dong , kyrie wu , , , , Yong Wu Subject: [PATCH v6 09/14] iommu/mediatek: Set dma_mask for the master devices Date: Mon, 3 Apr 2023 17:13:32 +0800 Message-ID: <20230403091337.26745-10-yong.wu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230403091337.26745-1-yong.wu@mediatek.com> References: <20230403091337.26745-1-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MediaTek iommu arranges dma ranges for all the masters, this patch is to help them set dma mask. This is to avoid each master setting their own mask, but also to avoid a real issue, such as JPEG uses "mediatek,mtk-jpgenc" for 2701/8183/8186/8188, then JPEG could ignore its different dma_mask in different SoC to achieve common code. Signed-off-by: Yong Wu --- drivers/iommu/mtk_iommu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0e104bb27010..f58b970dccf2 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -738,6 +738,14 @@ static int mtk_iommu_attach_device(struct iommu_domain= *domain, } mutex_unlock(&data->mutex); =20 + if (region_id > 0) { + ret =3D dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); + if (ret) { + dev_err(m4udev, "Failed to set dma_mask for %s(%d).\n", dev_name(dev), = ret); + return ret; + } + } + return mtk_iommu_config(data, dev, true, region_id); =20 err_unlock: --=20 2.25.1