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[83.9.1.37]) by smtp.gmail.com with ESMTPSA id o28-20020ac2495c000000b004eb2db994e7sm2869344lfi.239.2023.04.05.08.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 08:50:59 -0700 (PDT) From: Konrad Dybcio Date: Wed, 05 Apr 2023 17:50:32 +0200 Subject: [PATCH v2 3/5] arm64: dts: qcom: Add initial QCM2290 device tree MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-topic-rb1_qcm-v2-3-dae06f8830dc@linaro.org> References: <20230403-topic-rb1_qcm-v2-0-dae06f8830dc@linaro.org> In-Reply-To: <20230403-topic-rb1_qcm-v2-0-dae06f8830dc@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Robert Marko , Das Srinagesh Cc: Bhupesh Sharma , Vladimir Zapolskiy , Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680709854; l=41838; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZLAR0hfE9dCtsdhH5I7NhN016VxthG+bkgn5vsQ7j0c=; b=nGIb+xcNx1DZ01fp7R20JKTNLe26+v27nGLuKnn/j1tn4TbVOuS8UEEH4I5uEEww9k2DLIRzaFu3 pIFoAdl+CFjYD3Revedtw8oXpP1N9hLXLNJV/zri5kLZGeQh8DSH X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add an initial device tree for the QCM2290 low-end SoC, featuring 4 "customized" Cortex-A53 cores and up to 4 GiB of LPDDR(3/4X). This revision brings support for: - TSENS & thermal zones - SDHCI1/2 - I2C, SPI, UART - MPSS - ADSP - Wi-Fi Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1561 +++++++++++++++++++++++++++++= ++++ 2 files changed, 1562 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 1a29403400b7..6fc8d6664f0c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qru1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qc= om/qcm2290.dtsi new file mode 100644 index 000000000000..ae5abc76bcc7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -0,0 +1,1561 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + * + * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x0>; + clocks =3D <&cpufreq_hw 0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + }; + }; + + CPU1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x1>; + clocks =3D <&cpufreq_hw 0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + }; + + CPU2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x2>; + clocks =3D <&cpufreq_hw 0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + }; + + CPU3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0 0x3>; + clocks =3D <&cpufreq_hw 0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + enable-method =3D "psci"; + next-level-cache =3D <&L2_0>; + qcom,freq-domain =3D <&cpufreq_hw 0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + + core1 { + cpu =3D <&CPU1>; + }; + + core2 { + cpu =3D <&CPU2>; + }; + + core3 { + cpu =3D <&CPU3>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-qcm2290", "qcom,scm"; + clocks =3D <&rpmcc RPM_SMD_CE1_CLK>; + clock-names =3D "core"; + #reset-cells =3D <1>; + }; + }; + + memory@40000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0 0x40000000 0 0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: hyp@45700000 { + reg =3D <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@45e00000 { + reg =3D <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: sec-apps@45fff000 { + reg =3D <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@46000000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + }; + + pil_modem_mem: modem@4ab00000 { + reg =3D <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: video@51400000 { + reg =3D <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@51900000 { + reg =3D <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_adsp_mem: adsp@51a00000 { + reg =3D <0x0 0x51a00000 0x0 0x1c00000>; + no-map; + }; + + pil_ipa_fw_mem: ipa-fw@53600000 { + reg =3D <0x0 0x53600000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: ipa-gsi@53610000 { + reg =3D <0x0 0x53610000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: zap@53615000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x53615000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: framebuffer@5c000000 { + reg =3D <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: dpfs-data@5cf00000 { + reg =3D <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: reserved@60000000 { + reg =3D <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + + rmtfs_mem: memory@89b01000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0x89b01000 0x0 0x200000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + }; + + rpm-glink { + compatible =3D "qcom,glink-rpm"; + interrupts =3D ; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + mboxes =3D <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-qcm2290"; + qcom,glink-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-qcm2290", "qcom,rpmcc"; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <1>; + }; + + rpmpd: power-controller { + compatible =3D "qcom,qcm2290-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level =3D ; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + + interrupts =3D ; + + mboxes =3D <&apcs_glb 10>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-mpss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + + interrupts =3D ; + + mboxes =3D <&apcs_glb 14>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + wlan_smp2p_in: wlan-wpss-to-ap { + qcom,entry-name =3D "wlan"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + dma-ranges =3D <0 0 0 0 0x10 0>; + + tcsr_mutex: hwlock@340000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tlmm: pinctrl@500000 { + compatible =3D "qcom,qcm2290-tlmm"; + reg =3D <0x0 0x00500000 0x0 0x300000>; + interrupts =3D ; + gpio-controller; + gpio-ranges =3D <&tlmm 0 0 127>; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins =3D "gpio0", "gpio1"; + function =3D "qup0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins =3D "gpio4", "gpio5"; + function =3D "qup1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins =3D "gpio6", "gpio7"; + function =3D "qup2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins =3D "gpio8", "gpio9"; + function =3D "qup3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins =3D "gpio12", "gpio13"; + function =3D "qup4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins =3D "gpio14", "gpio15"; + function =3D "qup5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins =3D "gpio0", "gpio1","gpio2", "gpio3"; + function =3D "qup0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default-state { + pins =3D "gpio4", "gpio5", "gpio69", "gpio70"; + function =3D "qup1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default-state { + pins =3D "gpio6", "gpio7", "gpio71", "gpio80"; + function =3D "qup2"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default-state { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "qup3"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default-state { + pins =3D "gpio12", "gpio13", "gpio96", "gpio97"; + function =3D "qup4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default-state { + pins =3D "gpio14", "gpio15", "gpio16", "gpio17"; + function =3D "qup5"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart0_default: qup-uart0-default-state { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qup0"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins =3D "gpio12", "gpio13"; + function =3D "qup4"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible =3D "qcom,gcc-qcm2290"; + reg =3D <0x0 0x01400000 0x0 0x1f0000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names =3D "bi_tcxo", "sleep_clk"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + usb_hsphy: phy@1613000 { + compatible =3D "qcom,qcm2290-qusb2-phy"; + reg =3D <0x0 0x01613000 0x0 0x180>; + + clocks =3D <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "cfg_ahb", "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells =3D <&qusb2_hstx_trim>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + qfprom@1b44000 { + compatible =3D "qcom,qcm2290-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x01b44000 0x0 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg =3D <0x25b 0x1>; + bits =3D <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts =3D ; + interrupt-names =3D "periph_irq"; + qcom,ee =3D <0>; + qcom,channel =3D <0>; + #address-cells =3D <2>; + #size-cells =3D <0>; + interrupt-controller; + #interrupt-cells =3D <4>; + }; + + tsens0: thermal-sensor@4411000 { + compatible =3D "qcom,qcm2290-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x04411000 0x0 0x1ff>, + <0x0 0x04410000 0x0 0x8>; + #qcom,sensors =3D <10>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + }; + + rng: rng@4453000 { + compatible =3D "qcom,prng-ee"; + reg =3D <0x0 0x04453000 0x0 0x1000>; + clocks =3D <&rpmcc RPM_SMD_HWKM_CLK>; + clock-names =3D "core"; + }; + + rpm_msg_ram: sram@45f0000 { + compatible =3D "qcom,rpm-msg-ram"; + reg =3D <0x0 0x045f0000 0x0 0x7000>; + }; + + sram@4690000 { + compatible =3D "qcom,rpm-stats"; + reg =3D <0x0 0x04690000 0x0 0x10000>; + }; + + sdhc_1: mmc@4744000 { + compatible =3D "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>, + <0x0 0x04748000 0x0 0x8000>; + reg-names =3D "hc", + "cqhci", + "ice"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names =3D "iface", + "core", + "xo", + "ice"; + + resets =3D <&gcc GCC_SDCC1_BCR>; + + power-domains =3D <&rpmpd QCM2290_VDDCX>; + iommus =3D <&apps_smmu 0xc0 0x0>; + + qcom,dll-config =3D <0x000f642c>; + qcom,ddr-config =3D <0x80040868>; + bus-width =3D <8>; + + status =3D "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible =3D "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x04784000 0x0 0x1000>; + reg-names =3D "hc"; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "core", + "xo"; + + resets =3D <&gcc GCC_SDCC2_BCR>; + + power-domains =3D <&rpmpd QCM2290_VDDCX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + iommus =3D <&apps_smmu 0xa0 0x0>; + + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + bus-width =3D <4>; + + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + }; + }; + + gpi_dma0: dma-controller@4a00000 { + compatible =3D "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x04a00000 0x0 0x60000>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + dma-channels =3D <10>; + dma-channel-mask =3D <0x1f>; + iommus =3D <&apps_smmu 0xf6 0x0>; + #dma-cells =3D <3>; + status =3D "disabled"; + }; + + qupv3_id_0: geniqup@4ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x04ac0000 0x0 0x2000>; + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", "s-ahb"; + iommus =3D <&apps_smmu 0xe3 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + i2c0: i2c@4a80000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x04a80000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c0_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi0: spi@4a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x04a80000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi0_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart0: serial@4a80000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a80000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart0_default>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x04a84000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c1_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi1: spi@4a84000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x04a84000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi1_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x04a88000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c2_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi2: spi@4a88000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x04a88000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi2_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x04a8c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c3_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi3: spi@4a8c000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x04a8c000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi3_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x04a90000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c4_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi4: spi@4a90000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x04a90000 0x0 0x4000>; + interrupts =3D ; + clock-names =3D "se"; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&qup_spi4_default>; + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + uart4: serial@4a90000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x04a90000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_uart4_default>; + pinctrl-names =3D "default"; + status =3D "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x04a94000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_i2c5_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + spi5: spi@4a94000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x04a94000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + pinctrl-0 =3D <&qup_spi5_default>; + pinctrl-names =3D "default"; + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", "rx"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + usb: usb@4ef8800 { + compatible =3D "qcom,qcm2290-dwc3", "qcom,dwc3"; + reg =3D <0x0 0x04ef8800 0x0 0x400>; + interrupts =3D , + ; + interrupt-names =3D "hs_phy_irq", "ss_phy_irq"; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <133333333>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + wakeup-source; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + usb_dwc3: usb@4e00000 { + compatible =3D "snps,dwc3"; + reg =3D <0x0 0x04e00000 0x0 0xcd00>; + interrupts =3D ; + phys =3D <&usb_hsphy>; + phy-names =3D "usb2-phy"; + iommus =3D <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold =3D /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed =3D "super-speed"; + dr_mode =3D "otg"; + }; + }; + + remoteproc_mpss: remoteproc@6080000 { + compatible =3D "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; + reg =3D <0x0 0x06080000 0x0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "xo"; + + power-domains =3D <&rpmpd QCM2290_VDDCX>; + + memory-region =3D <&pil_modem_mem>; + + qcom,smem-states =3D <&modem_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts =3D ; + label =3D "mpss"; + qcom,remote-pid =3D <1>; + mboxes =3D <&apcs_glb 12>; + }; + }; + + remoteproc_adsp: remoteproc@ab00000 { + compatible =3D "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; + reg =3D <0x0 0x0ab00000 0x0 0x100>; + + interrupts-extended =3D <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "xo"; + + power-domains =3D <&rpmpd QCM2290_VDD_LPI_CX>, + <&rpmpd QCM2290_VDD_LPI_MX>; + + memory-region =3D <&pil_adsp_mem>; + + qcom,smem-states =3D <&adsp_smp2p_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts =3D ; + label =3D "lpass"; + qcom,remote-pid =3D <2>; + mboxes =3D <&apcs_glb 8>; + }; + }; + + apps_smmu: iommu@c600000 { + compatible =3D "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + wifi: wifi@c800000 { + compatible =3D "qcom,wcn3990-wifi"; + reg =3D <0x0 0x0c800000 0x0 0x800000>; + reg-names =3D "membase"; + memory-region =3D <&wlan_msa_mem>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + iommus =3D <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + status =3D "disabled"; + }; + + watchdog@f017000 { + compatible =3D "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; + reg =3D <0x0 0x0f017000 0x0 0x1000>; + interrupts =3D , + ; + clocks =3D <&sleep_clk>; + }; + + apcs_glb: mailbox@f111000 { + compatible =3D "qcom,qcm2290-apcs-hmss-global"; + reg =3D <0x0 0x0f111000 0x0 0x1000>; + #mbox-cells =3D <1>; + }; + + timer@f120000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x0f120000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x0f121000 0x8000>; + + frame@0 { + reg =3D <0x0 0x1000>, + <0x1000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@2000 { + reg =3D <0x2000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + status =3D "disabled"; + }; + + frame@3000 { + reg =3D <0x3000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + status =3D "disabled"; + }; + + frame@4000 { + reg =3D <0x4000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + status =3D "disabled"; + }; + + frame@5000 { + reg =3D <0x5000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + status =3D "disabled"; + }; + + frame@6000 { + reg =3D <0x6000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + status =3D "disabled"; + }; + + frame@7000 { + reg =3D <0x7000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + status =3D "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f300000 0x0 0x100000>; + interrupts =3D ; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupt-parent =3D <&intc>; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + }; + + cpufreq_hw: cpufreq@f521000 { + compatible =3D "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; + reg =3D <0x0 0x0f521000 0x0 0x1000>; + reg-names =3D "freq-domain0"; + interrupts =3D ; + interrupt-names =3D "dcvsh-irq-0"; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + }; + + thermal-zones { + mapss-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 0>; + + trips { + mapss_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + mapss_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + mapss_crit: mapss-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 1>; + + trips { + video_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + video_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + video_crit: video-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 2>; + + trips { + wlan_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + wlan_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + wlan_crit: wlan-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + cpuss0_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss0_crit: cpuss0-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + cpuss1_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpuss1_crit: cpuss1-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + mdm0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + mdm0_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + mdm0_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + mdm0_crit: mdm0-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + mdm1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + mdm1_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + mdm1_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + mdm1_crit: mdm1-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + gpu_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu_crit: gpu-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + hm-center-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 8>; + + trips { + hm_center_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + hm_center_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + hm_center_crit: hm-center-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + + thermal-sensors =3D <&tsens0 9>; + + trips { + camera_alert0: trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + camera_alert1: trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + camera_crit: camera-crit { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.40.0