From nobody Tue Feb 10 23:53:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B82C761A6 for ; Tue, 4 Apr 2023 09:43:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234325AbjDDJnW (ORCPT ); Tue, 4 Apr 2023 05:43:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234310AbjDDJnQ (ORCPT ); Tue, 4 Apr 2023 05:43:16 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F8771BF1 for ; Tue, 4 Apr 2023 02:43:14 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id k37so41665840lfv.0 for ; Tue, 04 Apr 2023 02:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680601392; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OEIEuBxKK8j0WCwoJQ18kuVBxSDA3HKgR75PLHwlYjY=; b=QUgnZEVbU8qkLDF2ntyTZYUEn81xMGQMTF+In3pJjOtoHeA+wHfgBjiPJd3SQo2ubS EdNjEPTsTPejVfxjcQyDuBp9bw6lcgMwOYJ0hzaw94espyf5V34EXkl/ZpBlcv3D9D83 +0V2+XrzqywGLnbVfh9drT5aX/q5V4zCL36sADRuJeqAfcn/NLlq8m4DdSrZY3wG0Zi/ q8FBEDa9RQuvXQZ0GWlpOlmM6ZZK4U1qYzUppqfAYv14x6YsE1Ip3xn/3V6DSPeA1aCF FhyY2tH7hm6RIvEb2q12iB15E5zC2jQ355mxMbjoyJAliFKlrL3/5gyw+cCOHZfsai7x J1Fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680601392; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OEIEuBxKK8j0WCwoJQ18kuVBxSDA3HKgR75PLHwlYjY=; b=b/65aUyq8mtUQUmVlZKfMOC6e36HWWz+ZDBMxPcm/rjJAO87cbCdniifmjEPjpXo0Z xfADFwDZUrG7TPt86wv1LiYKsZp8GsM8EH6Vm0IcBfkJqND5KF2kleCWXLOH5RTgoywj XAEI2CqZyhXwkPfyAdjI6+sf57XBowN5eouWI5JrpATWh+Aij7LSyuf5lufRMabmh+i2 uG9UiWzVWM7burKVoGxy2NOT5s/qKrX3Z+H83wG/3rATgVpKWikLGEzCX7kyREhIxOSa BYgkMWDHCKW9kBxl4D5J0tYEj+W3f4q352u/JmHH88R7q5rwz+Gl/UmT9zeiFzc2VEP2 cBLQ== X-Gm-Message-State: AAQBX9fAiRCKzi1AJ2O9T7IGgZMxOL7EPAuNKD3zwCth9MD9P3CGKy0x 7jWU91llko+8LgZvD0qM4mkulg== X-Google-Smtp-Source: AKy350Y1n4D3ouEbNQ+64kQoJU+ffHbBrLRRh0g8NH1+mtywafqluhvvLZ5sB6bllrfgJQ3/14bcqQ== X-Received: by 2002:a19:ad04:0:b0:4cb:4362:381d with SMTP id t4-20020a19ad04000000b004cb4362381dmr457830lfc.62.1680601392722; Tue, 04 Apr 2023 02:43:12 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id l25-20020a19c219000000b004eb258f73a9sm2218443lfc.163.2023.04.04.02.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 02:43:12 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:05 +0200 Subject: [PATCH 3/9] pinctrl: armada-37xx: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-3-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 34 ++++++++++++++++++++-----= ---- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/= mvebu/pinctrl-armada-37xx.c index 261b46841b9f..67c6751a6f06 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include =20 @@ -101,7 +102,6 @@ struct armada_37xx_pinctrl { const struct armada_37xx_pin_data *data; struct device *dev; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; raw_spinlock_t irq_lock; struct pinctrl_desc pctl; struct pinctrl_dev *pctl_dev; @@ -548,6 +548,7 @@ static void armada_37xx_irq_mask(struct irq_data *d) val =3D readl(info->base + reg); writel(val & ~d->mask, info->base + reg); raw_spin_unlock_irqrestore(&info->irq_lock, flags); + gpiochip_disable_irq(chip, irqd_to_hwirq(d)); } =20 static void armada_37xx_irq_unmask(struct irq_data *d) @@ -557,6 +558,7 @@ static void armada_37xx_irq_unmask(struct irq_data *d) u32 val, reg =3D IRQ_EN; unsigned long flags; =20 + gpiochip_enable_irq(chip, irqd_to_hwirq(d)); armada_37xx_irq_update_reg(®, d); raw_spin_lock_irqsave(&info->irq_lock, flags); val =3D readl(info->base + reg); @@ -729,11 +731,30 @@ static unsigned int armada_37xx_irq_startup(struct ir= q_data *d) return 0; } =20 +static void armada_37xx_irq_print_chip(struct irq_data *d, struct seq_file= *p) +{ + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info =3D gpiochip_get_data(chip); + + seq_printf(p, info->data->name); +} + +static const struct irq_chip armada_37xx_irqchip =3D { + .irq_ack =3D armada_37xx_irq_ack, + .irq_mask =3D armada_37xx_irq_mask, + .irq_unmask =3D armada_37xx_irq_unmask, + .irq_set_wake =3D armada_37xx_irq_set_wake, + .irq_set_type =3D armada_37xx_irq_set_type, + .irq_startup =3D armada_37xx_irq_startup, + .irq_print_chip =3D armada_37xx_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int armada_37xx_irqchip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { struct gpio_chip *gc =3D &info->gpio_chip; - struct irq_chip *irqchip =3D &info->irq_chip; struct gpio_irq_chip *girq =3D &gc->irq; struct device_node *np =3D to_of_node(gc->fwnode); struct device *dev =3D &pdev->dev; @@ -751,14 +772,7 @@ static int armada_37xx_irqchip_register(struct platfor= m_device *pdev, if (IS_ERR(info->base)) return PTR_ERR(info->base); =20 - irqchip->irq_ack =3D armada_37xx_irq_ack; - irqchip->irq_mask =3D armada_37xx_irq_mask; - irqchip->irq_unmask =3D armada_37xx_irq_unmask; - irqchip->irq_set_wake =3D armada_37xx_irq_set_wake; - irqchip->irq_set_type =3D armada_37xx_irq_set_type; - irqchip->irq_startup =3D armada_37xx_irq_startup; - irqchip->name =3D info->data->name; - girq->chip =3D irqchip; + gpio_irq_chip_set_chip(girq, &armada_37xx_irqchip); girq->parent_handler =3D armada_37xx_irq_handler; /* * Many interrupts are connected to the parent interrupt --=20 2.34.1