From nobody Tue Feb 10 23:53:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 744B0C6FD1D for ; Tue, 4 Apr 2023 09:43:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234319AbjDDJnT (ORCPT ); Tue, 4 Apr 2023 05:43:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234305AbjDDJnP (ORCPT ); Tue, 4 Apr 2023 05:43:15 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AF051BEA for ; Tue, 4 Apr 2023 02:43:13 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id c29so41632161lfv.3 for ; Tue, 04 Apr 2023 02:43:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680601391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=E1U3mznWUSnJq2x7KzrZeo74yHwZxjse8U63SQkTN4k=; b=eX5ZeFcrDyeOZ/+cmIw1GthasxB336QssKMWmkFVFjzUzquTWCGLPH0q1EZGkx57D7 lMBTV4GQvDuLwdcpX7uMkCsYiT15dsHdEflv9g0w1W+ahbDSVxbyUvz5gUTVJ5sYN5nd gGSkMJIKgzuEsvJpz5qvVuUa9tXPAIFLLMxBUS9ZN6aJGEJa88cvLFIhVRzr7cFD3xO4 V/C0tVGfceLtY5T6HC9Bg5fuMQSPe39vC9gft3my7IAoHhwOGoYe386nE0RCa7Nph0FF HFz4nkApA+T03Chl0EFnlvCZrI+HrbjlWiHUeCW0UG/pPXcOb+msKYSk3REigmMJsDvV tYCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680601391; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E1U3mznWUSnJq2x7KzrZeo74yHwZxjse8U63SQkTN4k=; b=ucHHd5+1AImvREDep9Iw/1dRuH3rAwYWh4hGg9JnTSkcqMUxylbEzwMyC7BmilCZ36 KMSF0/lnCHlOTLoIV3O3m3Au1af7rG8GNYzL4JklIHAFSLcydUaPCdHR16xZIc5wseuv UfhX8p/6+toFxgcmuf5Iyi4kDTPW7Pqv+K5tAGs0k5vxI6v2eUcdXjbwKALIXBOn9dWy GDKzTt9Q/xDKGe3EIcUvtEWGbZiKVbaAYg7yUEqSPjg/eTeXULritfTiZZ1RLPtO/0xF 4HIE91lLyCzeXfmuq+H20KHq6sD4o/eoz30cKY+iTAZAVU8nx5ZNHS5EUWP5i6RLpVug 7AxA== X-Gm-Message-State: AAQBX9efCR+2DHA+635s9sOCoM4Yi1TDlxN9/T8ymHLWlDjECOsinU+v tQJbgW5QDFd3W3QLJHSEaiF8Ww== X-Google-Smtp-Source: AKy350a7DLDlAx2wATbxYZ+yV4+OnJfCSexEHHMxv0+zsfQNpGxjvujPBQwRFlw396afIThPkSlLDg== X-Received: by 2002:a05:6512:118d:b0:4eb:2b62:134f with SMTP id g13-20020a056512118d00b004eb2b62134fmr4661753lfr.16.1680601391634; Tue, 04 Apr 2023 02:43:11 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id l25-20020a19c219000000b004eb258f73a9sm2218443lfc.163.2023.04.04.02.43.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 02:43:11 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:04 +0200 Subject: [PATCH 2/9] pinctrl: nsp: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-2-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/p= inctrl-nsp-gpio.c index 3c792bf03bda..5045a7e57f1d 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -60,7 +60,6 @@ struct nsp_gpio { struct device *dev; void __iomem *base; void __iomem *io_ctrl; - struct irq_chip irqchip; struct gpio_chip gc; struct pinctrl_dev *pctl; struct pinctrl_desc pctldesc; @@ -193,6 +192,7 @@ static void nsp_gpio_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&chip->lock, flags); nsp_gpio_irq_set_mask(d, false); raw_spin_unlock_irqrestore(&chip->lock, flags); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 static void nsp_gpio_irq_unmask(struct irq_data *d) @@ -201,6 +201,7 @@ static void nsp_gpio_irq_unmask(struct irq_data *d) struct nsp_gpio *chip =3D gpiochip_get_data(gc); unsigned long flags; =20 + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); raw_spin_lock_irqsave(&chip->lock, flags); nsp_gpio_irq_set_mask(d, true); raw_spin_unlock_irqrestore(&chip->lock, flags); @@ -258,6 +259,16 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, u= nsigned int type) return 0; } =20 +static const struct irq_chip nsp_gpio_irq_chip =3D { + .name =3D "gpio-a", + .irq_ack =3D nsp_gpio_irq_ack, + .irq_mask =3D nsp_gpio_irq_mask, + .irq_unmask =3D nsp_gpio_irq_unmask, + .irq_set_type =3D nsp_gpio_irq_set_type, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) { struct nsp_gpio *chip =3D gpiochip_get_data(gc); @@ -650,14 +661,6 @@ static int nsp_gpio_probe(struct platform_device *pdev) irq =3D platform_get_irq(pdev, 0); if (irq > 0) { struct gpio_irq_chip *girq; - struct irq_chip *irqc; - - irqc =3D &chip->irqchip; - irqc->name =3D "gpio-a"; - irqc->irq_ack =3D nsp_gpio_irq_ack; - irqc->irq_mask =3D nsp_gpio_irq_mask; - irqc->irq_unmask =3D nsp_gpio_irq_unmask; - irqc->irq_set_type =3D nsp_gpio_irq_set_type; =20 val =3D readl(chip->base + NSP_CHIP_A_INT_MASK); val =3D val | NSP_CHIP_A_GPIO_INT_BIT; @@ -673,7 +676,7 @@ static int nsp_gpio_probe(struct platform_device *pdev) } =20 girq =3D &chip->gc.irq; - girq->chip =3D irqc; + gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; girq->num_parents =3D 0; --=20 2.34.1