From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 712F7C6FD1D for ; Tue, 4 Apr 2023 09:43:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234330AbjDDJnZ (ORCPT ); Tue, 4 Apr 2023 05:43:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234309AbjDDJnQ (ORCPT ); Tue, 4 Apr 2023 05:43:16 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58A6B1BD0 for ; Tue, 4 Apr 2023 02:43:12 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id c29so41632118lfv.3 for ; Tue, 04 Apr 2023 02:43:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680601390; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RKK9eLgubzxWPHMWxI1yK7d1/+43BWwyQkM2tfuG2Ww=; b=x7ppiWbyNyZwwriIorzWRnpZP4rWgQx6yFQbqXqh1OXDLJel4zda/pCcS6POdONcaG 7Yv3e7fbUTqfjUrHeAtVc5xqJ4Gmz4/GtSFu4grqH+f3gGPtr0jGvRyKK6vRApV0uNNn pBO5KB050ARhuPvDhuT2MFcCNRi/fcfb9A8aqygpgQrVbjwJfG7hcodVt+q/oS/Bx9LW /fnKSlEVfDctfs5GeV3aYtiORbT1k5+p5mQ5pjXT0uBW89SPhm+5PXh2tDA/qmLebjcZ KK5Dn3f/RObhVpTmQsLbGJDuntgJHC8ftHLkH2+hc+DxBbBxb4xgIHwtdQT4P8ohou1j CfyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680601390; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RKK9eLgubzxWPHMWxI1yK7d1/+43BWwyQkM2tfuG2Ww=; b=uqZwHWh/OGVpnthIJG/+v2OsUDB8kK7VV73DLVvWs/x+t+RYVedwnyhWmHoo0+QSKp IZp/NNzsd1tErcyHU+TzkhX9x+d2KmvVw/Ulz66v/n12yTWQlnjYjh1O+6/H3vIwXWg+ V0HxLMdd0vxX8bdJfJkXCcEyLkzMLISNKA+qhUoruJJFD3lUTcwZPV9llKayB8Ux4rPJ nR1DwH6lWCCJL012WKGRaO8GraEBlhmL6VuKcfiZS+g85x93579m1n9YQvtjxY+DUlXK c79v1SxR+ZAVclebwQsezAjY8k38pSs/C9T/EH2at/ngs1tTL3D87wGjN1oRQ7WNHJbC TvVw== X-Gm-Message-State: AAQBX9fF6eG/Smni353omIGGNoffUxsvKKx2f9/r8jFd3eL7f1Vlfpp3 c0ptOmqNIGiANW24HuAwVxm1QA== X-Google-Smtp-Source: AKy350bXU9qE5on50GOy/zA3QRbSNFs+CqcTvsLk9DkI3fNquQp8y9IwP/2sQB6t0bTIVTgIgnAjHw== X-Received: by 2002:ac2:4c92:0:b0:4df:b32b:a2a3 with SMTP id d18-20020ac24c92000000b004dfb32ba2a3mr477734lfl.47.1680601390612; Tue, 04 Apr 2023 02:43:10 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id l25-20020a19c219000000b004eb258f73a9sm2218443lfc.163.2023.04.04.02.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 02:43:10 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:03 +0200 Subject: [PATCH 1/9] pinctrl: iproc: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-1-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 38 +++++++++++++++++++++-------= ---- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm= /pinctrl-iproc-gpio.c index 3df56a4ea510..cc3eb7409ab3 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -23,6 +23,7 @@ #include #include #include +#include #include =20 #include @@ -108,7 +109,6 @@ struct iproc_gpio { =20 raw_spinlock_t lock; =20 - struct irq_chip irqchip; struct gpio_chip gc; unsigned num_banks; =20 @@ -217,7 +217,7 @@ static void iproc_gpio_irq_set_mask(struct irq_data *d,= bool unmask) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct iproc_gpio *chip =3D gpiochip_get_data(gc); - unsigned gpio =3D d->hwirq; + unsigned gpio =3D irqd_to_hwirq(d); =20 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask); } @@ -231,6 +231,7 @@ static void iproc_gpio_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&chip->lock, flags); iproc_gpio_irq_set_mask(d, false); raw_spin_unlock_irqrestore(&chip->lock, flags); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 static void iproc_gpio_irq_unmask(struct irq_data *d) @@ -239,6 +240,7 @@ static void iproc_gpio_irq_unmask(struct irq_data *d) struct iproc_gpio *chip =3D gpiochip_get_data(gc); unsigned long flags; =20 + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); raw_spin_lock_irqsave(&chip->lock, flags); iproc_gpio_irq_set_mask(d, true); raw_spin_unlock_irqrestore(&chip->lock, flags); @@ -302,6 +304,26 @@ static int iproc_gpio_irq_set_type(struct irq_data *d,= unsigned int type) return 0; } =20 +static void iproc_gpio_irq_print_chip(struct irq_data *d, struct seq_file = *p) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct iproc_gpio *chip =3D gpiochip_get_data(gc); + + seq_printf(p, dev_name(chip->dev)); +} + +static const struct irq_chip iproc_gpio_irq_chip =3D { + .irq_ack =3D iproc_gpio_irq_ack, + .irq_mask =3D iproc_gpio_irq_mask, + .irq_unmask =3D iproc_gpio_irq_unmask, + .irq_set_type =3D iproc_gpio_irq_set_type, + .irq_enable =3D iproc_gpio_irq_unmask, + .irq_disable =3D iproc_gpio_irq_mask, + .irq_print_chip =3D iproc_gpio_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + /* * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO */ @@ -852,20 +874,10 @@ static int iproc_gpio_probe(struct platform_device *p= dev) /* optional GPIO interrupt support */ irq =3D platform_get_irq_optional(pdev, 0); if (irq > 0) { - struct irq_chip *irqc; struct gpio_irq_chip *girq; =20 - irqc =3D &chip->irqchip; - irqc->name =3D dev_name(dev); - irqc->irq_ack =3D iproc_gpio_irq_ack; - irqc->irq_mask =3D iproc_gpio_irq_mask; - irqc->irq_unmask =3D iproc_gpio_irq_unmask; - irqc->irq_set_type =3D iproc_gpio_irq_set_type; - irqc->irq_enable =3D iproc_gpio_irq_unmask; - irqc->irq_disable =3D iproc_gpio_irq_mask; - girq =3D &gc->irq; - girq->chip =3D irqc; + gpio_irq_chip_set_chip(girq, &iproc_gpio_irq_chip); girq->parent_handler =3D iproc_gpio_irq_handler; girq->num_parents =3D 1; girq->parents =3D devm_kcalloc(dev, 1, --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 744B0C6FD1D for ; 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Tue, 04 Apr 2023 02:43:11 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:04 +0200 Subject: [PATCH 2/9] pinctrl: nsp: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-2-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-nsp-gpio.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/p= inctrl-nsp-gpio.c index 3c792bf03bda..5045a7e57f1d 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -60,7 +60,6 @@ struct nsp_gpio { struct device *dev; void __iomem *base; void __iomem *io_ctrl; - struct irq_chip irqchip; struct gpio_chip gc; struct pinctrl_dev *pctl; struct pinctrl_desc pctldesc; @@ -193,6 +192,7 @@ static void nsp_gpio_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&chip->lock, flags); nsp_gpio_irq_set_mask(d, false); raw_spin_unlock_irqrestore(&chip->lock, flags); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 static void nsp_gpio_irq_unmask(struct irq_data *d) @@ -201,6 +201,7 @@ static void nsp_gpio_irq_unmask(struct irq_data *d) struct nsp_gpio *chip =3D gpiochip_get_data(gc); unsigned long flags; =20 + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); raw_spin_lock_irqsave(&chip->lock, flags); nsp_gpio_irq_set_mask(d, true); raw_spin_unlock_irqrestore(&chip->lock, flags); @@ -258,6 +259,16 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, u= nsigned int type) return 0; } =20 +static const struct irq_chip nsp_gpio_irq_chip =3D { + .name =3D "gpio-a", + .irq_ack =3D nsp_gpio_irq_ack, + .irq_mask =3D nsp_gpio_irq_mask, + .irq_unmask =3D nsp_gpio_irq_unmask, + .irq_set_type =3D nsp_gpio_irq_set_type, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) { struct nsp_gpio *chip =3D gpiochip_get_data(gc); @@ -650,14 +661,6 @@ static int nsp_gpio_probe(struct platform_device *pdev) irq =3D platform_get_irq(pdev, 0); if (irq > 0) { struct gpio_irq_chip *girq; - struct irq_chip *irqc; - - irqc =3D &chip->irqchip; - irqc->name =3D "gpio-a"; - irqc->irq_ack =3D nsp_gpio_irq_ack; - irqc->irq_mask =3D nsp_gpio_irq_mask; - irqc->irq_unmask =3D nsp_gpio_irq_unmask; - irqc->irq_set_type =3D nsp_gpio_irq_set_type; =20 val =3D readl(chip->base + NSP_CHIP_A_INT_MASK); val =3D val | NSP_CHIP_A_GPIO_INT_BIT; @@ -673,7 +676,7 @@ static int nsp_gpio_probe(struct platform_device *pdev) } =20 girq =3D &chip->gc.irq; - girq->chip =3D irqc; + gpio_irq_chip_set_chip(girq, &nsp_gpio_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; girq->num_parents =3D 0; --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B82C761A6 for ; Tue, 4 Apr 2023 09:43:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234325AbjDDJnW (ORCPT ); Tue, 4 Apr 2023 05:43:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234310AbjDDJnQ (ORCPT ); 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Tue, 04 Apr 2023 02:43:12 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:05 +0200 Subject: [PATCH 3/9] pinctrl: armada-37xx: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-3-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 34 ++++++++++++++++++++-----= ---- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/= mvebu/pinctrl-armada-37xx.c index 261b46841b9f..67c6751a6f06 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include =20 @@ -101,7 +102,6 @@ struct armada_37xx_pinctrl { const struct armada_37xx_pin_data *data; struct device *dev; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; raw_spinlock_t irq_lock; struct pinctrl_desc pctl; struct pinctrl_dev *pctl_dev; @@ -548,6 +548,7 @@ static void armada_37xx_irq_mask(struct irq_data *d) val =3D readl(info->base + reg); writel(val & ~d->mask, info->base + reg); raw_spin_unlock_irqrestore(&info->irq_lock, flags); + gpiochip_disable_irq(chip, irqd_to_hwirq(d)); } =20 static void armada_37xx_irq_unmask(struct irq_data *d) @@ -557,6 +558,7 @@ static void armada_37xx_irq_unmask(struct irq_data *d) u32 val, reg =3D IRQ_EN; unsigned long flags; =20 + gpiochip_enable_irq(chip, irqd_to_hwirq(d)); armada_37xx_irq_update_reg(®, d); raw_spin_lock_irqsave(&info->irq_lock, flags); val =3D readl(info->base + reg); @@ -729,11 +731,30 @@ static unsigned int armada_37xx_irq_startup(struct ir= q_data *d) return 0; } =20 +static void armada_37xx_irq_print_chip(struct irq_data *d, struct seq_file= *p) +{ + struct gpio_chip *chip =3D irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info =3D gpiochip_get_data(chip); + + seq_printf(p, info->data->name); +} + +static const struct irq_chip armada_37xx_irqchip =3D { + .irq_ack =3D armada_37xx_irq_ack, + .irq_mask =3D armada_37xx_irq_mask, + .irq_unmask =3D armada_37xx_irq_unmask, + .irq_set_wake =3D armada_37xx_irq_set_wake, + .irq_set_type =3D armada_37xx_irq_set_type, + .irq_startup =3D armada_37xx_irq_startup, + .irq_print_chip =3D armada_37xx_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int armada_37xx_irqchip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { struct gpio_chip *gc =3D &info->gpio_chip; - struct irq_chip *irqchip =3D &info->irq_chip; struct gpio_irq_chip *girq =3D &gc->irq; struct device_node *np =3D to_of_node(gc->fwnode); struct device *dev =3D &pdev->dev; @@ -751,14 +772,7 @@ static int armada_37xx_irqchip_register(struct platfor= m_device *pdev, if (IS_ERR(info->base)) return PTR_ERR(info->base); =20 - irqchip->irq_ack =3D armada_37xx_irq_ack; - irqchip->irq_mask =3D armada_37xx_irq_mask; - irqchip->irq_unmask =3D armada_37xx_irq_unmask; - irqchip->irq_set_wake =3D armada_37xx_irq_set_wake; - irqchip->irq_set_type =3D armada_37xx_irq_set_type; - irqchip->irq_startup =3D armada_37xx_irq_startup; - irqchip->name =3D info->data->name; - girq->chip =3D irqchip; + gpio_irq_chip_set_chip(girq, &armada_37xx_irqchip); girq->parent_handler =3D armada_37xx_irq_handler; /* * Many interrupts are connected to the parent interrupt --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0532FC6FD1D for ; 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Tue, 04 Apr 2023 02:43:13 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:06 +0200 Subject: [PATCH 4/9] pinctrl: npcm7xx: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-4-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. I refactored the way the state container was accessed in the irq_chip callbacks to all look the same and switch to use irqd_to_hwirq() while we are at it. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 34 ++++++++++++++++-----------= ---- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nu= voton/pinctrl-npcm7xx.c index ff5bcea172e8..05d39f9111c2 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -82,7 +82,6 @@ struct npcm7xx_gpio { struct gpio_chip gc; int irqbase; int irq; - struct irq_chip irq_chip; u32 pinctrl_id; int (*direction_input)(struct gpio_chip *chip, unsigned int offset); int (*direction_output)(struct gpio_chip *chip, unsigned int offset, @@ -240,9 +239,9 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) =20 static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type) { - struct npcm7xx_gpio *bank =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - unsigned int gpio =3D BIT(d->hwirq); + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct npcm7xx_gpio *bank =3D gpiochip_get_data(gc); + unsigned int gpio =3D BIT(irqd_to_hwirq(d)); =20 dev_dbg(bank->gc.parent, "setirqtype: %u.%u =3D %u\n", gpio, d->irq, type); @@ -288,9 +287,9 @@ static int npcmgpio_set_irq_type(struct irq_data *d, un= signed int type) =20 static void npcmgpio_irq_ack(struct irq_data *d) { - struct npcm7xx_gpio *bank =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - unsigned int gpio =3D d->hwirq; + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct npcm7xx_gpio *bank =3D gpiochip_get_data(gc); + unsigned int gpio =3D irqd_to_hwirq(d); =20 dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); @@ -299,23 +298,25 @@ static void npcmgpio_irq_ack(struct irq_data *d) /* Disable GPIO interrupt */ static void npcmgpio_irq_mask(struct irq_data *d) { - struct npcm7xx_gpio *bank =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - unsigned int gpio =3D d->hwirq; + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct npcm7xx_gpio *bank =3D gpiochip_get_data(gc); + unsigned int gpio =3D irqd_to_hwirq(d); =20 /* Clear events */ dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); + gpiochip_disable_irq(gc, gpio); } =20 /* Enable GPIO interrupt */ static void npcmgpio_irq_unmask(struct irq_data *d) { - struct npcm7xx_gpio *bank =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - unsigned int gpio =3D d->hwirq; + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct npcm7xx_gpio *bank =3D gpiochip_get_data(gc); + unsigned int gpio =3D irqd_to_hwirq(d); =20 /* Enable events */ + gpiochip_enable_irq(gc, gpio); dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); } @@ -323,7 +324,7 @@ static void npcmgpio_irq_unmask(struct irq_data *d) static unsigned int npcmgpio_irq_startup(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); - unsigned int gpio =3D d->hwirq; + unsigned int gpio =3D irqd_to_hwirq(d); =20 /* active-high, input, clear interrupt, enable interrupt */ dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq); @@ -341,6 +342,8 @@ static const struct irq_chip npcmgpio_irqchip =3D { .irq_mask =3D npcmgpio_irq_mask, .irq_set_type =3D npcmgpio_set_irq_type, .irq_startup =3D npcmgpio_irq_startup, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 /* pinmux handing in the pinctrl driver*/ @@ -1906,7 +1909,6 @@ static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pc= trl) return -EINVAL; } pctrl->gpio_bank[id].irq =3D ret; - pctrl->gpio_bank[id].irq_chip =3D npcmgpio_irqchip; pctrl->gpio_bank[id].irqbase =3D id * NPCM7XX_GPIO_PER_BANK; pctrl->gpio_bank[id].pinctrl_id =3D args.args[0]; pctrl->gpio_bank[id].gc.base =3D args.args[1]; @@ -1941,7 +1943,7 @@ static int npcm7xx_gpio_register(struct npcm7xx_pinct= rl *pctrl) struct gpio_irq_chip *girq; =20 girq =3D &pctrl->gpio_bank[id].gc.irq; - girq->chip =3D &pctrl->gpio_bank[id].irq_chip; + gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip); girq->parent_handler =3D npcmgpio_irq_handler; girq->num_parents =3D 1; girq->parents =3D devm_kcalloc(pctrl->dev, 1, --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59E6AC6FD1D for ; Tue, 4 Apr 2023 09:43:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233963AbjDDJnk (ORCPT ); Tue, 4 Apr 2023 05:43:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234335AbjDDJn0 (ORCPT ); Tue, 4 Apr 2023 05:43:26 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B815213B for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-5-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-equilibrium.c | 22 ++++++++++++++-------- drivers/pinctrl/pinctrl-equilibrium.h | 2 -- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctr= l-equilibrium.c index 99cf24eb67ae..5b5ddf7e5d0e 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -32,6 +32,7 @@ static void eqbr_gpio_disable_irq(struct irq_data *d) raw_spin_lock_irqsave(&gctrl->lock, flags); writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); raw_spin_unlock_irqrestore(&gctrl->lock, flags); + gpiochip_disable_irq(gc, offset); } =20 static void eqbr_gpio_enable_irq(struct irq_data *d) @@ -42,6 +43,7 @@ static void eqbr_gpio_enable_irq(struct irq_data *d) unsigned long flags; =20 gc->direction_input(gc, offset); + gpiochip_enable_irq(gc, offset); raw_spin_lock_irqsave(&gctrl->lock, flags); writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); raw_spin_unlock_irqrestore(&gctrl->lock, flags); @@ -161,6 +163,17 @@ static void eqbr_irq_handler(struct irq_desc *desc) chained_irq_exit(ic, desc); } =20 +static const struct irq_chip eqbr_irq_chip =3D { + .name =3D "gpio_irq", + .irq_mask =3D eqbr_gpio_disable_irq, + .irq_unmask =3D eqbr_gpio_enable_irq, + .irq_ack =3D eqbr_gpio_ack_irq, + .irq_mask_ack =3D eqbr_gpio_mask_ack_irq, + .irq_set_type =3D eqbr_gpio_set_irq_type, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl) { struct gpio_irq_chip *girq; @@ -176,15 +189,8 @@ static int gpiochip_setup(struct device *dev, struct e= qbr_gpio_ctrl *gctrl) return 0; } =20 - gctrl->ic.name =3D "gpio_irq"; - gctrl->ic.irq_mask =3D eqbr_gpio_disable_irq; - gctrl->ic.irq_unmask =3D eqbr_gpio_enable_irq; - gctrl->ic.irq_ack =3D eqbr_gpio_ack_irq; - gctrl->ic.irq_mask_ack =3D eqbr_gpio_mask_ack_irq; - gctrl->ic.irq_set_type =3D eqbr_gpio_set_irq_type; - girq =3D &gctrl->chip.irq; - girq->chip =3D &gctrl->ic; + gpio_irq_chip_set_chip(girq, &eqbr_irq_chip); girq->parent_handler =3D eqbr_irq_handler; girq->num_parents =3D 1; girq->parents =3D devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL= ); diff --git a/drivers/pinctrl/pinctrl-equilibrium.h b/drivers/pinctrl/pinctr= l-equilibrium.h index 0c635a5b79f0..83768cc8b3db 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.h +++ b/drivers/pinctrl/pinctrl-equilibrium.h @@ -103,7 +103,6 @@ struct fwnode_handle; * @fwnode: firmware node of gpio controller. * @bank: pointer to corresponding pin bank. * @membase: base address of the gpio controller. - * @ic: irq chip. * @name: gpio chip name. * @virq: irq number of the gpio chip to parent's irq domain. * @lock: spin lock to protect gpio register write. @@ -113,7 +112,6 @@ struct eqbr_gpio_ctrl { struct fwnode_handle *fwnode; struct eqbr_pin_bank *bank; void __iomem *membase; - struct irq_chip ic; const char *name; unsigned int virq; raw_spinlock_t lock; /* protect gpio register */ --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5D9CC761AF for ; Tue, 4 Apr 2023 09:43:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234370AbjDDJng (ORCPT ); Tue, 4 Apr 2023 05:43:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234309AbjDDJn0 (ORCPT ); Tue, 4 Apr 2023 05:43:26 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B31B212D for ; Tue, 4 Apr 2023 02:43:16 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id j11so41569986lfg.13 for ; Tue, 04 Apr 2023 02:43:16 -0700 (PDT) DKIM-Signature: v=1; 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Tue, 04 Apr 2023 02:43:15 -0700 (PDT) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id l25-20020a19c219000000b004eb258f73a9sm2218443lfc.163.2023.04.04.02.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Apr 2023 02:43:15 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:08 +0200 Subject: [PATCH 6/9] pinctrl: mcp23s08: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-6-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. I switched to using irqd_to_hwirq() consistently while we are at it. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 36 ++++++++++++++++++++++++++--------= -- drivers/pinctrl/pinctrl-mcp23s08.h | 1 - 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-m= cp23s08.c index 5f356edfd0fd..7b7764c04327 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -436,17 +437,19 @@ static void mcp23s08_irq_mask(struct irq_data *data) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp =3D gpiochip_get_data(gc); - unsigned int pos =3D data->hwirq; + unsigned int pos =3D irqd_to_hwirq(data); =20 mcp_set_bit(mcp, MCP_GPINTEN, pos, false); + gpiochip_disable_irq(gc, pos); } =20 static void mcp23s08_irq_unmask(struct irq_data *data) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp =3D gpiochip_get_data(gc); - unsigned int pos =3D data->hwirq; + unsigned int pos =3D irqd_to_hwirq(data); =20 + gpiochip_enable_irq(gc, pos); mcp_set_bit(mcp, MCP_GPINTEN, pos, true); } =20 @@ -454,7 +457,7 @@ static int mcp23s08_irq_set_type(struct irq_data *data,= unsigned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp =3D gpiochip_get_data(gc); - unsigned int pos =3D data->hwirq; + unsigned int pos =3D irqd_to_hwirq(data); =20 if ((type & IRQ_TYPE_EDGE_BOTH) =3D=3D IRQ_TYPE_EDGE_BOTH) { mcp_set_bit(mcp, MCP_INTCON, pos, false); @@ -523,6 +526,25 @@ static int mcp23s08_irq_setup(struct mcp23s08 *mcp) return 0; } =20 +static void mcp23s08_irq_print_chip(struct irq_data *d, struct seq_file *p) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct mcp23s08 *mcp =3D gpiochip_get_data(gc); + + seq_printf(p, dev_name(mcp->dev)); +} + +static const struct irq_chip mcp23s08_irq_chip =3D { + .irq_mask =3D mcp23s08_irq_mask, + .irq_unmask =3D mcp23s08_irq_unmask, + .irq_set_type =3D mcp23s08_irq_set_type, + .irq_bus_lock =3D mcp23s08_irq_bus_lock, + .irq_bus_sync_unlock =3D mcp23s08_irq_bus_unlock, + .irq_print_chip =3D mcp23s08_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + /*----------------------------------------------------------------------*/ =20 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, @@ -538,12 +560,6 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct de= vice *dev, mcp->addr =3D addr; =20 mcp->irq_active_high =3D false; - mcp->irq_chip.name =3D dev_name(dev); - mcp->irq_chip.irq_mask =3D mcp23s08_irq_mask; - mcp->irq_chip.irq_unmask =3D mcp23s08_irq_unmask; - mcp->irq_chip.irq_set_type =3D mcp23s08_irq_set_type; - mcp->irq_chip.irq_bus_lock =3D mcp23s08_irq_bus_lock; - mcp->irq_chip.irq_bus_sync_unlock =3D mcp23s08_irq_bus_unlock; =20 mcp->chip.direction_input =3D mcp23s08_direction_input; mcp->chip.get =3D mcp23s08_get; @@ -603,7 +619,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct dev= ice *dev, if (mcp->irq && mcp->irq_controller) { struct gpio_irq_chip *girq =3D &mcp->chip.irq; =20 - girq->chip =3D &mcp->irq_chip; + gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; girq->num_parents =3D 0; diff --git a/drivers/pinctrl/pinctrl-mcp23s08.h b/drivers/pinctrl/pinctrl-m= cp23s08.h index b8d15939e0c2..b15516af7783 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.h +++ b/drivers/pinctrl/pinctrl-mcp23s08.h @@ -36,7 +36,6 @@ struct mcp23s08 { struct mutex lock; =20 struct gpio_chip chip; - struct irq_chip irq_chip; =20 struct regmap *regmap; struct device *dev; --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0F30C761A6 for ; Tue, 4 Apr 2023 09:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234386AbjDDJnl (ORCPT ); Tue, 4 Apr 2023 05:43:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234320AbjDDJnd (ORCPT ); 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Tue, 04 Apr 2023 02:43:16 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:09 +0200 Subject: [PATCH 7/9] pinctrl: st: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-7-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. I switched to using irqd_to_hwirq() consistently while we are at it. This driver does not use the GPIOCHIP_IRQ_RESOURCE_HELPERS as it defines its own resource reservations, simply in order to turn IRQ lines into inputs on initialization. Also switched the open coded calls to gpiochip_lock_as_irq() to gpiochip_reqres_irq() so we also get the right module reference counting. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-st.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index 1409339f0279..c1f36b164ea5 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -1313,7 +1313,8 @@ static void st_gpio_irq_mask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct st_gpio_bank *bank =3D gpiochip_get_data(gc); =20 - writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK); + writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_CLR_PMASK); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 static void st_gpio_irq_unmask(struct irq_data *d) @@ -1321,7 +1322,8 @@ static void st_gpio_irq_unmask(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct st_gpio_bank *bank =3D gpiochip_get_data(gc); =20 - writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK); + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + writel(BIT(irqd_to_hwirq(d)), bank->base + REG_PIO_SET_PMASK); } =20 static int st_gpio_irq_request_resources(struct irq_data *d) @@ -1330,14 +1332,14 @@ static int st_gpio_irq_request_resources(struct irq= _data *d) =20 st_gpio_direction_input(gc, d->hwirq); =20 - return gpiochip_lock_as_irq(gc, d->hwirq); + return gpiochip_reqres_irq(gc, d->hwirq); } =20 static void st_gpio_irq_release_resources(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); =20 - gpiochip_unlock_as_irq(gc, d->hwirq); + gpiochip_relres_irq(gc, d->hwirq); } =20 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type) @@ -1492,7 +1494,7 @@ static const struct gpio_chip st_gpio_template =3D { .ngpio =3D ST_GPIO_PINS_PER_BANK, }; =20 -static struct irq_chip st_gpio_irqchip =3D { +static const struct irq_chip st_gpio_irqchip =3D { .name =3D "GPIO", .irq_request_resources =3D st_gpio_irq_request_resources, .irq_release_resources =3D st_gpio_irq_release_resources, @@ -1500,7 +1502,7 @@ static struct irq_chip st_gpio_irqchip =3D { .irq_mask =3D st_gpio_irq_mask, .irq_unmask =3D st_gpio_irq_unmask, .irq_set_type =3D st_gpio_irq_set_type, - .flags =3D IRQCHIP_SKIP_SET_WAKE, + .flags =3D IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, }; =20 static int st_gpiolib_register_bank(struct st_pinctrl *info, @@ -1570,7 +1572,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl= *info, } =20 girq =3D &bank->gpio_chip.irq; - girq->chip =3D &st_gpio_irqchip; + gpio_irq_chip_set_chip(girq, &st_gpio_irqchip); girq->parent_handler =3D st_gpio_irq_handler; girq->num_parents =3D 1; girq->parents =3D devm_kcalloc(dev, 1, sizeof(*girq->parents), --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9841EC761A6 for ; Tue, 4 Apr 2023 09:43:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234374AbjDDJnr (ORCPT ); Tue, 4 Apr 2023 05:43:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234350AbjDDJne (ORCPT ); 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Tue, 04 Apr 2023 02:43:17 -0700 (PDT) From: Linus Walleij Date: Tue, 04 Apr 2023 11:43:10 +0200 Subject: [PATCH 8/9] pinctrl: stmfx: Convert to immutable irq_chip MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-8-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. This driver rolls it's own resource handling and does not use GPIOCHIP_IRQ_RESOURCE_HELPERS. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-stmfx.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmf= x.c index 1181c4b506b1..eba7d8d9c753 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -85,7 +85,6 @@ struct stmfx_pinctrl { struct pinctrl_dev *pctl_dev; struct pinctrl_desc pctl_desc; struct gpio_chip gpio_chip; - struct irq_chip irq_chip; struct mutex lock; /* IRQ bus lock */ unsigned long gpio_valid_mask; /* Cache of IRQ_GPI_* registers for bus_lock */ @@ -427,6 +426,7 @@ static void stmfx_pinctrl_irq_mask(struct irq_data *dat= a) u32 mask =3D get_mask(data->hwirq); =20 pctl->irq_gpi_src[reg] &=3D ~mask; + gpiochip_disable_irq(gpio_chip, irqd_to_hwirq(data)); } =20 static void stmfx_pinctrl_irq_unmask(struct irq_data *data) @@ -436,6 +436,7 @@ static void stmfx_pinctrl_irq_unmask(struct irq_data *d= ata) u32 reg =3D get_reg(data->hwirq); u32 mask =3D get_mask(data->hwirq); =20 + gpiochip_enable_irq(gpio_chip, irqd_to_hwirq(data)); pctl->irq_gpi_src[reg] |=3D mask; } =20 @@ -592,6 +593,26 @@ static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq= , void *dev_id) return IRQ_HANDLED; } =20 +static void stmfx_pinctrl_irq_print_chip(struct irq_data *d, struct seq_fi= le *p) +{ + struct gpio_chip *gpio_chip =3D irq_data_get_irq_chip_data(d); + struct stmfx_pinctrl *pctl =3D gpiochip_get_data(gpio_chip); + + seq_printf(p, dev_name(pctl->dev)); +} + +static const struct irq_chip stmfx_pinctrl_irq_chip =3D { + .irq_mask =3D stmfx_pinctrl_irq_mask, + .irq_unmask =3D stmfx_pinctrl_irq_unmask, + .irq_set_type =3D stmfx_pinctrl_irq_set_type, + .irq_bus_lock =3D stmfx_pinctrl_irq_bus_lock, + .irq_bus_sync_unlock =3D stmfx_pinctrl_irq_bus_sync_unlock, + .irq_request_resources =3D stmfx_gpio_irq_request_resources, + .irq_release_resources =3D stmfx_gpio_irq_release_resources, + .irq_print_chip =3D stmfx_pinctrl_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, +}; + static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) { struct pinctrl_gpio_range *gpio_range; @@ -678,17 +699,8 @@ static int stmfx_pinctrl_probe(struct platform_device = *pdev) pctl->gpio_chip.ngpio =3D pctl->pctl_desc.npins; pctl->gpio_chip.can_sleep =3D true; =20 - pctl->irq_chip.name =3D dev_name(pctl->dev); - pctl->irq_chip.irq_mask =3D stmfx_pinctrl_irq_mask; - pctl->irq_chip.irq_unmask =3D stmfx_pinctrl_irq_unmask; - pctl->irq_chip.irq_set_type =3D stmfx_pinctrl_irq_set_type; - pctl->irq_chip.irq_bus_lock =3D stmfx_pinctrl_irq_bus_lock; - pctl->irq_chip.irq_bus_sync_unlock =3D stmfx_pinctrl_irq_bus_sync_unlock; - pctl->irq_chip.irq_request_resources =3D stmfx_gpio_irq_request_resources; - pctl->irq_chip.irq_release_resources =3D stmfx_gpio_irq_release_resources; - girq =3D &pctl->gpio_chip.irq; - girq->chip =3D &pctl->irq_chip; + gpio_irq_chip_set_chip(girq, &stmfx_pinctrl_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; girq->num_parents =3D 0; @@ -710,7 +722,7 @@ static int stmfx_pinctrl_probe(struct platform_device *= pdev) ret =3D devm_request_threaded_irq(pctl->dev, irq, NULL, stmfx_pinctrl_irq_thread_fn, IRQF_ONESHOT, - pctl->irq_chip.name, pctl); + dev_name(pctl->dev), pctl); if (ret) { dev_err(pctl->dev, "cannot request irq%d\n", irq); return ret; --=20 2.34.1 From nobody Tue Feb 10 23:53:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD251C761A6 for ; Tue, 4 Apr 2023 09:43:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234369AbjDDJno (ORCPT ); Tue, 4 Apr 2023 05:43:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234349AbjDDJne (ORCPT ); Tue, 4 Apr 2023 05:43:34 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C53692D61 for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230403-immutable-irqchips-v1-9-503788a7f6e6@linaro.org> References: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> In-Reply-To: <20230403-immutable-irqchips-v1-0-503788a7f6e6@linaro.org> To: Ray Jui , Scott Branden , Broadcom internal kernel review list , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Patrice Chotard , Maxime Coquelin , Alexandre Torgue Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, linux-stm32@st-md-mailman.stormreply.com, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the driver to immutable irq-chip with a bit of intuition. I switched to consistently using irqd_to_hwirq() consistently while we are at it. As the driver now needs to get the gpio_chip in the .irq_mask and .irq_unmask callbacks, I switched to a pattern where we first fetch the gpio_chip and then the state container from that in two steps. The compiler will do the same thing anyway. Cc: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sx150x.c | 64 +++++++++++++++++++++++-------------= ---- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx1= 50x.c index 0b5ff99641e1..e49c7be2b47b 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -99,7 +99,6 @@ struct sx150x_pinctrl { struct pinctrl_dev *pctldev; struct pinctrl_desc pinctrl_desc; struct gpio_chip gpio; - struct irq_chip irq_chip; struct regmap *regmap; struct { u32 sense; @@ -487,19 +486,21 @@ static int sx150x_gpio_direction_output(struct gpio_c= hip *chip, =20 static void sx150x_irq_mask(struct irq_data *d) { - struct sx150x_pinctrl *pctl =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - unsigned int n =3D d->hwirq; + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct sx150x_pinctrl *pctl =3D gpiochip_get_data(gc); + unsigned int n =3D irqd_to_hwirq(d); =20 pctl->irq.masked |=3D BIT(n); + gpiochip_disable_irq(gc, n); } =20 static void sx150x_irq_unmask(struct irq_data *d) { - struct sx150x_pinctrl *pctl =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); - unsigned int n =3D d->hwirq; + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct sx150x_pinctrl *pctl =3D gpiochip_get_data(gc); + unsigned int n =3D irqd_to_hwirq(d); =20 + gpiochip_enable_irq(gc, n); pctl->irq.masked &=3D ~BIT(n); } =20 @@ -520,14 +521,14 @@ static void sx150x_irq_set_sense(struct sx150x_pinctr= l *pctl, =20 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) { - struct sx150x_pinctrl *pctl =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct sx150x_pinctrl *pctl =3D gpiochip_get_data(gc); unsigned int n, val =3D 0; =20 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) return -EINVAL; =20 - n =3D d->hwirq; + n =3D irqd_to_hwirq(d); =20 if (flow_type & IRQ_TYPE_EDGE_RISING) val |=3D SX150X_IRQ_TYPE_EDGE_RISING; @@ -562,22 +563,42 @@ static irqreturn_t sx150x_irq_thread_fn(int irq, void= *dev_id) =20 static void sx150x_irq_bus_lock(struct irq_data *d) { - struct sx150x_pinctrl *pctl =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct sx150x_pinctrl *pctl =3D gpiochip_get_data(gc); =20 mutex_lock(&pctl->lock); } =20 static void sx150x_irq_bus_sync_unlock(struct irq_data *d) { - struct sx150x_pinctrl *pctl =3D - gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct sx150x_pinctrl *pctl =3D gpiochip_get_data(gc); =20 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked); regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense); mutex_unlock(&pctl->lock); } =20 + +static void sx150x_irq_print_chip(struct irq_data *d, struct seq_file *p) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct sx150x_pinctrl *pctl =3D gpiochip_get_data(gc); + + seq_printf(p, pctl->client->name); +} + +static const struct irq_chip sx150x_irq_chip =3D { + .irq_mask =3D sx150x_irq_mask, + .irq_unmask =3D sx150x_irq_unmask, + .irq_set_type =3D sx150x_irq_set_type, + .irq_bus_lock =3D sx150x_irq_bus_lock, + .irq_bus_sync_unlock =3D sx150x_irq_bus_sync_unlock, + .irq_print_chip =3D sx150x_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pi= n, unsigned long *config) { @@ -1181,19 +1202,8 @@ static int sx150x_probe(struct i2c_client *client) if (client->irq > 0) { struct gpio_irq_chip *girq; =20 - pctl->irq_chip.irq_mask =3D sx150x_irq_mask; - pctl->irq_chip.irq_unmask =3D sx150x_irq_unmask; - pctl->irq_chip.irq_set_type =3D sx150x_irq_set_type; - pctl->irq_chip.irq_bus_lock =3D sx150x_irq_bus_lock; - pctl->irq_chip.irq_bus_sync_unlock =3D sx150x_irq_bus_sync_unlock; - pctl->irq_chip.name =3D devm_kstrdup(dev, client->name, - GFP_KERNEL); - if (!pctl->irq_chip.name) - return -ENOMEM; - pctl->irq.masked =3D ~0; pctl->irq.sense =3D 0; - /* * Because sx150x_irq_threaded_fn invokes all of the * nested interrupt handlers via handle_nested_irq, @@ -1206,7 +1216,7 @@ static int sx150x_probe(struct i2c_client *client) * called (should not happen) */ girq =3D &pctl->gpio.irq; - girq->chip =3D &pctl->irq_chip; + gpio_irq_chip_set_chip(girq, &sx150x_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; girq->num_parents =3D 0; @@ -1219,7 +1229,7 @@ static int sx150x_probe(struct i2c_client *client) sx150x_irq_thread_fn, IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_FALLING, - pctl->irq_chip.name, pctl); + client->name, pctl); if (ret < 0) return ret; } --=20 2.34.1