From nobody Mon Feb 9 16:01:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A333AC7619A for ; Sun, 2 Apr 2023 09:51:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbjDBJv3 (ORCPT ); Sun, 2 Apr 2023 05:51:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjDBJvX (ORCPT ); Sun, 2 Apr 2023 05:51:23 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A7B15B8D; Sun, 2 Apr 2023 02:51:13 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 28108660312D; Sun, 2 Apr 2023 10:51:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680429072; bh=VEHW/c/2s4Nzddue0SQRQN8yI6FlgApEF6XFoJ9BplU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vx8WEjF2lA7GED+2VC23ZSYMdFobqU6uXTqxv01t8b6pc6fuoRjKnC3wlmrGV9Rna A2NEmDM81oWgSfprFVwTY/kwcnTT5+t6RMfreeRP8NRT3J7mhtJhDMNwDWyvk1K+s8 QtISG3TuVBmYCr3OMa+eAX6DAQD7QyIVi2p8ZCjSenNr6piCSoOX0jQw9IPR4e+uzT FngRE128Fc1XhUzQuu2EWFg+QriyzKuyE/FUnfT0Cxee/llX4UcQa1J7HtU9aYlXMy yj6E2U4NMhLAkq0xWyfIvIBRQR+lQ+JWZlP6WuHlrqXZpRHlD/dDim1JQo8QuRHT5o 8HPGl7Y9OiVbw== From: Cristian Ciocaltea To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sugar Zhang , Jagan Teki , Kever Yang , Elaine Zhang , Nicolas Frattaroli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 4/5] arm64: dts: rockchip: rk3588: Add I2S nodes Date: Sun, 2 Apr 2023 12:50:53 +0300 Message-Id: <20230402095054.384739-5-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> References: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides another group of four I2S/PCM/TDM controllers. Add the DT nodes corresponding to the additional controllers. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index d085e57fbc4c..8be75556af8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,74 @@ #include "rk3588-pinctrl.dtsi" =20 / { + i2s8_8ch: i2s@fddc8000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddc8000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_= I2S8_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 22>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO0>; + resets =3D <&cru SRST_M_I2S8_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddf4000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_= I2S6_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 4>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S6_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddf8000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_= I2S7_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 21>; + dma-names =3D "rx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S7_8CH_RX>; + reset-names =3D "rx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfde00000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCL= K_I2S10_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 24>; + dma-names =3D "rx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S10_8CH_RX>; + reset-names =3D "rx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + gmac0: ethernet@fe1b0000 { compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg =3D <0x0 0xfe1b0000 0x0 0x10000>; --=20 2.40.0