From nobody Mon Feb 9 21:37:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DA6AC77B60 for ; Sun, 2 Apr 2023 09:51:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230270AbjDBJvR (ORCPT ); Sun, 2 Apr 2023 05:51:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjDBJvL (ORCPT ); Sun, 2 Apr 2023 05:51:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B59605FF9; Sun, 2 Apr 2023 02:51:09 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 658BD660312B; Sun, 2 Apr 2023 10:51:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680429068; bh=XO/BROgu9s186EZyA4Y0THzEjWTcDSJbUQnZjuYVoLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VaYy3P1c5C4yOiVjw4jLJMVn6oiNQLeU6vIS3veMtCPgK//cvJXZe7EjMFPQ6yWkk UwnKKjqIBRn7tj2zhPtm9gIE66LX+ORhkyhVP76/mImhtBsENGXLLoQRGG26ujSjpa Vrzu8CUkcfGd74qgJnz5vWHX5UR3lB8N/A1I8W1Atf6jEjTbPi5P34aswjDV8qqAjL JJ5THpKvVrh24ccUgNEMfDbuyIilxrdb3/D+cOle4/7RXRK5Ji1QlJ6pMlwgvBCl7p FyiI7RCD9113eBy/D0pzcIdUrnFqIu3q0wBzr7AUu1/QFWZ3ut7shhUdhXTyqMLx1r RKzmoDWUvwUqg== From: Cristian Ciocaltea To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sugar Zhang , Jagan Teki , Kever Yang , Elaine Zhang , Nicolas Frattaroli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 3/5] arm64: dts: rockchip: rk3588s: Add I2S nodes Date: Sun, 2 Apr 2023 12:50:52 +0300 Message-Id: <20230402095054.384739-4-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> References: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are five I2S/PCM/TDM controllers and two I2S/PCM controllers embedded in the RK3588 and RK3588S SoCs. Add the DT nodes corresponding to the above mentioned Rockchip controllers. Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers, which are handled via a separate patch. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 148 ++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index e3546cfacc88..cabf1cfe208e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -821,6 +821,57 @@ power-domain@RK3588_PD_SDMMC { }; }; =20 + i2s4_8ch: i2s@fddc0000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddc0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_= I2S4_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 0>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO0>; + resets =3D <&cru SRST_M_I2S4_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddf0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_= I2S5_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 2>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S5_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddfc000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_= I2S9_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 23>; + dma-names =3D "rx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S9_8CH_RX>; + reset-names =3D "rx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + qos_gpu_m0: qos@fdf35000 { compatible =3D "rockchip,rk3588-qos", "syscon"; reg =3D <0x0 0xfdf35000 0x0 0x20>; @@ -1143,6 +1194,103 @@ sdhci: mmc@fe2e0000 { status =3D "disabled"; }; =20 + i2s0_8ch: i2s@fe470000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfe470000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_= I2S0_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SR= C>; + assigned-clock-parents =3D <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas =3D <&dmac0 0>, <&dmac0 1>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3588_PD_AUDIO>; + resets =3D <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names =3D "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfe480000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_= I2S1_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + dmas =3D <&dmac0 2>, <&dmac0 3>; + dma-names =3D "tx", "rx"; + resets =3D <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names =3D "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible =3D "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg =3D <0x0 0xfe490000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names =3D "i2s_clk", "i2s_hclk"; + assigned-clocks =3D <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac1 0>, <&dmac1 1>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible =3D "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg =3D <0x0 0xfe4a0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names =3D "i2s_clk", "i2s_hclk"; + assigned-clocks =3D <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac1 2>, <&dmac1 3>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0xfe600000 0 0x10000>, /* GICD */ --=20 2.40.0