From nobody Sun Feb 8 15:42:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2B30C76196 for ; Sun, 2 Apr 2023 09:51:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230288AbjDBJvK (ORCPT ); Sun, 2 Apr 2023 05:51:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230218AbjDBJvF (ORCPT ); Sun, 2 Apr 2023 05:51:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6665059E8; Sun, 2 Apr 2023 02:51:04 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id CF83D660312D; Sun, 2 Apr 2023 10:51:02 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680429063; bh=SvocWMiVjKrI7HollcLDxvyJtaFIB6bgp0o82PWqs70=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QIo9uK7+AH7ROGJvnguRB1/dtbxQviEQzGpzG1Y6HUMwCYqSyeiMJr8qk5c3+sT64 M/8o4CFuIfXFDXhARCPHDoGq9beaSCPe55liYqH7R5NuZ5iebo+DJvvvawDU4qqHK4 7/wiPV/7IIeX3f0vX8dggrqWSZarwAejtu03J2ouqKjPnoMMr/rYcAhgPiEXzuD4Hm Yy26n7XIWbt/jLt7GsGyPiBJpoHqjgn58zyXUIcBTI2GKU/8qmUxwvc00iT7QY7g5E 2W11StE3PCPPTHsMeWc3IVukwpgaZosXovx0aHLeoPoZv0CNtYN5neJ0epyoJut/RJ kAuLb0Sbcrqfg== From: Cristian Ciocaltea To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sugar Zhang , Jagan Teki , Kever Yang , Elaine Zhang , Nicolas Frattaroli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel Subject: [PATCH v4 1/5] arm64: dts: rockchip: rk3588s: Fix SCMI assigned clocks Date: Sun, 2 Apr 2023 12:50:50 +0300 Message-Id: <20230402095054.384739-2-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> References: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since commit df4fdd0db475 ("dt-bindings: firmware: arm,scmi: Restrict protocol child node properties") the following dtbs_check warning is shown: rk3588-rock-5b.dtb: scmi: protocol@14: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) Because adding the missing properties to firmware/arm,scmi.yaml binding document was not an acceptable solution, move SCMI_CLK_CPUB01 and SCMI_CLK_CPUB23 assigned clocks to the related CPU nodes and also add the missing SCMI_CLK_CPUL. Additionally, adjust frequency to 816 MHz for all the above mentioned assigned clocks, in order to match the firmware defaults. Suggested-by: Sebastian Reichel Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 7840767dfcd8..028dc62f63ce 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -60,6 +60,8 @@ cpu_l0: cpu@0 { enable-method =3D "psci"; capacity-dmips-mhz =3D <530>; clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates =3D <816000000>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <32768>; i-cache-line-size =3D <64>; @@ -136,6 +138,8 @@ cpu_b0: cpu@400 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates =3D <816000000>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -174,6 +178,8 @@ cpu_b2: cpu@600 { enable-method =3D "psci"; capacity-dmips-mhz =3D <1024>; clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates =3D <816000000>; cpu-idle-states =3D <&CPU_SLEEP>; i-cache-size =3D <65536>; i-cache-line-size =3D <64>; @@ -313,10 +319,6 @@ scmi: scmi { =20 scmi_clk: protocol@14 { reg =3D <0x14>; - assigned-clocks =3D <&scmi_clk SCMI_CLK_CPUB01>, - <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates =3D <1200000000>, - <1200000000>; #clock-cells =3D <1>; }; =20 --=20 2.40.0 From nobody Sun Feb 8 15:42:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7030AC76196 for ; Sun, 2 Apr 2023 09:51:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbjDBJvP (ORCPT ); Sun, 2 Apr 2023 05:51:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230248AbjDBJvH (ORCPT ); Sun, 2 Apr 2023 05:51:07 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED7347EDB; Sun, 2 Apr 2023 02:51:06 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id AA5BE660313D; Sun, 2 Apr 2023 10:51:05 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680429065; bh=otwKTZ+LUzkWr51HoDAAyTXvgoa041tRNRUmqfxmfo4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DpvJMONWIUvQWf/Pz9uUmvEgABMS/2S1rppOj3+jUUu39V/rxYeVArTa5QS46wSpd I0m6Lz60eeCxZ3/lP3LNl5lRLSEwa18qlhLe0NW/JiL+fIfREKsF6x/xrWcI7AsWHt ROV6ZYdp9OVgx8AN2hhdEneFJHqQ8X7tqHLNPkpNRZoMZUqBXevDS5Sw2e1il/LI3X rZyyHWa7zIzAVAXtYVTOMCpT0GvdutwRXbEw2wveUj7voH8ZTuE8SxCMHS/RMucY28 wToN5ELgGariQp6SHSaT3874opD0gZUJ+WurAoZgYGLgR4iVYIO9nrpPt/46JrWB9s bj/fVoSisjGLA== From: Cristian Ciocaltea To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sugar Zhang , Jagan Teki , Kever Yang , Elaine Zhang , Nicolas Frattaroli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Sebastian Reichel Subject: [PATCH v4 2/5] arm64: dts: rockchip: rk3588s: Assign PLL_PPLL clock rate to 1.1 GHz Date: Sun, 2 Apr 2023 12:50:51 +0300 Message-Id: <20230402095054.384739-3-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> References: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz instead of 1.1 GHz. Fix it. Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC") Reported-by: Sebastian Reichel Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 028dc62f63ce..e3546cfacc88 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -425,7 +425,7 @@ cru: clock-controller@fd7c0000 { <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates =3D - <100000000>, <786432000>, + <1100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>, --=20 2.40.0 From nobody Sun Feb 8 15:42:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DA6AC77B60 for ; Sun, 2 Apr 2023 09:51:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230270AbjDBJvR (ORCPT ); Sun, 2 Apr 2023 05:51:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjDBJvL (ORCPT ); Sun, 2 Apr 2023 05:51:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B59605FF9; Sun, 2 Apr 2023 02:51:09 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 658BD660312B; Sun, 2 Apr 2023 10:51:08 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680429068; bh=XO/BROgu9s186EZyA4Y0THzEjWTcDSJbUQnZjuYVoLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VaYy3P1c5C4yOiVjw4jLJMVn6oiNQLeU6vIS3veMtCPgK//cvJXZe7EjMFPQ6yWkk UwnKKjqIBRn7tj2zhPtm9gIE66LX+ORhkyhVP76/mImhtBsENGXLLoQRGG26ujSjpa Vrzu8CUkcfGd74qgJnz5vWHX5UR3lB8N/A1I8W1Atf6jEjTbPi5P34aswjDV8qqAjL JJ5THpKvVrh24ccUgNEMfDbuyIilxrdb3/D+cOle4/7RXRK5Ji1QlJ6pMlwgvBCl7p FyiI7RCD9113eBy/D0pzcIdUrnFqIu3q0wBzr7AUu1/QFWZ3ut7shhUdhXTyqMLx1r RKzmoDWUvwUqg== From: Cristian Ciocaltea To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sugar Zhang , Jagan Teki , Kever Yang , Elaine Zhang , Nicolas Frattaroli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 3/5] arm64: dts: rockchip: rk3588s: Add I2S nodes Date: Sun, 2 Apr 2023 12:50:52 +0300 Message-Id: <20230402095054.384739-4-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> References: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are five I2S/PCM/TDM controllers and two I2S/PCM controllers embedded in the RK3588 and RK3588S SoCs. Add the DT nodes corresponding to the above mentioned Rockchip controllers. Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers, which are handled via a separate patch. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 148 ++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index e3546cfacc88..cabf1cfe208e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -821,6 +821,57 @@ power-domain@RK3588_PD_SDMMC { }; }; =20 + i2s4_8ch: i2s@fddc0000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddc0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_= I2S4_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 0>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO0>; + resets =3D <&cru SRST_M_I2S4_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddf0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_= I2S5_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 2>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S5_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddfc000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_= I2S9_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 23>; + dma-names =3D "rx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S9_8CH_RX>; + reset-names =3D "rx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + qos_gpu_m0: qos@fdf35000 { compatible =3D "rockchip,rk3588-qos", "syscon"; reg =3D <0x0 0xfdf35000 0x0 0x20>; @@ -1143,6 +1194,103 @@ sdhci: mmc@fe2e0000 { status =3D "disabled"; }; =20 + i2s0_8ch: i2s@fe470000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfe470000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_= I2S0_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SR= C>; + assigned-clock-parents =3D <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas =3D <&dmac0 0>, <&dmac0 1>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3588_PD_AUDIO>; + resets =3D <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names =3D "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfe480000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_= I2S1_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + dmas =3D <&dmac0 2>, <&dmac0 3>; + dma-names =3D "tx", "rx"; + resets =3D <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names =3D "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible =3D "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg =3D <0x0 0xfe490000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names =3D "i2s_clk", "i2s_hclk"; + assigned-clocks =3D <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac1 0>, <&dmac1 1>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible =3D "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg =3D <0x0 0xfe4a0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names =3D "i2s_clk", "i2s_hclk"; + assigned-clocks =3D <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac1 2>, <&dmac1 3>; + dma-names =3D "tx", "rx"; + power-domains =3D <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0xfe600000 0 0x10000>, /* GICD */ --=20 2.40.0 From nobody Sun Feb 8 15:42:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A333AC7619A for ; Sun, 2 Apr 2023 09:51:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbjDBJv3 (ORCPT ); Sun, 2 Apr 2023 05:51:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjDBJvX (ORCPT ); Sun, 2 Apr 2023 05:51:23 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A7B15B8D; Sun, 2 Apr 2023 02:51:13 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 28108660312D; Sun, 2 Apr 2023 10:51:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680429072; bh=VEHW/c/2s4Nzddue0SQRQN8yI6FlgApEF6XFoJ9BplU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vx8WEjF2lA7GED+2VC23ZSYMdFobqU6uXTqxv01t8b6pc6fuoRjKnC3wlmrGV9Rna A2NEmDM81oWgSfprFVwTY/kwcnTT5+t6RMfreeRP8NRT3J7mhtJhDMNwDWyvk1K+s8 QtISG3TuVBmYCr3OMa+eAX6DAQD7QyIVi2p8ZCjSenNr6piCSoOX0jQw9IPR4e+uzT FngRE128Fc1XhUzQuu2EWFg+QriyzKuyE/FUnfT0Cxee/llX4UcQa1J7HtU9aYlXMy yj6E2U4NMhLAkq0xWyfIvIBRQR+lQ+JWZlP6WuHlrqXZpRHlD/dDim1JQo8QuRHT5o 8HPGl7Y9OiVbw== From: Cristian Ciocaltea To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sugar Zhang , Jagan Teki , Kever Yang , Elaine Zhang , Nicolas Frattaroli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 4/5] arm64: dts: rockchip: rk3588: Add I2S nodes Date: Sun, 2 Apr 2023 12:50:53 +0300 Message-Id: <20230402095054.384739-5-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> References: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides another group of four I2S/PCM/TDM controllers. Add the DT nodes corresponding to the additional controllers. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index d085e57fbc4c..8be75556af8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,74 @@ #include "rk3588-pinctrl.dtsi" =20 / { + i2s8_8ch: i2s@fddc8000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddc8000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_= I2S8_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 22>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO0>; + resets =3D <&cru SRST_M_I2S8_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddf4000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_= I2S6_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 4>; + dma-names =3D "tx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S6_8CH_TX>; + reset-names =3D "tx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfddf8000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_= I2S7_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 21>; + dma-names =3D "rx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S7_8CH_RX>; + reset-names =3D "rx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible =3D "rockchip,rk3588-i2s-tdm"; + reg =3D <0x0 0xfde00000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCL= K_I2S10_8CH>; + clock-names =3D "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks =3D <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents =3D <&cru PLL_AUPLL>; + dmas =3D <&dmac2 24>; + dma-names =3D "rx"; + power-domains =3D <&power RK3588_PD_VO1>; + resets =3D <&cru SRST_M_I2S10_8CH_RX>; + reset-names =3D "rx-m"; + #sound-dai-cells =3D <0>; + status =3D "disabled"; + }; + gmac0: ethernet@fe1b0000 { compatible =3D "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg =3D <0x0 0xfe1b0000 0x0 0x10000>; --=20 2.40.0 From nobody Sun Feb 8 15:42:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4E9EC7619A for ; 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d=collabora.com; s=mail; t=1680429075; bh=kJdtSesynjBrpuEEDEDtpj5X9IcAxkUH0Y/1s8Txv6c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VPVs0DcGUSDRxbBrFcdRhMjqt8jtEg5eb28bos+eF5kpI1VDZqZ+dhsFH6buDdKEF WRtsAa5DN849V5kQTAZqh5CSiBloB8WjFuyNhoQOPhwCLtLqjX41p9uS7ig9l+0g7O x+YMryXdGC068oBI9C4vV1pMHo2HR7hpKbgZrM6yfoRb55Oh08or6wydCW73SySoDl wI6DD6mb+GWdIwzNpGS3MsuMEvfsi3FV4pI4887sWayoBH6bMHxmvqRZH22yVcpoGN b9Wwd9LRONXwRIlWMy0iTmmYe3yohpbl5kNze3lBsMqTI2caZkP7C2rUdnPF9IMStE xba9WMu6jAwSg== From: Cristian Ciocaltea To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Sugar Zhang , Jagan Teki , Kever Yang , Elaine Zhang , Nicolas Frattaroli Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v4 5/5] arm64: dts: rockchip: rk3588-rock-5b: Add analog audio Date: Sun, 2 Apr 2023 12:50:54 +0300 Message-Id: <20230402095054.384739-6-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> References: <20230402095054.384739-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary DT nodes for the Rock 5B board to enable the analog audio support provided by the Everest Semi ES8316 codec. Signed-off-by: Cristian Ciocaltea Reviewed-by: Christopher Obbard --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/b= oot/dts/rockchip/rk3588-rock-5b.dts index 95805cb0adfa..a9e12e098d48 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -2,6 +2,7 @@ =20 /dts-v1/; =20 +#include #include "rk3588.dtsi" =20 / { @@ -17,6 +18,23 @@ chosen { stdout-path =3D "serial2:1500000n8"; }; =20 + sound { + compatible =3D "audio-graph-card"; + label =3D "Analog"; + + widgets =3D "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing =3D "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais =3D <&i2s0_8ch_p0>; + hp-det-gpio =3D <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hp_detect>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vcc5v0_sys"; @@ -27,6 +45,50 @@ vcc5v0_sys: vcc5v0-sys-regulator { }; }; =20 +&i2c7 { + status =3D "okay"; + + es8316: es8316@11 { + compatible =3D "everest,es8316"; + reg =3D <0x11>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + clock-names =3D "mclk"; + #sound-dai-cells =3D <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint =3D <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format =3D "i2s"; + mclk-fs =3D <256>; + remote-endpoint =3D <&es8316_p0_0>; + }; + }; +}; + +&pinctrl { + sound { + hp_detect: hp-detect { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + &sdhci { bus-width =3D <8>; no-sdio; --=20 2.40.0