From nobody Wed Sep 10 09:08:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAF1CC6FD1D for ; Sat, 1 Apr 2023 11:20:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229588AbjDALUE convert rfc822-to-8bit (ORCPT ); Sat, 1 Apr 2023 07:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229810AbjDALTu (ORCPT ); Sat, 1 Apr 2023 07:19:50 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A616420339; Sat, 1 Apr 2023 04:19:48 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 4C0E524E094; Sat, 1 Apr 2023 19:19:47 +0800 (CST) Received: from EXMBX172.cuchost.com (172.16.6.92) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sat, 1 Apr 2023 19:19:47 +0800 Received: from ubuntu.localdomain (113.72.144.76) by EXMBX172.cuchost.com (172.16.6.92) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Sat, 1 Apr 2023 19:19:46 +0800 From: Hal Feng To: , , CC: Stephen Boyd , Michael Turquette , Philipp Zabel , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , "Palmer Dabbelt" , Paul Walmsley , Albert Ou , Ben Dooks , "Daniel Lezcano" , Thomas Gleixner , Marc Zyngier , Emil Renner Berthing , Hal Feng , Subject: [PATCH v7 10/22] reset: starfive: Extract the common JH71X0 reset code Date: Sat, 1 Apr 2023 19:19:22 +0800 Message-ID: <20230401111934.130844-11-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230401111934.130844-1-hal.feng@starfivetech.com> References: <20230401111934.130844-1-hal.feng@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.76] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX172.cuchost.com (172.16.6.92) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Emil Renner Berthing Extract the common JH71X0 reset code for reusing them to support JH7110 SoC. Tested-by: Tommaso Merciai Reviewed-by: Conor Dooley Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng --- .../reset/starfive/reset-starfive-jh7100.c | 49 ++++++++++++ .../reset/starfive/reset-starfive-jh71x0.c | 76 ++++++------------- .../reset/starfive/reset-starfive-jh71x0.h | 5 +- 3 files changed, 76 insertions(+), 54 deletions(-) diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset= /starfive/reset-starfive-jh7100.c index 5a68327c1f6a..9d7cb4ed8869 100644 --- a/drivers/reset/starfive/reset-starfive-jh7100.c +++ b/drivers/reset/starfive/reset-starfive-jh7100.c @@ -10,6 +10,55 @@ =20 #include "reset-starfive-jh71x0.h" =20 +#include + +/* register offsets */ +#define JH7100_RESET_ASSERT0 0x00 +#define JH7100_RESET_ASSERT1 0x04 +#define JH7100_RESET_ASSERT2 0x08 +#define JH7100_RESET_ASSERT3 0x0c +#define JH7100_RESET_STATUS0 0x10 +#define JH7100_RESET_STATUS1 0x14 +#define JH7100_RESET_STATUS2 0x18 +#define JH7100_RESET_STATUS3 0x1c + +/* + * Writing a 1 to the n'th bit of the m'th ASSERT register asserts + * line 32m + n, and writing a 0 deasserts the same line. + * Most reset lines have their status inverted so a 0 bit in the STATUS + * register means the line is asserted and a 1 means it's deasserted. A few + * lines don't though, so store the expected value of the status registers= when + * all lines are asserted. + */ +static const u64 jh7100_reset_asserted[2] =3D { + /* STATUS0 */ + BIT_ULL_MASK(JH7100_RST_U74) | + BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | + BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | + /* STATUS1 */ + BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | + BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), + /* STATUS2 */ + BIT_ULL_MASK(JH7100_RST_E24) | + /* STATUS3 */ + 0, +}; + +static int __init jh7100_reset_probe(struct platform_device *pdev) +{ + void __iomem *base =3D devm_platform_ioremap_resource(pdev, 0); + + if (IS_ERR(base)) + return PTR_ERR(base); + + return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node, + base + JH7100_RESET_ASSERT0, + base + JH7100_RESET_STATUS0, + jh7100_reset_asserted, + JH7100_RSTN_END, + THIS_MODULE); +} + static const struct of_device_id jh7100_reset_dt_ids[] =3D { { .compatible =3D "starfive,jh7100-reset" }, { /* sentinel */ } diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset= /starfive/reset-starfive-jh71x0.c index 114a13c4b8a6..3577444a89c6 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.c +++ b/drivers/reset/starfive/reset-starfive-jh71x0.c @@ -10,51 +10,18 @@ #include #include #include -#include #include #include =20 #include "reset-starfive-jh71x0.h" =20 -#include - -/* register offsets */ -#define JH7100_RESET_ASSERT0 0x00 -#define JH7100_RESET_ASSERT1 0x04 -#define JH7100_RESET_ASSERT2 0x08 -#define JH7100_RESET_ASSERT3 0x0c -#define JH7100_RESET_STATUS0 0x10 -#define JH7100_RESET_STATUS1 0x14 -#define JH7100_RESET_STATUS2 0x18 -#define JH7100_RESET_STATUS3 0x1c - -/* - * Writing a 1 to the n'th bit of the m'th ASSERT register asserts - * line 32m + n, and writing a 0 deasserts the same line. - * Most reset lines have their status inverted so a 0 bit in the STATUS - * register means the line is asserted and a 1 means it's deasserted. A few - * lines don't though, so store the expected value of the status registers= when - * all lines are asserted. - */ -static const u64 jh7100_reset_asserted[2] =3D { - /* STATUS0 */ - BIT_ULL_MASK(JH7100_RST_U74) | - BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | - BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | - /* STATUS1 */ - BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | - BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), - /* STATUS2 */ - BIT_ULL_MASK(JH7100_RST_E24) | - /* STATUS3 */ - 0, -}; - struct jh7100_reset { struct reset_controller_dev rcdev; /* protect registers against concurrent read-modify-write */ spinlock_t lock; - void __iomem *base; + void __iomem *assert; + void __iomem *status; + const u64 *asserted; }; =20 static inline struct jh7100_reset * @@ -69,9 +36,9 @@ static int jh7100_reset_update(struct reset_controller_de= v *rcdev, struct jh7100_reset *data =3D jh7100_reset_from(rcdev); unsigned long offset =3D BIT_ULL_WORD(id); u64 mask =3D BIT_ULL_MASK(id); - void __iomem *reg_assert =3D data->base + JH7100_RESET_ASSERT0 + offset *= sizeof(u64); - void __iomem *reg_status =3D data->base + JH7100_RESET_STATUS0 + offset *= sizeof(u64); - u64 done =3D jh7100_reset_asserted[offset] & mask; + void __iomem *reg_assert =3D data->assert + offset * sizeof(u64); + void __iomem *reg_status =3D data->status + offset * sizeof(u64); + u64 done =3D data->asserted ? data->asserted[offset] & mask : 0; u64 value; unsigned long flags; int ret; @@ -125,10 +92,10 @@ static int jh7100_reset_status(struct reset_controller= _dev *rcdev, struct jh7100_reset *data =3D jh7100_reset_from(rcdev); unsigned long offset =3D BIT_ULL_WORD(id); u64 mask =3D BIT_ULL_MASK(id); - void __iomem *reg_status =3D data->base + JH7100_RESET_STATUS0 + offset *= sizeof(u64); + void __iomem *reg_status =3D data->status + offset * sizeof(u64); u64 value =3D readq(reg_status); =20 - return !((value ^ jh7100_reset_asserted[offset]) & mask); + return !((value ^ data->asserted[offset]) & mask); } =20 static const struct reset_control_ops jh7100_reset_ops =3D { @@ -138,25 +105,28 @@ static const struct reset_control_ops jh7100_reset_op= s =3D { .status =3D jh7100_reset_status, }; =20 -int jh7100_reset_probe(struct platform_device *pdev) +int reset_starfive_jh7100_register(struct device *dev, struct device_node = *of_node, + void __iomem *assert, void __iomem *status, + const u64 *asserted, unsigned int nr_resets, + struct module *owner) { struct jh7100_reset *data; =20 - data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; =20 - data->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(data->base)) - return PTR_ERR(data->base); - data->rcdev.ops =3D &jh7100_reset_ops; - data->rcdev.owner =3D THIS_MODULE; - data->rcdev.nr_resets =3D JH7100_RSTN_END; - data->rcdev.dev =3D &pdev->dev; - data->rcdev.of_node =3D pdev->dev.of_node; + data->rcdev.owner =3D owner; + data->rcdev.nr_resets =3D nr_resets; + data->rcdev.dev =3D dev; + data->rcdev.of_node =3D of_node; + spin_lock_init(&data->lock); + data->assert =3D assert; + data->status =3D status; + data->asserted =3D asserted; =20 - return devm_reset_controller_register(&pdev->dev, &data->rcdev); + return devm_reset_controller_register(dev, &data->rcdev); } -EXPORT_SYMBOL_GPL(jh7100_reset_probe); +EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register); diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset= /starfive/reset-starfive-jh71x0.h index 318d7a0e096a..1fc5a648c8d8 100644 --- a/drivers/reset/starfive/reset-starfive-jh71x0.h +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h @@ -6,6 +6,9 @@ #ifndef __RESET_STARFIVE_JH71X0_H #define __RESET_STARFIVE_JH71X0_H =20 -int jh7100_reset_probe(struct platform_device *pdev); +int reset_starfive_jh7100_register(struct device *dev, struct device_node = *of_node, + void __iomem *assert, void __iomem *status, + const u64 *asserted, unsigned int nr_resets, + struct module *owner); =20 #endif /* __RESET_STARFIVE_JH71X0_H */ --=20 2.38.1