From nobody Wed Feb 11 02:06:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2505C6FD1D for ; Sat, 1 Apr 2023 06:37:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233250AbjDAGhP (ORCPT ); Sat, 1 Apr 2023 02:37:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233283AbjDAGhK (ORCPT ); Sat, 1 Apr 2023 02:37:10 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DBA11D86D for ; Fri, 31 Mar 2023 23:37:08 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id D459421A1E; Sat, 1 Apr 2023 06:37:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331026; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7+r4owlpRl68SnHTZez3F/1Q0HJdHfyMYOiLaES+G08=; b=IeBqVbmIMhtC5DMJs1CgV3RogvScaXZSq6C0oCoJUDt5DzNA78qzAcxx+++u6Jic+OWjMf ccxznvwrrJc41E+ot9pBd551crYP+rPHKnjKc6DoRVG55r8D7+H7NEFWXB+AY571usGbuN tnGZH9Qvi4hzt1Y0V63R1R+2jZinsto= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 92D9B134FB; Sat, 1 Apr 2023 06:37:06 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id KxKEIhLRJ2QcdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:06 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 02/15] x86/mtrr: optimize mtrr_calc_physbits() Date: Sat, 1 Apr 2023 08:36:39 +0200 Message-Id: <20230401063652.23522-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Optimize mtrr_calc_physbits() for better readability. Drop a stale comment, as reality has made it obsolete. [ bp: - s/mtrr/MTRR/ - s/boot_cpu_has/cpu_feature_enabled/ - use GENMASK_ULL - simplify. ] Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov (AMD) Tested-by: Michael Kelley --- V3: - new patch, split off from previous patch (Boris Petkov) V5: - add some modifications by Boris Petkov --- arch/x86/kernel/cpu/mtrr/mtrr.c | 27 +++++++-------------------- 1 file changed, 7 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 8310bdb111d0..ce0b82209ad3 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -619,8 +619,6 @@ static struct syscore_ops mtrr_syscore_ops =3D { =20 int __initdata changed_by_mtrr_cleanup; =20 -#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) - static unsigned int __init mtrr_calc_physbits(bool generic) { unsigned int phys_addr; @@ -628,15 +626,8 @@ static unsigned int __init mtrr_calc_physbits(bool gen= eric) phys_addr =3D 32; =20 if (generic) { - size_or_mask =3D SIZE_OR_MASK_BITS(36); - size_and_mask =3D 0x00f00000; phys_addr =3D 36; =20 - /* - * This is an AMD specific MSR, but we assume(hope?) that - * Intel will implement it too when they extend the address - * bus of the Xeon. - */ if (cpuid_eax(0x80000000) >=3D 0x80000008) { phys_addr =3D cpuid_eax(0x80000008) & 0xff; /* CPUID workaround for Intel 0F33/0F34 CPU */ @@ -647,41 +638,37 @@ static unsigned int __init mtrr_calc_physbits(bool ge= neric) boot_cpu_data.x86_stepping =3D=3D 0x4)) phys_addr =3D 36; =20 - size_or_mask =3D SIZE_OR_MASK_BITS(phys_addr); - size_and_mask =3D ~size_or_mask & 0xfffff00000ULL; } else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_CENTAUR && boot_cpu_data.x86 =3D=3D 6) { /* * VIA C* family have Intel style MTRRs, * but don't support PAE */ - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; phys_addr =3D 32; } - } else { - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; } =20 + size_or_mask =3D ~GENMASK_ULL(phys_addr - PAGE_SHIFT - 1, 0); + size_and_mask =3D ~size_or_mask & GENMASK_ULL(39, 20); + return phys_addr; } =20 /** - * mtrr_bp_init - initialize mtrrs on the boot CPU + * mtrr_bp_init - initialize MTRRs on the boot CPU * * This needs to be called early; before any of the other CPUs are * initialized (i.e. before smp_init()). - * */ void __init mtrr_bp_init(void) { + bool generic_mtrrs =3D cpu_feature_enabled(X86_FEATURE_MTRR); const char *why =3D "(not available)"; unsigned int phys_addr; =20 - phys_addr =3D mtrr_calc_physbits(boot_cpu_has(X86_FEATURE_MTRR)); + phys_addr =3D mtrr_calc_physbits(generic_mtrrs); =20 - if (boot_cpu_has(X86_FEATURE_MTRR)) { + if (generic_mtrrs) { mtrr_if =3D &generic_mtrr_ops; } else { switch (boot_cpu_data.x86_vendor) { --=20 2.35.3