From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CC5AC77B6C for ; Sat, 1 Apr 2023 06:37:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233273AbjDAGhI (ORCPT ); Sat, 1 Apr 2023 02:37:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233230AbjDAGhG (ORCPT ); Sat, 1 Apr 2023 02:37:06 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90EC51E73B for ; Fri, 31 Mar 2023 23:37:02 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 324471FD78; Sat, 1 Apr 2023 06:37:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331021; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gsM8JG+0YjKpprMSP0WcpLzh0EmtHSX+OEFp6YWu4DY=; b=g8DLE9Ug7PYEkqHVYmdV+X8Cg3YN7OhOO2THjBCiMltqzaduccgavEz5vuQLMoxChKwp7O qiXUoviI00yYbavx/BgEsUy+5Y3Kx9swildIQ6yxKHyyaa7PyZiTk9m953mG3IWXpviIqP GMlpfHJbaMPFJgIH7WxAVxFFzSG57rc= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id E29F9134FB; Sat, 1 Apr 2023 06:37:00 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 0IT8NQzRJ2QSdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:00 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 01/15] x86/mtrr: split off physical address size calculation Date: Sat, 1 Apr 2023 08:36:38 +0200 Message-Id: <20230401063652.23522-2-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the calculation of the physical address size in mtrr_bp_init() into a helper function. This will be needed later. Do only the pure code movement without optimizing it. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch V3: - only move code, split off optimizations (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/mtrr.c | 57 ++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 783f3210d582..8310bdb111d0 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -620,22 +620,14 @@ static struct syscore_ops mtrr_syscore_ops =3D { int __initdata changed_by_mtrr_cleanup; =20 #define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) -/** - * mtrr_bp_init - initialize mtrrs on the boot CPU - * - * This needs to be called early; before any of the other CPUs are - * initialized (i.e. before smp_init()). - * - */ -void __init mtrr_bp_init(void) + +static unsigned int __init mtrr_calc_physbits(bool generic) { - const char *why =3D "(not available)"; - u32 phys_addr; + unsigned int phys_addr; =20 phys_addr =3D 32; =20 - if (boot_cpu_has(X86_FEATURE_MTRR)) { - mtrr_if =3D &generic_mtrr_ops; + if (generic) { size_or_mask =3D SIZE_OR_MASK_BITS(36); size_and_mask =3D 0x00f00000; phys_addr =3D 36; @@ -667,29 +659,44 @@ void __init mtrr_bp_init(void) size_and_mask =3D 0; phys_addr =3D 32; } + } else { + size_or_mask =3D SIZE_OR_MASK_BITS(32); + size_and_mask =3D 0; + } + + return phys_addr; +} + +/** + * mtrr_bp_init - initialize mtrrs on the boot CPU + * + * This needs to be called early; before any of the other CPUs are + * initialized (i.e. before smp_init()). + * + */ +void __init mtrr_bp_init(void) +{ + const char *why =3D "(not available)"; + unsigned int phys_addr; + + phys_addr =3D mtrr_calc_physbits(boot_cpu_has(X86_FEATURE_MTRR)); + + if (boot_cpu_has(X86_FEATURE_MTRR)) { + mtrr_if =3D &generic_mtrr_ops; } else { switch (boot_cpu_data.x86_vendor) { case X86_VENDOR_AMD: - if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) { - /* Pre-Athlon (K6) AMD CPU MTRRs */ + /* Pre-Athlon (K6) AMD CPU MTRRs */ + if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) mtrr_if =3D &amd_mtrr_ops; - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; - } break; case X86_VENDOR_CENTAUR: - if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) { + if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) mtrr_if =3D ¢aur_mtrr_ops; - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; - } break; case X86_VENDOR_CYRIX: - if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) { + if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) mtrr_if =3D &cyrix_mtrr_ops; - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; - } break; default: break; --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2505C6FD1D for ; Sat, 1 Apr 2023 06:37:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233250AbjDAGhP (ORCPT ); Sat, 1 Apr 2023 02:37:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233283AbjDAGhK (ORCPT ); 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Sat, 1 Apr 2023 06:37:06 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id KxKEIhLRJ2QcdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:06 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 02/15] x86/mtrr: optimize mtrr_calc_physbits() Date: Sat, 1 Apr 2023 08:36:39 +0200 Message-Id: <20230401063652.23522-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Optimize mtrr_calc_physbits() for better readability. Drop a stale comment, as reality has made it obsolete. [ bp: - s/mtrr/MTRR/ - s/boot_cpu_has/cpu_feature_enabled/ - use GENMASK_ULL - simplify. ] Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov (AMD) Tested-by: Michael Kelley --- V3: - new patch, split off from previous patch (Boris Petkov) V5: - add some modifications by Boris Petkov --- arch/x86/kernel/cpu/mtrr/mtrr.c | 27 +++++++-------------------- 1 file changed, 7 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 8310bdb111d0..ce0b82209ad3 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -619,8 +619,6 @@ static struct syscore_ops mtrr_syscore_ops =3D { =20 int __initdata changed_by_mtrr_cleanup; =20 -#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) - static unsigned int __init mtrr_calc_physbits(bool generic) { unsigned int phys_addr; @@ -628,15 +626,8 @@ static unsigned int __init mtrr_calc_physbits(bool gen= eric) phys_addr =3D 32; =20 if (generic) { - size_or_mask =3D SIZE_OR_MASK_BITS(36); - size_and_mask =3D 0x00f00000; phys_addr =3D 36; =20 - /* - * This is an AMD specific MSR, but we assume(hope?) that - * Intel will implement it too when they extend the address - * bus of the Xeon. - */ if (cpuid_eax(0x80000000) >=3D 0x80000008) { phys_addr =3D cpuid_eax(0x80000008) & 0xff; /* CPUID workaround for Intel 0F33/0F34 CPU */ @@ -647,41 +638,37 @@ static unsigned int __init mtrr_calc_physbits(bool ge= neric) boot_cpu_data.x86_stepping =3D=3D 0x4)) phys_addr =3D 36; =20 - size_or_mask =3D SIZE_OR_MASK_BITS(phys_addr); - size_and_mask =3D ~size_or_mask & 0xfffff00000ULL; } else if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_CENTAUR && boot_cpu_data.x86 =3D=3D 6) { /* * VIA C* family have Intel style MTRRs, * but don't support PAE */ - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; phys_addr =3D 32; } - } else { - size_or_mask =3D SIZE_OR_MASK_BITS(32); - size_and_mask =3D 0; } =20 + size_or_mask =3D ~GENMASK_ULL(phys_addr - PAGE_SHIFT - 1, 0); + size_and_mask =3D ~size_or_mask & GENMASK_ULL(39, 20); + return phys_addr; } =20 /** - * mtrr_bp_init - initialize mtrrs on the boot CPU + * mtrr_bp_init - initialize MTRRs on the boot CPU * * This needs to be called early; before any of the other CPUs are * initialized (i.e. before smp_init()). - * */ void __init mtrr_bp_init(void) { + bool generic_mtrrs =3D cpu_feature_enabled(X86_FEATURE_MTRR); const char *why =3D "(not available)"; unsigned int phys_addr; =20 - phys_addr =3D mtrr_calc_physbits(boot_cpu_has(X86_FEATURE_MTRR)); + phys_addr =3D mtrr_calc_physbits(generic_mtrrs); =20 - if (boot_cpu_has(X86_FEATURE_MTRR)) { + if (generic_mtrrs) { mtrr_if =3D &generic_mtrr_ops; } else { switch (boot_cpu_data.x86_vendor) { --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27008C77B70 for ; Sat, 1 Apr 2023 06:37:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233385AbjDAGh1 (ORCPT ); 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bh=5tBXsp0muXYt38fiqF48mI0NM1nAHxNxMRiNpwrq0p8=; b=pkYfCnFpOH8pZGbqSy25hweqcgFa7lM80kv9hgtSwJUFq5u3pGem/fY9+Bf7EHSa57sdRQ oxc6OfCjN5TMskB5pdc7I13Pnqi+L6R5CmsF2qCWRbcNrqzUsfYrW2kYP58o9BftSGQBhQ KmuYJWeRZ6AHvUop0MKuYTrW5bUeUuw= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 437D4134FB; Sat, 1 Apr 2023 06:37:12 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id nyXhDhjRJ2QjdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:12 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v5 03/15] x86/mtrr: replace some constants with defines Date: Sat, 1 Apr 2023 08:36:40 +0200 Message-Id: <20230401063652.23522-4-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of using constants in MTRR code, use some new #defines. Signed-off-by: Juergen Gross --- V5: - new patch (inspired by a request of Boris Petkov) --- arch/x86/include/asm/mtrr.h | 25 +++++++++++++-- arch/x86/kernel/cpu/mtrr/cleanup.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 51 +++++++++++++++++------------- arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- 4 files changed, 54 insertions(+), 26 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index f0eeaf6e5f5f..4e59f7854950 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -23,8 +23,26 @@ #ifndef _ASM_X86_MTRR_H #define _ASM_X86_MTRR_H =20 +#include #include =20 +/* Defines for hardware MTRR registers. */ +#define MTRR_CONFIG_NUM_VAR_MASK GENMASK(7, 0) +#define MTRR_CONFIG_HAVE_FIXED BIT_MASK(8) +#define MTRR_CONFIG_HAVE_WC BIT_MASK(10) + +#define MTRR_DEFTYPE_TYPE_MASK GENMASK(7, 0) +#define MTRR_DEFTYPE_FIXED_ENABLED BIT_MASK(10) +#define MTRR_DEFTYPE_ENABLED BIT_MASK(11) +#define MTRR_DEFTYPE_ENABLE_MASK (MTRR_DEFTYPE_FIXED_ENABLED | \ + MTRR_DEFTYPE_ENABLED) +#define MTRR_DEFTYPE_DISABLE_MASK ~(MTRR_DEFTYPE_TYPE_MASK | \ + MTRR_DEFTYPE_ENABLE_MASK) + +#define MTRR_BASE_TYPE_MASK GENMASK_ULL(7, 0) + +#define MTRR_MASK_VALID BIT_ULL_MASK(11) + /* * The following functions are for use by other drivers that cannot use * arch_phys_wc_add and arch_phys_wc_del. @@ -121,7 +139,10 @@ struct mtrr_gentry32 { #endif /* CONFIG_COMPAT */ =20 /* Bit fields for enabled in struct mtrr_state_type */ -#define MTRR_STATE_MTRR_FIXED_ENABLED 0x01 -#define MTRR_STATE_MTRR_ENABLED 0x02 +#define MTRR_STATE_SHIFT 10 +#define MTRR_STATE_MTRR_FIXED_ENABLED \ + (MTRR_DEFTYPE_FIXED_ENABLED >> MTRR_STATE_SHIFT) +#define MTRR_STATE_MTRR_ENABLED \ + (MTRR_DEFTYPE_ENABLED >> MTRR_STATE_SHIFT) =20 #endif /* _ASM_X86_MTRR_H */ diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/= cleanup.c index b5f43049fa5f..ce45d7617874 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -890,7 +890,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_= pfn) return 0; =20 rdmsr(MSR_MTRRdefType, def, dummy); - def &=3D 0xff; + def &=3D MTRR_DEFTYPE_TYPE_MASK; if (def !=3D MTRR_TYPE_UNCACHABLE) return 0; =20 diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index ee09d359e08f..9a12da76635c 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -171,7 +171,7 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end,= u64 *partial_end, for (i =3D 0; i < num_var_ranges; ++i) { unsigned short start_state, end_state, inclusive; =20 - if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) + if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_MASK_VALID)) continue; =20 base =3D (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + @@ -223,7 +223,8 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end,= u64 *partial_end, if ((start & mask) !=3D (base & mask)) continue; =20 - curr_match =3D mtrr_state.var_ranges[i].base_lo & 0xff; + curr_match =3D mtrr_state.var_ranges[i].base_lo & + MTRR_BASE_TYPE_MASK; if (prev_match =3D=3D MTRR_TYPE_INVALID) { prev_match =3D curr_match; continue; @@ -425,7 +426,7 @@ static void __init print_mtrr_state(void) high_width =3D (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4; =20 for (i =3D 0; i < num_var_ranges; ++i) { - if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) + if (mtrr_state.var_ranges[i].mask_lo & MTRR_MASK_VALID) pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", i, high_width, @@ -434,7 +435,8 @@ static void __init print_mtrr_state(void) high_width, mtrr_state.var_ranges[i].mask_hi, mtrr_state.var_ranges[i].mask_lo >> 12, - mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); + mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & + MTRR_BASE_TYPE_MASK)); else pr_debug(" %u disabled\n", i); } @@ -452,7 +454,7 @@ bool __init get_mtrr_state(void) vrs =3D mtrr_state.var_ranges; =20 rdmsr(MSR_MTRRcap, lo, dummy); - mtrr_state.have_fixed =3D (lo >> 8) & 1; + mtrr_state.have_fixed =3D !!(lo & MTRR_CONFIG_HAVE_FIXED); =20 for (i =3D 0; i < num_var_ranges; i++) get_mtrr_var_range(i, &vrs[i]); @@ -460,8 +462,9 @@ bool __init get_mtrr_state(void) get_fixed_ranges(mtrr_state.fixed_ranges); =20 rdmsr(MSR_MTRRdefType, lo, dummy); - mtrr_state.def_type =3D (lo & 0xff); - mtrr_state.enabled =3D (lo & 0xc00) >> 10; + mtrr_state.def_type =3D lo & MTRR_DEFTYPE_TYPE_MASK; + mtrr_state.enabled =3D (lo & MTRR_DEFTYPE_ENABLE_MASK) >> + MTRR_STATE_SHIFT; =20 if (amd_special_default_mtrr()) { unsigned low, high; @@ -574,7 +577,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned= long *base, =20 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); =20 - if ((mask_lo & 0x800) =3D=3D 0) { + if ((mask_lo & MTRR_MASK_VALID) =3D=3D 0) { /* Invalid (i.e. free) range */ *base =3D 0; *size =3D 0; @@ -606,7 +609,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned= long *base, */ *size =3D -mask; *base =3D (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; - *type =3D base_lo & 0xff; + *type =3D base_lo & MTRR_BASE_TYPE_MASK; =20 out_put_cpu: put_cpu(); @@ -643,10 +646,12 @@ static bool set_mtrr_var_ranges(unsigned int index, s= truct mtrr_var_range *vr) unsigned int lo, hi; bool changed =3D false; =20 +#define BASE_MASK (MTRR_BASE_TYPE_MASK | (size_and_mask << PAGE_SHIFT)) +#define MASK_MASK (MTRR_MASK_VALID | (size_and_mask << PAGE_SHIFT)) + rdmsr(MTRRphysBase_MSR(index), lo, hi); - if ((vr->base_lo & 0xfffff0ffUL) !=3D (lo & 0xfffff0ffUL) - || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=3D - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->base_lo & BASE_MASK) !=3D (lo & BASE_MASK) + || (vr->base_hi & (BASE_MASK >> 32)) !=3D (hi & (BASE_MASK >> 32))) { =20 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); changed =3D true; @@ -654,9 +659,8 @@ static bool set_mtrr_var_ranges(unsigned int index, str= uct mtrr_var_range *vr) =20 rdmsr(MTRRphysMask_MSR(index), lo, hi); =20 - if ((vr->mask_lo & 0xfffff800UL) !=3D (lo & 0xfffff800UL) - || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=3D - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->mask_lo & MASK_MASK) !=3D (lo & MASK_MASK) + || (vr->mask_hi & (MASK_MASK >> 32)) !=3D (hi & (MASK_MASK >> 32))) { mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); changed =3D true; } @@ -691,11 +695,13 @@ static unsigned long set_mtrr_state(void) * Set_mtrr_restore restores the old value of MTRRdefType, * so to set it we fiddle with the saved value: */ - if ((deftype_lo & 0xff) !=3D mtrr_state.def_type - || ((deftype_lo & 0xc00) >> 10) !=3D mtrr_state.enabled) { + if ((deftype_lo & MTRR_DEFTYPE_TYPE_MASK) !=3D mtrr_state.def_type + || ((deftype_lo & MTRR_DEFTYPE_ENABLE_MASK) >> MTRR_STATE_SHIFT) !=3D + mtrr_state.enabled) { =20 - deftype_lo =3D (deftype_lo & ~0xcff) | mtrr_state.def_type | - (mtrr_state.enabled << 10); + deftype_lo =3D (deftype_lo & MTRR_DEFTYPE_DISABLE_MASK) | + mtrr_state.def_type | + (mtrr_state.enabled << MTRR_STATE_SHIFT); change_mask |=3D MTRR_CHANGE_MASK_DEFTYPE; } =20 @@ -708,7 +714,8 @@ void mtrr_disable(void) rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); =20 /* Disable MTRRs, and set the default type to uncached */ - mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); + mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEFTYPE_DISABLE_MASK, + deftype_hi); } =20 void mtrr_enable(void) @@ -763,7 +770,7 @@ static void generic_set_mtrr(unsigned int reg, unsigned= long base, } else { vr->base_lo =3D base << PAGE_SHIFT | type; vr->base_hi =3D (base & size_and_mask) >> (32 - PAGE_SHIFT); - vr->mask_lo =3D -size << PAGE_SHIFT | 0x800; + vr->mask_lo =3D -size << PAGE_SHIFT | MTRR_MASK_VALID; vr->mask_hi =3D (-size & size_and_mask) >> (32 - PAGE_SHIFT); =20 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); @@ -817,7 +824,7 @@ static int generic_have_wrcomb(void) { unsigned long config, dummy; rdmsr(MSR_MTRRcap, config, dummy); - return config & (1 << 10); + return config & MTRR_CONFIG_HAVE_WC; } =20 int positive_have_wrcomb(void) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index ce0b82209ad3..1beb38f7a7a3 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -117,7 +117,7 @@ static void __init set_num_var_ranges(bool use_generic) else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) config =3D 8; =20 - num_var_ranges =3D config & 0xff; + num_var_ranges =3D config & MTRR_CONFIG_NUM_VAR_MASK; } =20 static void __init init_table(void) --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 515ECC76196 for ; Sat, 1 Apr 2023 06:37:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233342AbjDAGhj (ORCPT ); Sat, 1 Apr 2023 02:37:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233079AbjDAGhc (ORCPT ); Sat, 1 Apr 2023 02:37:32 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DC8E20C01 for ; Fri, 31 Mar 2023 23:37:19 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 3900D21A1E; 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Sat, 01 Apr 2023 06:37:17 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 04/15] x86/mtrr: support setting MTRR state for software defined MTRRs Date: Sat, 1 Apr 2023 08:36:41 +0200 Message-Id: <20230401063652.23522-5-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When running virtualized, MTRR access can be reduced (e.g. in Xen PV guests or when running as a SEV-SNP guest under Hyper-V). Typically the hypervisor will reset the MTRR feature in CPUID data, resulting in no MTRR memory type information being available for the kernel. This has turned out to result in problems: - Hyper-V SEV-SNP guests using uncached mappings where they shouldn't - Xen PV dom0 mapping memory as WB which should be UC- instead Solve those problems by supporting to set a static MTRR state, overwriting the empty state used today. In case such a state has been set, don't call get_mtrr_state() in mtrr_bp_init(). The set state will only be used by mtrr_type_lookup(), as in all other cases mtrr_enabled() is being checked, which will return false. Accept the overwrite call only for selected cases when running as a guest. Disable X86_FEATURE_MTRR in order to avoid any MTRR modifications by just refusing them. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch V3: - omit fixed MTRRs, as those are currently not needed - disable X86_FEATURE_MTRR instead of testing it - provide a stub for !CONFIG_MTRR (Michael Kelley) - use cpu_feature_enabled() (Boris Petkov) - add tests for mtrr_overwrite_state() being allowed (Boris Petkov) V4: - add test for hv_is_isolation_supported() (Michael Kelley) V5: - drop test for running as native (Boris Petkov) - split large complex test into multiple simple ones (Boris Petkov) - enhance test in mtrr_bp_init() (Boris Petkov) --- arch/x86/include/asm/mtrr.h | 8 +++++ arch/x86/kernel/cpu/mtrr/generic.c | 58 +++++++++++++++++++++++++++++- arch/x86/kernel/cpu/mtrr/mtrr.c | 9 +++++ arch/x86/kernel/setup.c | 2 ++ 4 files changed, 76 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 4e59f7854950..6decb18e22ed 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -49,6 +49,8 @@ */ # ifdef CONFIG_MTRR void mtrr_bp_init(void); +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type); extern u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform); extern void mtrr_save_fixed_ranges(void *); extern void mtrr_save_state(void); @@ -66,6 +68,12 @@ void mtrr_disable(void); void mtrr_enable(void); void mtrr_generic_set_state(void); # else +static inline void mtrr_overwrite_state(struct mtrr_var_range *var, + unsigned int num_var, + mtrr_type def_type) +{ +} + static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 9a12da76635c..0794f3f1cc27 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -8,10 +8,12 @@ #include #include #include - +#include #include #include #include +#include +#include #include #include #include @@ -241,6 +243,60 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end= , u64 *partial_end, return mtrr_state.def_type; } =20 +/** + * mtrr_overwrite_state - set static MTRR state + * + * Used to set MTRR state via different means (e.g. with data obtained from + * a hypervisor). + * Is allowed only for special cases when running virtualized. Must be cal= led + * from the x86_init.hyper.init_platform() hook. + */ +void mtrr_overwrite_state(struct mtrr_var_range *var, unsigned int num_var, + mtrr_type def_type) +{ + unsigned int i; + + /* Only allowed to be called once before mtrr_bp_init(). */ + if (WARN_ON(mtrr_state_set)) + return; + + /* Only allowed when running virtualized. */ + if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) + return; + + /* + * Only allowed for special virtualization cases: + * - when running as SEV-SNP guest + * - when running as Hyper-V isolated guest + * - when running as Xen PV guest + * - when running as TSX guest + */ + if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP) && + !hv_is_isolation_supported() && + !cpu_feature_enabled(X86_FEATURE_XENPV) && + !cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) + return; + + /* Disable MTRR in order to disable MTRR modifications. */ + setup_clear_cpu_cap(X86_FEATURE_MTRR); + + if (var) { + if (num_var > MTRR_MAX_VAR_RANGES) { + pr_warn("Trying to overwrite MTRR state with %u variable entries\n", + num_var); + num_var =3D MTRR_MAX_VAR_RANGES; + } + for (i =3D 0; i < num_var; i++) + mtrr_state.var_ranges[i] =3D var[i]; + num_var_ranges =3D num_var; + } + + mtrr_state.def_type =3D def_type; + mtrr_state.enabled |=3D MTRR_STATE_MTRR_ENABLED; + + mtrr_state_set =3D 1; +} + /** * mtrr_type_lookup - look up memory type in MTRR * diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 1beb38f7a7a3..1c19d67ddab3 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -666,6 +666,15 @@ void __init mtrr_bp_init(void) const char *why =3D "(not available)"; unsigned int phys_addr; =20 + if (!generic_mtrrs && mtrr_state.enabled) { + /* Software overwrite of MTRR state, only for generic case. */ + mtrr_calc_physbits(true); + init_table(); + pr_info("MTRRs set to read-only\n"); + + return; + } + phys_addr =3D mtrr_calc_physbits(generic_mtrrs); =20 if (generic_mtrrs) { diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 16babff771bd..0cccfeb67c3a 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -1037,6 +1037,8 @@ void __init setup_arch(char **cmdline_p) /* * VMware detection requires dmi to be available, so this * needs to be done after dmi_setup(), for the boot CPU. + * For some guest types (Xen PV, SEV-SNP, TDX) it is required to be + * called before cache_bp_init() for setting up MTRR state. */ init_hypervisor_platform(); =20 --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12623C77B60 for ; Sat, 1 Apr 2023 06:37:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232528AbjDAGhv (ORCPT ); Sat, 1 Apr 2023 02:37:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232426AbjDAGhr (ORCPT ); Sat, 1 Apr 2023 02:37:47 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B38991D912; Fri, 31 Mar 2023 23:37:25 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 08D4C21A48; Sat, 1 Apr 2023 06:37:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331044; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pb/qNhjjqBGVJo7Fmuv925HQ9Z5bT3aQVdQm6MKlfSg=; b=TGo1WV1P/iS2JNstiqxFXFknQ8WqtOvAk0laUW9IOlTsCtclVDPucDgnXk1y1mDR/zGroE RCt3W57dqASE+DqaeItDKCm2lZA2tTpSsf2Foe++Ec2E9xZgnhoaxnyUKzjGZdHlSUCWPo RPuhmyAkLXUtcLY1j/c9MxD0q4KTXn8= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 9E137134FB; Sat, 1 Apr 2023 06:37:23 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 3pc7JSPRJ2RDdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:23 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-hyperv@vger.kernel.org Cc: Juergen Gross , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 05/15] x86/hyperv: set MTRR state when running as SEV-SNP Hyper-V guest Date: Sat, 1 Apr 2023 08:36:42 +0200 Message-Id: <20230401063652.23522-6-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to avoid mappings using the UC- cache attribute, set the MTRR state to use WB caching as the default. This is needed in order to cope with the fact that PAT is enabled, while MTRRs are not supported by the hypervisor. Fixes: 90b926e68f50 ("x86/pat: Fix pat_x_mtrr_type() for MTRR disabled case= ") Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - new patch --- arch/x86/kernel/cpu/mshyperv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index f36dc2f796c5..0a6cc3cf8919 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -34,6 +34,7 @@ #include #include #include +#include =20 /* Is Linux running as the root partition? */ bool hv_root_partition; @@ -408,6 +409,9 @@ static void __init ms_hyperv_init_platform(void) #ifdef CONFIG_SWIOTLB swiotlb_unencrypted_base =3D ms_hyperv.shared_gpa_boundary; #endif + + /* Set WB as the default cache mode. */ + mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); } /* Isolation VMs are unenlightened SEV-based VMs, thus this check: */ if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) { --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Sat, 01 Apr 2023 06:37:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: acec79e9-d057-11ed-b464-930f4c7d94ae DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331049; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BBSVwIjfh8GqolcmguccgHbT9FXyjh+eQq+oIFQmSnw=; b=ajS/iUmKoQdV4uRxzu4IIGIVP4xHuK0N0mFHi+m4Vq9E4sezhaed9RpDBa3+M5YQFdJCaq gZbqX3tuVGAXhzB3za13DOYXPeqgOYoxxl+pC7dSY9e8MohVhKnXH+ccd+fRqFRO43AjOz n25N0ONmdBS7BJtWgUpIwdIAaFHoHiM= From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Boris Ostrovsky , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , xen-devel@lists.xenproject.org Subject: [PATCH v5 06/15] x86/xen: set MTRR state when running as Xen PV initial domain Date: Sat, 1 Apr 2023 08:36:43 +0200 Message-Id: <20230401063652.23522-7-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1680331081946100001 Content-Type: text/plain; charset="utf-8" When running as Xen PV initial domain (aka dom0), MTRRs are disabled by the hypervisor, but the system should nevertheless use correct cache memory types. This has always kind of worked, as disabled MTRRs resulted in disabled PAT, too, so that the kernel avoided code paths resulting in inconsistencies. This bypassed all of the sanity checks the kernel is doing with enabled MTRRs in order to avoid memory mappings with conflicting memory types. This has been changed recently, leading to PAT being accepted to be enabled, while MTRRs stayed disabled. The result is that mtrr_type_lookup() no longer is accepting all memory type requests, but started to return WB even if UC- was requested. This led to driver failures during initialization of some devices. In reality MTRRs are still in effect, but they are under complete control of the Xen hypervisor. It is possible, however, to retrieve the MTRR settings from the hypervisor. In order to fix those problems, overwrite the MTRR state via mtrr_overwrite_state() with the MTRR data from the hypervisor, if the system is running as a Xen dom0. Fixes: 72cbc8f04fe2 ("x86/PAT: Have pat_enabled() properly reflect state wh= en running on Xen") Signed-off-by: Juergen Gross Reviewed-by: Boris Ostrovsky --- V2: - new patch V3: - move the call of mtrr_overwrite_state() to xen_pv_init_platform() V4: - only call mtrr_overwrite_state() if any MTRR got from Xen (Boris Ostrovsky) --- arch/x86/xen/enlighten_pv.c | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 093b78c8bbec..fdaea02ab5ab 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -68,6 +68,7 @@ #include #include #include +#include #include #include #include @@ -119,6 +120,54 @@ static int __init parse_xen_msr_safe(char *str) } early_param("xen_msr_safe", parse_xen_msr_safe); =20 +/* Get MTRR settings from Xen and put them into mtrr_state. */ +static void __init xen_set_mtrr_data(void) +{ +#ifdef CONFIG_MTRR + struct xen_platform_op op =3D { + .cmd =3D XENPF_read_memtype, + .interface_version =3D XENPF_INTERFACE_VERSION, + }; + unsigned int reg; + unsigned long mask; + uint32_t eax, width; + static struct mtrr_var_range var[MTRR_MAX_VAR_RANGES] __initdata; + + /* Get physical address width (only 64-bit cpus supported). */ + width =3D 36; + eax =3D cpuid_eax(0x80000000); + if ((eax >> 16) =3D=3D 0x8000 && eax >=3D 0x80000008) { + eax =3D cpuid_eax(0x80000008); + width =3D eax & 0xff; + } + + for (reg =3D 0; reg < MTRR_MAX_VAR_RANGES; reg++) { + op.u.read_memtype.reg =3D reg; + if (HYPERVISOR_platform_op(&op)) + break; + + /* + * Only called in dom0, which has all RAM PFNs mapped at + * RAM MFNs, and all PCI space etc. is identity mapped. + * This means we can treat MFN =3D=3D PFN regarding MTRR settings. + */ + var[reg].base_lo =3D op.u.read_memtype.type; + var[reg].base_lo |=3D op.u.read_memtype.mfn << PAGE_SHIFT; + var[reg].base_hi =3D op.u.read_memtype.mfn >> (32 - PAGE_SHIFT); + mask =3D ~((op.u.read_memtype.nr_mfns << PAGE_SHIFT) - 1); + mask &=3D (1UL << width) - 1; + if (mask) + mask |=3D MTRR_MASK_VALID; + var[reg].mask_lo =3D mask; + var[reg].mask_hi =3D mask >> 32; + } + + /* Only overwrite MTRR state if any MTRR could be got from Xen. */ + if (reg) + mtrr_overwrite_state(var, reg, MTRR_TYPE_UNCACHABLE); +#endif +} + static void __init xen_pv_init_platform(void) { /* PV guests can't operate virtio devices without grants. */ @@ -135,6 +184,9 @@ static void __init xen_pv_init_platform(void) =20 /* pvclock is in shared info area */ xen_init_time_ops(); + + if (xen_initial_domain()) + xen_set_mtrr_data(); } =20 static void __init xen_pv_guest_late_init(void) --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4819CC76196 for ; Sat, 1 Apr 2023 06:38:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233425AbjDAGiJ (ORCPT ); Sat, 1 Apr 2023 02:38:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233345AbjDAGiB (ORCPT ); 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Sat, 1 Apr 2023 06:37:35 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id zSTiCS/RJ2RbdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:35 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 07/15] x86/mtrr: replace vendor tests in MTRR code Date: Sat, 1 Apr 2023 08:36:44 +0200 Message-Id: <20230401063652.23522-8-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Modern CPUs all share the same MTRR interface implemented via generic_mtrr_ops. At several places in MTRR code this generic interface is deduced via is_cpu(INTEL) tests, which is only working due to X86_VENDOR_INTEL being 0 (the is_cpu() macro is testing mtrr_if->vendor, which isn't explicitly set in generic_mtrr_ops). Fix that by replacing the is_cpu(INTEL) tests with testing for mtrr_if to be &generic_mtrr_ops. The only other place where the .vendor member of struct mtrr_ops is being used is in set_num_var_ranges(), where depending on the vendor the number of MTRR registers is determined. This can easily be changed by replacing .vendor with the static number of MTRR registers. It should be noted that the test "is_cpu(HYGON)" wasn't ever returning true, as there is no struct mtrr_ops with that vendor information. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V4: - use cpu_feature_enabled(X86_FEATURE_MTRR) for testing generic MTRRs (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/amd.c | 2 +- arch/x86/kernel/cpu/mtrr/centaur.c | 2 +- arch/x86/kernel/cpu/mtrr/cleanup.c | 4 ++-- arch/x86/kernel/cpu/mtrr/cyrix.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 2 +- arch/x86/kernel/cpu/mtrr/mtrr.c | 8 +++----- arch/x86/kernel/cpu/mtrr/mtrr.h | 4 +--- 7 files changed, 10 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c index eff6ac62c0ff..ef3e8e42b782 100644 --- a/arch/x86/kernel/cpu/mtrr/amd.c +++ b/arch/x86/kernel/cpu/mtrr/amd.c @@ -110,7 +110,7 @@ amd_validate_add_page(unsigned long base, unsigned long= size, unsigned int type) } =20 const struct mtrr_ops amd_mtrr_ops =3D { - .vendor =3D X86_VENDOR_AMD, + .var_regs =3D 2, .set =3D amd_set_mtrr, .get =3D amd_get_mtrr, .get_free_region =3D generic_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/= centaur.c index b8a74eddde83..4466ddeb0125 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -112,7 +112,7 @@ centaur_validate_add_page(unsigned long base, unsigned = long size, unsigned int t } =20 const struct mtrr_ops centaur_mtrr_ops =3D { - .vendor =3D X86_VENDOR_CENTAUR, + .var_regs =3D 8, .set =3D centaur_set_mcr, .get =3D centaur_get_mcr, .get_free_region =3D centaur_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/= cleanup.c index ce45d7617874..0f27c38f3ff9 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -689,7 +689,7 @@ int __init mtrr_cleanup(unsigned address_bits) int index_good; int i; =20 - if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1) + if (!cpu_feature_enabled(X86_FEATURE_MTRR) || enable_mtrr_cleanup < 1) return 0; =20 rdmsr(MSR_MTRRdefType, def, dummy); @@ -886,7 +886,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_= pfn) * Make sure we only trim uncachable memory on machines that * support the Intel MTRR architecture: */ - if (!is_cpu(INTEL) || disable_mtrr_trim) + if (!cpu_feature_enabled(X86_FEATURE_MTRR) || disable_mtrr_trim) return 0; =20 rdmsr(MSR_MTRRdefType, def, dummy); diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cy= rix.c index 173b9e01e623..238dad57d4d6 100644 --- a/arch/x86/kernel/cpu/mtrr/cyrix.c +++ b/arch/x86/kernel/cpu/mtrr/cyrix.c @@ -235,7 +235,7 @@ static void cyrix_set_arr(unsigned int reg, unsigned lo= ng base, } =20 const struct mtrr_ops cyrix_mtrr_ops =3D { - .vendor =3D X86_VENDOR_CYRIX, + .var_regs =3D 8, .set =3D cyrix_set_arr, .get =3D cyrix_get_arr, .get_free_region =3D cyrix_get_free_region, diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 0794f3f1cc27..5d60b46187f7 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -846,7 +846,7 @@ int generic_validate_add_page(unsigned long base, unsig= ned long size, * For Intel PPro stepping <=3D 7 * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF */ - if (is_cpu(INTEL) && boot_cpu_data.x86 =3D=3D 6 && + if (mtrr_if =3D=3D &generic_mtrr_ops && boot_cpu_data.x86 =3D=3D 6 && boot_cpu_data.x86_model =3D=3D 1 && boot_cpu_data.x86_stepping <=3D 7) { if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) { diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 1c19d67ddab3..46aae69d259e 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -108,14 +108,12 @@ static int have_wrcomb(void) /* This function returns the number of variable MTRRs */ static void __init set_num_var_ranges(bool use_generic) { - unsigned long config =3D 0, dummy; + unsigned long config, dummy; =20 if (use_generic) rdmsr(MSR_MTRRcap, config, dummy); - else if (is_cpu(AMD) || is_cpu(HYGON)) - config =3D 2; - else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) - config =3D 8; + else + config =3D mtrr_if->var_regs; =20 num_var_ranges =3D config & MTRR_CONFIG_NUM_VAR_MASK; } diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtr= r.h index 02eb5871492d..a3c362d3d5bf 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -13,7 +13,7 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; =20 struct mtrr_ops { - u32 vendor; + u32 var_regs; void (*set)(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type); void (*get)(unsigned int reg, unsigned long *base, @@ -54,8 +54,6 @@ bool get_mtrr_state(void); extern u64 size_or_mask, size_and_mask; extern const struct mtrr_ops *mtrr_if; =20 -#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor =3D=3D X86_VENDOR_##vnd) - extern unsigned int num_var_ranges; extern u64 mtrr_tom2; extern struct mtrr_state_type mtrr_state; --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02032C76196 for ; Sat, 1 Apr 2023 06:38:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233159AbjDAGi0 (ORCPT ); Sat, 1 Apr 2023 02:38:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233437AbjDAGiK (ORCPT ); Sat, 1 Apr 2023 02:38:10 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D11220C29 for ; Fri, 31 Mar 2023 23:37:44 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 2AEE921A1E; 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Sat, 01 Apr 2023 06:37:40 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v5 08/15] x86/mtrr: have only one set_mtrr() variant Date: Sat, 1 Apr 2023 08:36:45 +0200 Message-Id: <20230401063652.23522-9-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Today there are two variants of set_mtrr(): one calling stop_machine() and one calling stop_machine_cpuslocked(). The first one (set_mtrr()) has only one caller, and this caller is always running with only one CPU online and interrupts being off. Remove the first variant completely and replace the call of it with a call of mtrr_if->set(). Rename the second variant set_mtrr_cpuslocked() to set_mtrr() now that there is only one variant left. Signed-off-by: Juergen Gross --- V5: - new patch --- arch/x86/kernel/cpu/mtrr/mtrr.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 46aae69d259e..4fa3d0f94f39 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -192,20 +192,8 @@ static inline int types_compatible(mtrr_type type1, mt= rr_type type2) * Note that the mechanism is the same for UP systems, too; all the SMP st= uff * becomes nops. */ -static void -set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_ty= pe type) -{ - struct set_mtrr_data data =3D { .smp_reg =3D reg, - .smp_base =3D base, - .smp_size =3D size, - .smp_type =3D type - }; - - stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask); -} - -static void set_mtrr_cpuslocked(unsigned int reg, unsigned long base, - unsigned long size, mtrr_type type) +static void set_mtrr(unsigned int reg, unsigned long base, unsigned long s= ize, + mtrr_type type) { struct set_mtrr_data data =3D { .smp_reg =3D reg, .smp_base =3D base, @@ -335,7 +323,7 @@ int mtrr_add_page(unsigned long base, unsigned long siz= e, /* Search for an empty MTRR */ i =3D mtrr_if->get_free_region(base, size, replace); if (i >=3D 0) { - set_mtrr_cpuslocked(i, base, size, type); + set_mtrr(i, base, size, type); if (likely(replace < 0)) { mtrr_usage_table[i] =3D 1; } else { @@ -343,7 +331,7 @@ int mtrr_add_page(unsigned long base, unsigned long siz= e, if (increment) mtrr_usage_table[i]++; if (unlikely(replace !=3D i)) { - set_mtrr_cpuslocked(replace, 0, 0, 0); + set_mtrr(replace, 0, 0, 0); mtrr_usage_table[replace] =3D 0; } } @@ -471,7 +459,7 @@ int mtrr_del_page(int reg, unsigned long base, unsigned= long size) goto out; } if (--mtrr_usage_table[reg] < 1) - set_mtrr_cpuslocked(reg, 0, 0, 0); + set_mtrr(reg, 0, 0, 0); error =3D reg; out: mutex_unlock(&mtrr_mutex); @@ -601,9 +589,9 @@ static void mtrr_restore(void) =20 for (i =3D 0; i < num_var_ranges; i++) { if (mtrr_value[i].lsize) { - set_mtrr(i, mtrr_value[i].lbase, - mtrr_value[i].lsize, - mtrr_value[i].ltype); + mtrr_if->set(i, mtrr_value[i].lbase, + mtrr_value[i].lsize, + mtrr_value[i].ltype); } } } --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57268C76196 for ; Sat, 1 Apr 2023 06:38:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233512AbjDAGia (ORCPT ); Sat, 1 Apr 2023 02:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233459AbjDAGiW (ORCPT ); Sat, 1 Apr 2023 02:38:22 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE0E021A9A for ; Fri, 31 Mar 2023 23:37:52 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id D244821A73; Sat, 1 Apr 2023 06:37:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331066; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=K2ik7sM7MKDAhj6hnR4NNX3zRxA2aEkPlgWNeKuOI4M=; b=lX+D5IwceSzE0cz8ypRJFts7mCMjDq0IimYmxMR5U7LkjWBGFqNw6+mlan32M26qL1QJEE A1v83q6XYc0XyzElJNX+aB2GPCOHzFtG+BMHB93lAZ0AiJSvd0BUGCNKWyndw00psTYQ6J 3+84JSzgIK60gZvRgUfdBSHCERV2GnI= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 8F059134FB; Sat, 1 Apr 2023 06:37:46 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 9+OrITrRJ2RpdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:46 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 09/15] x86/mtrr: allocate mtrr_value array dynamically Date: Sat, 1 Apr 2023 08:36:46 +0200 Message-Id: <20230401063652.23522-10-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mtrr_value[] array is a static variable, which is used only in a few configurations. Consuming 6kB is ridiculous for this case, especially as the array doesn't need to be that large and it can easily be allocated dynamically. The "few configurations" are all 32-bit ones, so put the code inside a CONFIG_X86_32 #ifdef. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V5: - check for allocation failure (Kai Huang, Boris Petkov) - add #ifdef --- arch/x86/kernel/cpu/mtrr/mtrr.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 4fa3d0f94f39..76f5b5e1128b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -560,8 +560,10 @@ int arch_phys_wc_index(int handle) } EXPORT_SYMBOL_GPL(arch_phys_wc_index); =20 -/* The suspend/resume methods are only for CPU without MTRR. CPU using gen= eric - * MTRR driver doesn't require this +#ifdef CONFIG_X86_32 +/* + * The suspend/resume methods are only for CPUs without MTRR. CPUs using g= eneric + * MTRR driver don't require this. */ struct mtrr_value { mtrr_type ltype; @@ -569,12 +571,15 @@ struct mtrr_value { unsigned long lsize; }; =20 -static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES]; +static struct mtrr_value *mtrr_value; =20 static int mtrr_save(void) { int i; =20 + if (!mtrr_value) + return -ENOMEM; + for (i =3D 0; i < num_var_ranges; i++) { mtrr_if->get(i, &mtrr_value[i].lbase, &mtrr_value[i].lsize, @@ -596,12 +601,11 @@ static void mtrr_restore(void) } } =20 - - static struct syscore_ops mtrr_syscore_ops =3D { .suspend =3D mtrr_save, .resume =3D mtrr_restore, }; +#endif /* CONFIG_X86_32 */ =20 int __initdata changed_by_mtrr_cleanup; =20 @@ -730,15 +734,20 @@ static int __init mtrr_init_finialize(void) return 0; } =20 +#ifdef CONFIG_X86_32 + mtrr_value =3D kcalloc(num_var_ranges, sizeof(*mtrr_value), GFP_KERNEL); + /* * The CPU has no MTRR and seems to not support SMP. They have * specific drivers, we use a tricky method to support - * suspend/resume for them. + * suspend/resume for them. In case above allocation failed we can't + * support suspend/resume (handled in mtrr_save()). * * TBD: is there any system with such CPU which supports * suspend/resume? If no, we should remove the code. */ register_syscore_ops(&mtrr_syscore_ops); +#endif =20 return 0; } --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54CB5C6FD1D for ; Sat, 1 Apr 2023 06:38:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233493AbjDAGim (ORCPT ); Sat, 1 Apr 2023 02:38:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233502AbjDAGi0 (ORCPT ); Sat, 1 Apr 2023 02:38:26 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D52B1D908 for ; Fri, 31 Mar 2023 23:38:00 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 885F421A48; Sat, 1 Apr 2023 06:37:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331072; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8lUW3P9mpcWjI7lNcX7PnUpBYL4zKefFnDWcjHwwm2k=; b=HexWFFQQVN5UN/qYGGwLOJTZXbNlqk67Lpl8/tvSu3uH7ydHzS+4O0feVIQhQJ973OGmFu Psqrkxh0wv+Fq+GClVWHorkEtZeRfyGUFk8NUfWidg5ha0oOMlOmIGoGC0+ODkliqiqFeo QhdZuv8XWJF+uveQWPaarVoXwuvvc5k= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 4290B134FB; Sat, 1 Apr 2023 06:37:52 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id MbvdDkDRJ2RwdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:52 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 10/15] x86/mtrr: add get_effective_type() service function Date: Sat, 1 Apr 2023 08:36:47 +0200 Message-Id: <20230401063652.23522-11-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a service function for obtaining the effective cache mode of overlapping MTRR registers. Make use of that function in check_type_overlap(). Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch --- arch/x86/kernel/cpu/mtrr/generic.c | 39 +++++++++++++++--------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 5d60b46187f7..005f07ebb3a3 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -78,31 +78,30 @@ static u64 get_mtrr_size(u64 mask) return size; } =20 +static u8 get_effective_type(u8 type1, u8 type2) +{ + if (type1 =3D=3D MTRR_TYPE_UNCACHABLE || type2 =3D=3D MTRR_TYPE_UNCACHABL= E) + return MTRR_TYPE_UNCACHABLE; + + if ((type1 =3D=3D MTRR_TYPE_WRBACK && type2 =3D=3D MTRR_TYPE_WRTHROUGH) || + (type1 =3D=3D MTRR_TYPE_WRTHROUGH && type2 =3D=3D MTRR_TYPE_WRBACK)) + return MTRR_TYPE_WRTHROUGH; + + if (type1 !=3D type2) + return MTRR_TYPE_UNCACHABLE; + + return type1; +} + /* * Check and return the effective type for MTRR-MTRR type overlap. - * Returns 1 if the effective type is UNCACHEABLE, else returns 0 + * Returns true if the effective type is UNCACHEABLE, else returns false */ -static int check_type_overlap(u8 *prev, u8 *curr) +static bool check_type_overlap(u8 *prev, u8 *curr) { - if (*prev =3D=3D MTRR_TYPE_UNCACHABLE || *curr =3D=3D MTRR_TYPE_UNCACHABL= E) { - *prev =3D MTRR_TYPE_UNCACHABLE; - *curr =3D MTRR_TYPE_UNCACHABLE; - return 1; - } - - if ((*prev =3D=3D MTRR_TYPE_WRBACK && *curr =3D=3D MTRR_TYPE_WRTHROUGH) || - (*prev =3D=3D MTRR_TYPE_WRTHROUGH && *curr =3D=3D MTRR_TYPE_WRBACK)) { - *prev =3D MTRR_TYPE_WRTHROUGH; - *curr =3D MTRR_TYPE_WRTHROUGH; - } + *prev =3D *curr =3D get_effective_type(*curr, *prev); =20 - if (*prev !=3D *curr) { - *prev =3D MTRR_TYPE_UNCACHABLE; - *curr =3D MTRR_TYPE_UNCACHABLE; - return 1; - } - - return 0; + return *prev =3D=3D MTRR_TYPE_UNCACHABLE; } =20 /** --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC6AAC6FD1D for ; Sat, 1 Apr 2023 06:38:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233552AbjDAGip (ORCPT ); Sat, 1 Apr 2023 02:38:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230193AbjDAGi1 (ORCPT ); Sat, 1 Apr 2023 02:38:27 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [IPv6:2001:67c:2178:6::1c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A6AB1BF5B for ; Fri, 31 Mar 2023 23:38:00 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 4070121A7A; Sat, 1 Apr 2023 06:37:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331078; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bwSaz6R/hqFIdk9RQ54LfqY77b02L677o5EAWpdjphI=; b=swx/QoA+37E0EjQsxMbKTi59tkfCEPsjAu3AWneVbkWCTRGeVvs7pKIHqOwxVrx5NHq06n 9ZK/jQ50ZGI9rqDIpb78oFcM1PSyTttyZWmJflusjoHsv3DtBPmrz+DbqSfDJt4qaiYyX8 8/RP3nFVtxz84YcAxjt2jllFwn7uX0s= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id ED9E2134FB; Sat, 1 Apr 2023 06:37:57 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 7e9dOEXRJ2R4dwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:37:57 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 11/15] x86/mtrr: construct a memory map with cache modes Date: Sat, 1 Apr 2023 08:36:48 +0200 Message-Id: <20230401063652.23522-12-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" After MTRR initialization construct a memory map with cache modes from MTRR values. This will speed up lookups via mtrr_lookup_type() especially in case of overlapping MTRRs. This will be needed when switching the semantics of the "uniform" parameter of mtrr_lookup_type() from "only covered by one MTRR" to "memory range has a uniform cache mode", which is the data the callers really want to know. Today this information is not easily available, in case MTRRs are not well sorted regarding base address. The map will be built in __initdata. When memory management is up, the map will be moved to dynamically allocated memory, in order to avoid the need of an overly large array. The size of this array is calculated using the number of variable MTRR registers and the needed size for fixed entries. Only add the map creation and expansion for now. The lookup will be added later. When writing new MTRR entries in the running system rebuild the map inside the call from mtrr_rendezvous_handler() in order to avoid nasty race conditions with concurrent lookups. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V5: - fix setting of mtrr_tom2 - change cache_map .type and .fixed to bitfields (Boris Petkov) - use memmove() (Boris Petkov) - a lot of comments (Boris Petkov) - rewrite setting of merge bools (Boris Petkov) - mark mtrr_build_map() as __init - add pr_info() (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/generic.c | 288 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/mtrr/mtrr.c | 10 +- arch/x86/kernel/cpu/mtrr/mtrr.h | 3 + 3 files changed, 300 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 005f07ebb3a3..fe8238832095 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -33,6 +33,38 @@ static struct fixed_range_block fixed_range_blocks[] =3D= { {} }; =20 +struct cache_map { + u64 start; + u64 end; + u64 flags; + u64 type:8; + u64 fixed:1; +}; + +/* + * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where + * no 2 adjacent ranges have the same cache mode (those would be merged). + * The number is based on the worst case: + * - no two adjacent fixed MTRRs share the same cache mode + * - one variable MTRR is spanning a huge area with mode WB + * - 255 variable MTRRs with mode UC all overlap with the WB MTRR, creatin= g 2 + * additional ranges each (result like "ababababa...aba" with a =3D WB, = b =3D UC), + * accounting for MTRR_MAX_VAR_RANGES * 2 - 1 range entries + * - a TOM2 area (even with overlapping an UC MTRR can't add 2 range entri= es + * to the possible maximum, as it always starts at 4GB, thus it can't be= in + * the middle of that MTRR, unless that MTRR starts at 0, which would re= move + * the initial "a" from the "abababa" pattern above) + * The map won't contain ranges with no matching MTRR (those fall back to = the + * default cache mode). + */ +#define CACHE_MAP_MAX (MTRR_NUM_FIXED_RANGES + MTRR_MAX_VAR_RANGES * 2) + +static struct cache_map init_cache_map[CACHE_MAP_MAX] __initdata; +static struct cache_map *cache_map __refdata =3D init_cache_map; +static unsigned int cache_map_size =3D CACHE_MAP_MAX; +static unsigned int cache_map_n; +static unsigned int cache_map_fixed; + static unsigned long smp_changes_mask; static int mtrr_state_set; u64 mtrr_tom2; @@ -78,6 +110,20 @@ static u64 get_mtrr_size(u64 mask) return size; } =20 +static u8 get_var_mtrr_state(unsigned int reg, u64 *start, u64 *size) +{ + struct mtrr_var_range *mtrr =3D mtrr_state.var_ranges + reg; + + if (!(mtrr->mask_lo & MTRR_MASK_VALID)) + return MTRR_TYPE_INVALID; + + *start =3D (((u64)mtrr->base_hi) << 32) + (mtrr->base_lo & PAGE_MASK); + *size =3D get_mtrr_size((((u64)mtrr->mask_hi) << 32) + + (mtrr->mask_lo & PAGE_MASK)); + + return mtrr->base_lo & MTRR_BASE_TYPE_MASK; +} + static u8 get_effective_type(u8 type1, u8 type2) { if (type1 =3D=3D MTRR_TYPE_UNCACHABLE || type2 =3D=3D MTRR_TYPE_UNCACHABL= E) @@ -242,6 +288,244 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 en= d, u64 *partial_end, return mtrr_state.def_type; } =20 +static void rm_map_entry_at(int idx) +{ + cache_map_n--; + memmove(cache_map + idx, cache_map + idx + 1, + sizeof(*cache_map) * (cache_map_n - idx)); +} + +/* + * Add an entry into cache_map at a specific index. Merges adjacent entri= es if + * appropriate. Return the number of merges for correcting the scan index + * (this is needed as merging will reduce the number of entries, which will + * result in skipping entries in future iterations if the scan index isn't + * corrected). + * Note that the corrected index can never go below -1 (resulting in being= 0 in + * the next scan iteration), as "2" is returned only if the current index = is + * larger than zero. + */ +static int add_map_entry_at(u64 start, u64 end, u8 type, int idx) +{ + bool merge_prev =3D false, merge_next =3D false; + + if (start >=3D end) + return 0; + + if (idx > 0) { + struct cache_map *prev =3D cache_map + idx - 1; + + if (!prev->fixed && start =3D=3D prev->end && type =3D=3D prev->type) + merge_prev =3D true; + } + + if (idx < cache_map_n) { + struct cache_map *next =3D cache_map + idx; + + if (!next->fixed && end =3D=3D next->start && type =3D=3D next->type) + merge_next =3D true; + } + + if (merge_prev && merge_next) { + cache_map[idx - 1].end =3D cache_map[idx].end; + rm_map_entry_at(idx); + return 2; + } + if (merge_prev) { + cache_map[idx - 1].end =3D end; + return 1; + } + if (merge_next) { + cache_map[idx].start =3D start; + return 1; + } + + /* Sanity check: the array should NEVER be too small! */ + if (cache_map_n =3D=3D cache_map_size) { + WARN(1, "MTRR cache mode memory map exhausted!\n"); + cache_map_n =3D cache_map_fixed; + return 0; + } + + memmove(cache_map + idx + 1, cache_map + idx, + sizeof(*cache_map) * (cache_map_n - idx)); + + cache_map[idx].start =3D start; + cache_map[idx].end =3D end; + cache_map[idx].type =3D type; + cache_map[idx].fixed =3D 0; + cache_map_n++; + + return 0; +} + +/* Clear a part of an entry. Return 1 if start of entry is still valid. */ +static int clr_map_range_at(u64 start, u64 end, int idx) +{ + int ret =3D start !=3D cache_map[idx].start; + u64 tmp; + + if (start =3D=3D cache_map[idx].start && end =3D=3D cache_map[idx].end) { + rm_map_entry_at(idx); + } else if (start =3D=3D cache_map[idx].start) { + cache_map[idx].start =3D end; + } else if (end =3D=3D cache_map[idx].end) { + cache_map[idx].end =3D start; + } else { + tmp =3D cache_map[idx].end; + cache_map[idx].end =3D start; + add_map_entry_at(end, tmp, cache_map[idx].type, idx + 1); + } + + return ret; +} + +/* + * Add MTRR to the map. The current map is scanned and each part of the M= TRR + * either overlapping with an existing entry or with a hole in the map is + * handled separately. + */ +static void add_map_entry(u64 start, u64 end, u8 type) +{ + u8 new_type, old_type; + u64 tmp; + int i; + + for (i =3D 0; i < cache_map_n && start < end; i++) { + if (start >=3D cache_map[i].end) + continue; + + if (start < cache_map[i].start) { + /* Region start has no overlap. */ + tmp =3D min(end, cache_map[i].start); + i -=3D add_map_entry_at(start, tmp, type, i); + start =3D tmp; + continue; + } + + new_type =3D get_effective_type(type, cache_map[i].type); + old_type =3D cache_map[i].type; + + if (cache_map[i].fixed || new_type =3D=3D old_type) { + /* Cut off start of new entry. */ + start =3D cache_map[i].end; + continue; + } + + /* Handle only overlapping part of region. */ + tmp =3D min(end, cache_map[i].end); + i +=3D clr_map_range_at(start, tmp, i); + i -=3D add_map_entry_at(start, tmp, new_type, i); + start =3D tmp; + } + + /* Add rest of region after last map entry (rest might be empty). */ + add_map_entry_at(start, end, type, i); +} + +/* Add variable MTRRs to cache map. */ +static void map_add_var(void) +{ + u64 start, size; + unsigned int i; + u8 type; + + /* + * Add AMD TOM2 MTRR. Can't be added in mtrr_build_map(), as it needs + * to be added again when rebuilding the map due to potentially having + * moved as a result of variable MTRRs for memory below 4GB. + */ + if (mtrr_tom2) { + add_map_entry(BIT_ULL(32), mtrr_tom2, MTRR_TYPE_WRBACK); + cache_map[cache_map_n - 1].fixed =3D 1; + } + + for (i =3D 0; i < num_var_ranges; i++) { + type =3D get_var_mtrr_state(i, &start, &size); + if (type !=3D MTRR_TYPE_INVALID) + add_map_entry(start, start + size, type); + } +} + +/* Rebuild map by replacing variable entries. */ +static void rebuild_map(void) +{ + cache_map_n =3D cache_map_fixed; + + map_add_var(); +} + +static unsigned int __init get_cache_map_size(void) +{ + return cache_map_fixed + 2 * num_var_ranges + (mtrr_tom2 !=3D 0); +} + +/* Build the cache_map containing the cache modes per memory range. */ +void __init mtrr_build_map(void) +{ + u64 start, end, size; + unsigned int i; + u8 type; + + if (!mtrr_state.enabled) + return; + + /* Add fixed MTRRs, optimize for adjacent entries with same type. */ + if (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED) { + /* + * Start with 64k size fixed entries, preset 1st one (hence the + * loop below is starting with index 1). + */ + start =3D 0; + end =3D size =3D 0x10000; + type =3D mtrr_state.fixed_ranges[0]; + + for (i =3D 1; i < MTRR_NUM_FIXED_RANGES; i++) { + /* 8 64k entries, then 16 16k ones, rest 4k. */ + if (i =3D=3D 8 || i =3D=3D 24) + size >>=3D 2; + + if (mtrr_state.fixed_ranges[i] !=3D type) { + add_map_entry(start, end, type); + start =3D end; + type =3D mtrr_state.fixed_ranges[i]; + } + end +=3D size; + } + add_map_entry(start, end, type); + } + + /* Mark fixed, they take precedence. */ + for (i =3D 0; i < cache_map_n; i++) + cache_map[i].fixed =3D 1; + cache_map_fixed =3D cache_map_n; + + map_add_var(); + + pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built fro= m %u variable MTRRs\n", + cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, + get_cache_map_size(), num_var_ranges + (mtrr_tom2 !=3D 0)); +} + +/* Copy the cache_map from __initdata memory to dynamically allocated one.= */ +void __init mtrr_copy_map(void) +{ + unsigned int new_size =3D get_cache_map_size(); + + if (!mtrr_state.enabled || !new_size) { + cache_map =3D NULL; + return; + } + + mutex_lock(&mtrr_mutex); + + cache_map =3D kcalloc(new_size, sizeof(*cache_map), GFP_KERNEL); + memmove(cache_map, init_cache_map, cache_map_n * sizeof(*cache_map)); + cache_map_size =3D new_size; + + mutex_unlock(&mtrr_mutex); +} + /** * mtrr_overwrite_state - set static MTRR state * @@ -834,6 +1118,10 @@ static void generic_set_mtrr(unsigned int reg, unsign= ed long base, =20 cache_enable(); local_irq_restore(flags); + + /* On the first CPU rebuild the cache mode memory map. */ + if (smp_processor_id() =3D=3D cpumask_first(cpu_online_mask)) + rebuild_map(); } =20 int generic_validate_add_page(unsigned long base, unsigned long size, diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 76f5b5e1128b..d44e4c2670cc 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -65,7 +65,7 @@ static bool mtrr_enabled(void) } =20 unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; -static DEFINE_MUTEX(mtrr_mutex); +DEFINE_MUTEX(mtrr_mutex); =20 u64 size_or_mask, size_and_mask; =20 @@ -660,6 +660,7 @@ void __init mtrr_bp_init(void) /* Software overwrite of MTRR state, only for generic case. */ mtrr_calc_physbits(true); init_table(); + mtrr_build_map(); pr_info("MTRRs set to read-only\n"); =20 return; @@ -697,6 +698,7 @@ void __init mtrr_bp_init(void) if (get_mtrr_state()) { memory_caching_control |=3D CACHE_MTRR; changed_by_mtrr_cleanup =3D mtrr_cleanup(phys_addr); + mtrr_build_map(); } else { mtrr_if =3D NULL; why =3D "by BIOS"; @@ -725,6 +727,12 @@ void mtrr_save_state(void) =20 static int __init mtrr_init_finialize(void) { + /* + * Map might exist if mtrr_overwrite_state() has been called or if + * mtrr_enabled() returns true. + */ + mtrr_copy_map(); + if (!mtrr_enabled()) return 0; =20 diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtr= r.h index a3c362d3d5bf..6246a1d8650b 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.h +++ b/arch/x86/kernel/cpu/mtrr/mtrr.h @@ -53,6 +53,7 @@ bool get_mtrr_state(void); =20 extern u64 size_or_mask, size_and_mask; extern const struct mtrr_ops *mtrr_if; +extern struct mutex mtrr_mutex; =20 extern unsigned int num_var_ranges; extern u64 mtrr_tom2; @@ -61,6 +62,8 @@ extern struct mtrr_state_type mtrr_state; void mtrr_state_warn(void); const char *mtrr_attrib_to_str(int x); void mtrr_wrmsr(unsigned, unsigned, unsigned); +void mtrr_build_map(void); +void mtrr_copy_map(void); =20 /* CPU specific mtrr_ops vectors. */ extern const struct mtrr_ops amd_mtrr_ops; --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA8D0C77B60 for ; Sat, 1 Apr 2023 06:39:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233575AbjDAGjK (ORCPT ); Sat, 1 Apr 2023 02:39:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233561AbjDAGiq (ORCPT ); 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Sat, 1 Apr 2023 06:38:03 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id N8d4KEvRJ2SDdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:38:03 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Michael Kelley Subject: [PATCH v5 12/15] x86/mtrr: use new cache_map in mtrr_type_lookup() Date: Sat, 1 Apr 2023 08:36:49 +0200 Message-Id: <20230401063652.23522-13-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of crawling through the MTRR register state, use the new cache_map for looking up the cache type(s) of a memory region. This allows now to set the uniform parameter according to the uniformity of the cache mode of the region, instead of setting it only if the complete region is mapped by a single MTRR. This now includes even the region covered by the fixed MTRR registers. Make sure uniform is always set. Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - new patch V3.1: - fix type_merge() (Michael Kelley) V4: - fix type_merge() again (Michael Kelley) --- arch/x86/kernel/cpu/mtrr/generic.c | 228 ++++------------------------- 1 file changed, 32 insertions(+), 196 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index fe8238832095..5d502b926dd8 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -139,155 +139,6 @@ static u8 get_effective_type(u8 type1, u8 type2) return type1; } =20 -/* - * Check and return the effective type for MTRR-MTRR type overlap. - * Returns true if the effective type is UNCACHEABLE, else returns false - */ -static bool check_type_overlap(u8 *prev, u8 *curr) -{ - *prev =3D *curr =3D get_effective_type(*curr, *prev); - - return *prev =3D=3D MTRR_TYPE_UNCACHABLE; -} - -/** - * mtrr_type_lookup_fixed - look up memory type in MTRR fixed entries - * - * Return the MTRR fixed memory type of 'start'. - * - * MTRR fixed entries are divided into the following ways: - * 0x00000 - 0x7FFFF : This range is divided into eight 64KB sub-ranges - * 0x80000 - 0xBFFFF : This range is divided into sixteen 16KB sub-ranges - * 0xC0000 - 0xFFFFF : This range is divided into sixty-four 4KB sub-rang= es - * - * Return Values: - * MTRR_TYPE_(type) - Matched memory type - * MTRR_TYPE_INVALID - Unmatched - */ -static u8 mtrr_type_lookup_fixed(u64 start, u64 end) -{ - int idx; - - if (start >=3D 0x100000) - return MTRR_TYPE_INVALID; - - /* 0x0 - 0x7FFFF */ - if (start < 0x80000) { - idx =3D 0; - idx +=3D (start >> 16); - return mtrr_state.fixed_ranges[idx]; - /* 0x80000 - 0xBFFFF */ - } else if (start < 0xC0000) { - idx =3D 1 * 8; - idx +=3D ((start - 0x80000) >> 14); - return mtrr_state.fixed_ranges[idx]; - } - - /* 0xC0000 - 0xFFFFF */ - idx =3D 3 * 8; - idx +=3D ((start - 0xC0000) >> 12); - return mtrr_state.fixed_ranges[idx]; -} - -/** - * mtrr_type_lookup_variable - look up memory type in MTRR variable entries - * - * Return Value: - * MTRR_TYPE_(type) - Matched memory type or default memory type (unmatche= d) - * - * Output Arguments: - * repeat - Set to 1 when [start:end] spanned across MTRR range and type - * returned corresponds only to [start:*partial_end]. Caller has - * to lookup again for [*partial_end:end]. - * - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. - */ -static u8 mtrr_type_lookup_variable(u64 start, u64 end, u64 *partial_end, - int *repeat, u8 *uniform) -{ - int i; - u64 base, mask; - u8 prev_match, curr_match; - - *repeat =3D 0; - *uniform =3D 1; - - prev_match =3D MTRR_TYPE_INVALID; - for (i =3D 0; i < num_var_ranges; ++i) { - unsigned short start_state, end_state, inclusive; - - if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_MASK_VALID)) - continue; - - base =3D (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + - (mtrr_state.var_ranges[i].base_lo & PAGE_MASK); - mask =3D (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) + - (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK); - - start_state =3D ((start & mask) =3D=3D (base & mask)); - end_state =3D ((end & mask) =3D=3D (base & mask)); - inclusive =3D ((start < base) && (end > base)); - - if ((start_state !=3D end_state) || inclusive) { - /* - * We have start:end spanning across an MTRR. - * We split the region into either - * - * - start_state:1 - * (start:mtrr_end)(mtrr_end:end) - * - end_state:1 - * (start:mtrr_start)(mtrr_start:end) - * - inclusive:1 - * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end) - * - * depending on kind of overlap. - * - * Return the type of the first region and a pointer - * to the start of next region so that caller will be - * advised to lookup again after having adjusted start - * and end. - * - * Note: This way we handle overlaps with multiple - * entries and the default type properly. - */ - if (start_state) - *partial_end =3D base + get_mtrr_size(mask); - else - *partial_end =3D base; - - if (unlikely(*partial_end <=3D start)) { - WARN_ON(1); - *partial_end =3D start + PAGE_SIZE; - } - - end =3D *partial_end - 1; /* end is inclusive */ - *repeat =3D 1; - *uniform =3D 0; - } - - if ((start & mask) !=3D (base & mask)) - continue; - - curr_match =3D mtrr_state.var_ranges[i].base_lo & - MTRR_BASE_TYPE_MASK; - if (prev_match =3D=3D MTRR_TYPE_INVALID) { - prev_match =3D curr_match; - continue; - } - - *uniform =3D 0; - if (check_type_overlap(&prev_match, &curr_match)) - return curr_match; - } - - if (prev_match !=3D MTRR_TYPE_INVALID) - return prev_match; - - return mtrr_state.def_type; -} - static void rm_map_entry_at(int idx) { cache_map_n--; @@ -580,6 +431,20 @@ void mtrr_overwrite_state(struct mtrr_var_range *var, = unsigned int num_var, mtrr_state_set =3D 1; } =20 +static u8 type_merge(u8 type, u8 new_type, u8 *uniform) +{ + u8 effective_type; + + if (type =3D=3D MTRR_TYPE_INVALID) + return new_type; + + effective_type =3D get_effective_type(type, new_type); + if (type !=3D effective_type) + *uniform =3D 0; + + return effective_type; +} + /** * mtrr_type_lookup - look up memory type in MTRR * @@ -588,66 +453,37 @@ void mtrr_overwrite_state(struct mtrr_var_range *var,= unsigned int num_var, * MTRR_TYPE_INVALID - MTRR is disabled * * Output Argument: - * uniform - Set to 1 when an MTRR covers the region uniformly, i.e. the - * region is fully covered by a single MTRR entry or the default - * type. + * uniform - Set to 1 when the returned MTRR type is valid for the whole + * region, set to 0 else. */ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) { - u8 type, prev_type, is_uniform =3D 1, dummy; - int repeat; - u64 partial_end; - - /* Make end inclusive instead of exclusive */ - end--; + u8 type =3D MTRR_TYPE_INVALID; + unsigned int i; =20 - if (!mtrr_state_set) + if (!mtrr_state_set) { + *uniform =3D 0; /* Uniformity is unknown. */ return MTRR_TYPE_INVALID; + } + + *uniform =3D 1; =20 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) return MTRR_TYPE_INVALID; =20 - /* - * Look up the fixed ranges first, which take priority over - * the variable ranges. - */ - if ((start < 0x100000) && - (mtrr_state.have_fixed) && - (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) { - is_uniform =3D 0; - type =3D mtrr_type_lookup_fixed(start, end); - goto out; - } - - /* - * Look up the variable ranges. Look of multiple ranges matching - * this address and pick type as per MTRR precedence. - */ - type =3D mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &is_uniform); + for (i =3D 0; i < cache_map_n && start < end; i++) { + if (start >=3D cache_map[i].end) + continue; + if (start < cache_map[i].start) + type =3D type_merge(type, mtrr_state.def_type, uniform); + type =3D type_merge(type, cache_map[i].type, uniform); =20 - /* - * Common path is with repeat =3D 0. - * However, we can have cases where [start:end] spans across some - * MTRR ranges and/or the default type. Do repeated lookups for - * that case here. - */ - while (repeat) { - prev_type =3D type; - start =3D partial_end; - is_uniform =3D 0; - type =3D mtrr_type_lookup_variable(start, end, &partial_end, - &repeat, &dummy); - - if (check_type_overlap(&prev_type, &type)) - goto out; + start =3D cache_map[i].end; } =20 - if (mtrr_tom2 && (start >=3D (1ULL<<32)) && (end < mtrr_tom2)) - type =3D MTRR_TYPE_WRBACK; + if (start < end) + type =3D type_merge(type, mtrr_state.def_type, uniform); =20 -out: - *uniform =3D is_uniform; return type; } =20 --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC3F6C77B60 for ; Sat, 1 Apr 2023 06:39:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233618AbjDAGjP (ORCPT ); Sat, 1 Apr 2023 02:39:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233532AbjDAGiy (ORCPT ); Sat, 1 Apr 2023 02:38:54 -0400 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 361D922E97 for ; Fri, 31 Mar 2023 23:38:29 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 9D556219FD; Sat, 1 Apr 2023 06:38:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331089; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=V3mHtqPo7I900IUU9mKC4TzJ6vMfpxeByTBPYTni3oA=; b=vLYErCtxmtJVZB4JAZxlvoZxl0KM5olB0YNHXZ6oMKkVa2hg3jOr9XLg+Ev7hH476WOehs 5ngjU22Qv75iC/FsbU+NWebMjFNQfy9eQPVUROKkUAKqmxeUcQY78nYMvVSwqbsti4ENwa aR+dlCzD+UQ1GXdQk6xc/xmnOxUBUv0= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 5376F134FB; Sat, 1 Apr 2023 06:38:09 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 5FgKE1HRJ2SJdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:38:09 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Linus Torvalds , Michael Kelley Subject: [PATCH v5 13/15] x86/mtrr: don't let mtrr_type_lookup() return MTRR_TYPE_INVALID Date: Sat, 1 Apr 2023 08:36:50 +0200 Message-Id: <20230401063652.23522-14-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mtrr_type_lookup() should always return a valid memory type. In case there is no information available, it should return the default UC. This will remove the last case where mtrr_type_lookup() can return MTRR_TYPE_INVALID, so adjust the comment in include/uapi/asm/mtrr.h. Note that removing the MTRR_TYPE_INVALID #define from that header could break user code, so it has to stay. At the same time the mtrr_type_lookup() stub for the !CONFIG_MTRR case should set uniform to 1, as if the memory range would be covered by no MTRR at all. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V2: - always set uniform - set uniform to 1 in case of disabled MTRRs (Linus Torvalds) V3: - adjust include/uapi/asm/mtrr.h comment --- arch/x86/include/asm/mtrr.h | 7 +++++-- arch/x86/include/uapi/asm/mtrr.h | 6 +++--- arch/x86/kernel/cpu/mtrr/generic.c | 4 ++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 6decb18e22ed..b17a66da1237 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -77,9 +77,12 @@ static inline void mtrr_overwrite_state(struct mtrr_var_= range *var, static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform) { /* - * Return no-MTRRs: + * Return the default MTRR type, without any known other types in + * that range. */ - return MTRR_TYPE_INVALID; + *uniform =3D 1; + + return MTRR_TYPE_UNCACHABLE; } #define mtrr_save_fixed_ranges(arg) do {} while (0) #define mtrr_save_state() do {} while (0) diff --git a/arch/x86/include/uapi/asm/mtrr.h b/arch/x86/include/uapi/asm/m= trr.h index 376563f2bac1..4aa05c2ffa78 100644 --- a/arch/x86/include/uapi/asm/mtrr.h +++ b/arch/x86/include/uapi/asm/mtrr.h @@ -115,9 +115,9 @@ struct mtrr_state_type { #define MTRR_NUM_TYPES 7 =20 /* - * Invalid MTRR memory type. mtrr_type_lookup() returns this value when - * MTRRs are disabled. Note, this value is allocated from the reserved - * values (0x7-0xff) of the MTRR memory types. + * Invalid MTRR memory type. No longer used outside of MTRR code. + * Note, this value is allocated from the reserved values (0x7-0xff) of + * the MTRR memory types. */ #define MTRR_TYPE_INVALID 0xff =20 diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 5d502b926dd8..178253d117c6 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -463,13 +463,13 @@ u8 mtrr_type_lookup(u64 start, u64 end, u8 *uniform) =20 if (!mtrr_state_set) { *uniform =3D 0; /* Uniformity is unknown. */ - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; } =20 *uniform =3D 1; =20 if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED)) - return MTRR_TYPE_INVALID; + return MTRR_TYPE_UNCACHABLE; =20 for (i =3D 0; i < cache_map_n && start < end; i++) { if (start >=3D cache_map[i].end) --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62A13C6FD1D for ; Sat, 1 Apr 2023 06:39:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233560AbjDAGjI (ORCPT ); Sat, 1 Apr 2023 02:39:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233551AbjDAGip (ORCPT ); Sat, 1 Apr 2023 02:38:45 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A468B20DB7 for ; Fri, 31 Mar 2023 23:38:23 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 6510F1FD6D; Sat, 1 Apr 2023 06:38:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331095; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PLhZnRzaTF/w19VvaTwREzeMUwLtgou6VVO1Iy9aXOI=; b=hlJX4+mn92AjAhl6PYx0T3gUWvKaL2etfSkUjXhW4rfmimMPLmlIg0hjuaB7X7gZP/vVQ+ 0wYDXpajnNGpXf6sBmava6k/WHQ2InPTViQQljFPd1R7lLImrKDpprLUmY4nHw4wKvj18x Gi+mz7kqtLf55Tk2X+Cq4e90o84NV7U= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 10565134FB; Sat, 1 Apr 2023 06:38:15 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 2ZmXAlfRJ2SQdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:38:15 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Linus Torvalds , Michael Kelley Subject: [PATCH v5 14/15] x86/mm: only check uniform after calling mtrr_type_lookup() Date: Sat, 1 Apr 2023 08:36:51 +0200 Message-Id: <20230401063652.23522-15-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Today pud_set_huge() and pmd_set_huge() test for the MTRR type to be WB or INVALID after calling mtrr_type_lookup(). Those tests can be dropped, as the only reason to not use a large mapping would be uniform being 0. Any MTRR type can be accepted as long as it applies to the whole memory range covered by the mapping, as the alternative would only be to map the same region with smaller pages instead, using the same PAT type as for the large mapping. Suggested-by: Linus Torvalds Signed-off-by: Juergen Gross Tested-by: Michael Kelley --- V3: - adapt comment for pud_set_huge() --- arch/x86/mm/pgtable.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c index e4f499eb0f29..15a8009a4480 100644 --- a/arch/x86/mm/pgtable.c +++ b/arch/x86/mm/pgtable.c @@ -702,14 +702,8 @@ void p4d_clear_huge(p4d_t *p4d) * pud_set_huge - setup kernel PUD mapping * * MTRRs can override PAT memory types with 4KiB granularity. Therefore, t= his - * function sets up a huge page only if any of the following conditions ar= e met: - * - * - MTRRs are disabled, or - * - * - MTRRs are enabled and the range is completely covered by a single MTR= R, or - * - * - MTRRs are enabled and the corresponding MTRR memory type is WB, which - * has no effect on the requested PAT memory type. + * function sets up a huge page only if the complete range has the same MT= RR + * caching mode. * * Callers should try to decrease page size (1GB -> 2MB -> 4K) if the bigg= er * page mapping attempt fails. @@ -718,11 +712,10 @@ void p4d_clear_huge(p4d_t *p4d) */ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; =20 - mtrr =3D mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); - if ((mtrr !=3D MTRR_TYPE_INVALID) && (!uniform) && - (mtrr !=3D MTRR_TYPE_WRBACK)) + mtrr_type_lookup(addr, addr + PUD_SIZE, &uniform); + if (!uniform) return 0; =20 /* Bail out if we are we on a populated non-leaf entry: */ @@ -745,11 +738,10 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot= _t prot) */ int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot) { - u8 mtrr, uniform; + u8 uniform; =20 - mtrr =3D mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); - if ((mtrr !=3D MTRR_TYPE_INVALID) && (!uniform) && - (mtrr !=3D MTRR_TYPE_WRBACK)) { + mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform); + if (!uniform) { pr_warn_once("%s: Cannot satisfy [mem %#010llx-%#010llx] with a huge-pag= e mapping due to MTRR override.\n", __func__, addr, addr + PMD_SIZE); return 0; --=20 2.35.3 From nobody Tue Feb 10 06:06:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79795C76196 for ; Sat, 1 Apr 2023 06:39:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233397AbjDAGjM (ORCPT ); Sat, 1 Apr 2023 02:39:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233565AbjDAGir (ORCPT ); Sat, 1 Apr 2023 02:38:47 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 130AE21AA8 for ; Fri, 31 Mar 2023 23:38:25 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 0CFD31FD78; Sat, 1 Apr 2023 06:38:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1680331101; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E7DHxTtJvlqvZrPXbQiV8NhXaH2BVGP/WAcxWNnt620=; b=G372kCwacV4DxPuUb7YsrKwAhoclIcxKTpoMLXIgetyWZQDNwL2mQE7gyFkHku5RACdJgI Rg2qoMbOhcsjptTaKLjKxNhMgIQLY4XoxdCloH3/L/Y7eAfEsSQvTRZkJR1OrkxuUvwfwU DIGcr9i7AwC2vtvVTTQNIr5v1Nn9WgA= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id C59F7134FB; Sat, 1 Apr 2023 06:38:20 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id z1P/LlzRJ2SZdwAAMHmgww (envelope-from ); Sat, 01 Apr 2023 06:38:20 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v5 15/15] x86/mtrr: remove unused code Date: Sat, 1 Apr 2023 08:36:52 +0200 Message-Id: <20230401063652.23522-16-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230401063652.23522-1-jgross@suse.com> References: <20230401063652.23522-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" mtrr_centaur_report_mcr() isn't used by anyone, so it can be removed. Signed-off-by: Juergen Gross --- V5: - new patch --- arch/x86/include/asm/mtrr.h | 4 ---- arch/x86/kernel/cpu/mtrr/centaur.c | 9 --------- 2 files changed, 13 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index b17a66da1237..3aced3568e2b 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -60,7 +60,6 @@ extern int mtrr_add_page(unsigned long base, unsigned lon= g size, unsigned int type, bool increment); extern int mtrr_del(int reg, unsigned long base, unsigned long size); extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); -extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); extern void mtrr_bp_restore(void); extern int mtrr_trim_uncached_memory(unsigned long end_pfn); extern int amd_special_default_mtrr(void); @@ -108,9 +107,6 @@ static inline int mtrr_trim_uncached_memory(unsigned lo= ng end_pfn) { return 0; } -static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ -} #define mtrr_bp_init() do {} while (0) #define mtrr_bp_restore() do {} while (0) #define mtrr_disable() do {} while (0) diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/= centaur.c index 4466ddeb0125..6f6c3ae92943 100644 --- a/arch/x86/kernel/cpu/mtrr/centaur.c +++ b/arch/x86/kernel/cpu/mtrr/centaur.c @@ -45,15 +45,6 @@ centaur_get_free_region(unsigned long base, unsigned lon= g size, int replace_reg) return -ENOSPC; } =20 -/* - * Report boot time MCR setups - */ -void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) -{ - centaur_mcr[mcr].low =3D lo; - centaur_mcr[mcr].high =3D hi; -} - static void centaur_get_mcr(unsigned int reg, unsigned long *base, unsigned long *size, mtrr_type * type) --=20 2.35.3