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[104.53.165.62]) by smtp.gmail.com with ESMTPSA id g11-20020a4a894b000000b0053bb2ae3a78sm1299277ooi.24.2023.03.31.14.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 14:58:28 -0700 (PDT) From: Andrew Halaney To: linux-kernel@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, bmasney@redhat.com, echanude@redhat.com, ncai@quicinc.com, jsuraj@qti.qualcomm.com, hisunil@quicinc.com, Andrew Halaney Subject: [PATCH v3 3/3] arm64: dts: qcom: sa8540p-ride: Add ethernet nodes Date: Fri, 31 Mar 2023 16:58:04 -0500 Message-Id: <20230331215804.783439-4-ahalaney@redhat.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230331215804.783439-1-ahalaney@redhat.com> References: <20230331215804.783439-1-ahalaney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable both the MACs found on the board. ethernet0 and ethernet1 both ultimately go to a series of on board switches which aren't managed by this processor. ethernet0 is connected to a Marvell 88EA1512 phy via RGMII. That goes to the series of switches via SGMII on the "media" side of the phy. RGMII_SGMII mode is enabled via devicetree register descriptions. The switch on the "media" side has auto-negotiation disabled, so configuration from userspace similar to: ethtool -s eth0 autoneg off speed 1000 duplex full is necessary to get traffic flowing on that interface. ethernet1 is in a mac2mac/fixed-link configuration going to the same series of switches directly via RGMII. Signed-off-by: Andrew Halaney --- Changes since v1 and v2: * None arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 181 ++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8540p-ride.dts index 40db5aa0803c..eb230265aa45 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -28,6 +28,65 @@ aliases { chosen { stdout-path =3D "serial0:115200n8"; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <1>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; }; =20 &apps_rsc { @@ -151,6 +210,68 @@ vreg_l8g: ldo8 { }; }; =20 +ðernet0 { + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + + max-speed =3D <1000>; + phy-handle =3D <&rgmii_phy>; + phy-mode =3D "rgmii-txid"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <ðernet0_default>; + + status =3D "okay"; + + mdio { + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + + compatible =3D "snps,dwmac-mdio"; + + /* Marvell 88EA1512 */ + rgmii_phy: phy@8 { + reg =3D <0x8>; + + interrupt-parent =3D <&tlmm>; + interrupts-extended =3D <&tlmm 127 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios =3D <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + + device_type =3D "ethernet-phy"; + + /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation + * from userspace to talk to the switch on the SGMII side of things + */ + marvell,reg-init =3D + /* Set MODE[2:0] to RGMII_SGMII */ + <0x12 0x14 0xfff8 0x4>, + /* Soft reset required after changing MODE[2:0] */ + <0x12 0x14 0x7fff 0x8000>; + }; + }; +}; + +ðernet1 { + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + + max-speed =3D <1000>; + phy-mode =3D "rgmii-txid"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <ðernet1_default>; + + status =3D "okay"; + + fixed-link { + speed =3D <1000>; + full-duplex; + }; +}; + &i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&i2c0_default>; @@ -316,6 +437,66 @@ &xo_board_clk { /* PINCTRL */ =20 &tlmm { + ethernet0_default: ethernet0-default-state { + mdc-pins { + pins =3D "gpio175"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-pull-up; + }; + + mdio-pins { + pins =3D "gpio176"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins =3D "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio18= 8"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins =3D "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio18= 2"; + function =3D "rgmii_0"; + drive-strength =3D <16>; + bias-disable; + }; + }; + + ethernet1_default: ethernet1-default-state { + mdc-pins { + pins =3D "gpio97"; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-pull-up; + }; + + mdio-pins { + pins =3D "gpio98"; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-tx-pins { + pins =3D "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio11= 0"; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-pull-up; + }; + + rgmii-rx-pins { + pins =3D "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104= "; + function =3D "rgmii_1"; + drive-strength =3D <16>; + bias-disable; + }; + }; + i2c0_default: i2c0-default-state { /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ pins =3D "gpio135", "gpio136"; --=20 2.39.2