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[104.53.165.62]) by smtp.gmail.com with ESMTPSA id g11-20020a4a894b000000b0053bb2ae3a78sm1299277ooi.24.2023.03.31.14.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 14:58:22 -0700 (PDT) From: Andrew Halaney To: linux-kernel@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, bmasney@redhat.com, echanude@redhat.com, ncai@quicinc.com, jsuraj@qti.qualcomm.com, hisunil@quicinc.com, Andrew Halaney Subject: [PATCH v3 1/3] clk: qcom: gcc-sc8280xp: Add EMAC GDSCs Date: Fri, 31 Mar 2023 16:58:02 -0500 Message-Id: <20230331215804.783439-2-ahalaney@redhat.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230331215804.783439-1-ahalaney@redhat.com> References: <20230331215804.783439-1-ahalaney@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the EMAC GDSCs to allow the EMAC hardware to be enabled. Acked-by: Stephen Boyd Reviewed-by: Konrad Dybcio Signed-off-by: Andrew Halaney --- Changes since v2: * Add Konrad's Reviewed-by Changes since v1: * Add Stephen's Acked-by * Explicitly tested on x13s laptop with no noticeable side effect (Konr= ad) drivers/clk/qcom/gcc-sc8280xp.c | 18 ++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc8280xp.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280x= p.c index b3198784e1c3..04a99dbaa57e 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -6873,6 +6873,22 @@ static struct gdsc usb30_sec_gdsc =3D { .pwrsts =3D PWRSTS_RET_ON, }; =20 +static struct gdsc emac_0_gdsc =3D { + .gdscr =3D 0xaa004, + .pd =3D { + .name =3D "emac_0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc emac_1_gdsc =3D { + .gdscr =3D 0xba004, + .pd =3D { + .name =3D "emac_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + static struct clk_regmap *gcc_sc8280xp_clocks[] =3D { [GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK] =3D &gcc_aggre_noc_pcie0_tunnel_axi_= clk.clkr, [GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK] =3D &gcc_aggre_noc_pcie1_tunnel_axi_= clk.clkr, @@ -7351,6 +7367,8 @@ static struct gdsc *gcc_sc8280xp_gdscs[] =3D { [USB30_MP_GDSC] =3D &usb30_mp_gdsc, [USB30_PRIM_GDSC] =3D &usb30_prim_gdsc, [USB30_SEC_GDSC] =3D &usb30_sec_gdsc, + [EMAC_0_GDSC] =3D &emac_0_gdsc, + [EMAC_1_GDSC] =3D &emac_1_gdsc, }; =20 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bin= dings/clock/qcom,gcc-sc8280xp.h index cb2fb638825c..721105ea4fad 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h @@ -492,5 +492,7 @@ #define USB30_MP_GDSC 9 #define USB30_PRIM_GDSC 10 #define USB30_SEC_GDSC 11 +#define EMAC_0_GDSC 12 +#define EMAC_1_GDSC 13 =20 #endif --=20 2.39.2