From nobody Tue Sep 9 16:54:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4842C6FD18 for ; Fri, 31 Mar 2023 09:01:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232001AbjCaJB6 (ORCPT ); Fri, 31 Mar 2023 05:01:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231952AbjCaJBR (ORCPT ); Fri, 31 Mar 2023 05:01:17 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48B3E1E72F; Fri, 31 Mar 2023 02:01:11 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32V912lX005871; Fri, 31 Mar 2023 04:01:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680253262; bh=OlWO5jrT2jfnnwKSAjPVq9NARge1RAycM4qFZ708ejk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TAICsLjFqeNgsse2dRk3gPTddpSZBZV/T8WSuE4PJUUu4Yj7gwmrPhuc/TBOPanjD mhzjANuP2JzCeZFtKJmO1f9JorzoCZpGY9QrZcBPeCWw/adCJatXUx7o1ppc5YoRkc 8zjUHWBxs0Zb8VN4W+ngc3Fg7VNH49pi7gJdeIPg= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32V912CS030081 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 31 Mar 2023 04:01:02 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 31 Mar 2023 04:01:02 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 31 Mar 2023 04:01:02 -0500 Received: from uda0500640.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32V90Sug125579; Fri, 31 Mar 2023 04:00:59 -0500 From: Ravi Gunasekaran To: , , , , , , , , CC: , , Subject: [PATCH v14 8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Date: Fri, 31 Mar 2023 14:30:28 +0530 Message-ID: <20230331090028.8373-9-r-gunasekaran@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230331090028.8373-1-r-gunasekaran@ti.com> References: <20230331090028.8373-1-r-gunasekaran@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Aswath Govindraju x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran --- Changes from v13: * No changes. Only rebased on top of linux-next Changes from v12: * No change Changes from v11: * No change Changes from v10: * Removed Link tag from commit message Changes from v9: * No change Changes from v8: * No change Changes from v7: * No change Changes from v6: * Removed pcie_ep node update Changes from v5: * No change Changes from v4: * No change Changes from v3: * No change Changes from v2: * Patch newly added to the series arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e6d99f19a55f..90f90b7b37e1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -401,6 +401,14 @@ }; }; =20 +&pcie1_rc { + status =3D "okay"; + reset-gpios =3D <&exp1 2 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes0_pcie_link>; + phy-names =3D "pcie-phy"; + num-lanes =3D <1>; +}; + &mcu_mcan0 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.17.1