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[35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:13 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 01/10] mtd: spi-nor: core: Move generic method to core - micron_st_nor_set_4byte_addr_mode Date: Fri, 31 Mar 2023 07:45:57 +0000 Message-Id: <20230331074606.3559258-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Move the method to core. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 24 ++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/micron-st.c | 24 ------------------------ 3 files changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 9e6a0730cdb8..d104c81f22c5 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -538,6 +538,30 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, b= ool enable) return ret; } =20 +/** + * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and + * Micron flashes. + * @nor: pointer to 'struct spi_nor'. + * @enable: true to enter the 4-byte address mode, false to exit the 4-byte + * address mode. + * + * Return: 0 on success, -errno otherwise. + */ +int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +{ + int ret; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + + ret =3D spi_nor_set_4byte_addr_mode(nor, enable); + if (ret) + return ret; + + return spi_nor_write_disable(nor); +} + /** * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion * flashes. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index de31e430f77e..d5cb42245820 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -648,6 +648,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); +int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_prep_and_lock(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 7bb86df52f0b..3bbf65234ebd 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -301,30 +301,6 @@ static const struct flash_info st_nor_parts[] =3D { { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) }, }; =20 -/** - * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and - * Micron flashes. - * @nor: pointer to 'struct spi_nor'. - * @enable: true to enter the 4-byte address mode, false to exit the 4-byte - * address mode. - * - * Return: 0 on success, -errno otherwise. - */ -static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool ena= ble) -{ - int ret; - - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - ret =3D spi_nor_set_4byte_addr_mode(nor, enable); - if (ret) - return ret; - - return spi_nor_write_disable(nor); -} - /** * micron_st_nor_read_fsr() - Read the Flag Status Register. * @nor: pointer to 'struct spi_nor' --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22A53C77B60 for ; Fri, 31 Mar 2023 07:46:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231179AbjCaHqd (ORCPT ); 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[35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:13 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 02/10] mtd: spi-nor: core: Update name and description of micron_st_nor_set_4byte_addr_mode Date: Fri, 31 Mar 2023 07:45:58 +0000 Message-Id: <20230331074606.3559258-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rename method to spi_nor_set_4byte_addr_mode_wren_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 7 ++++--- drivers/mtd/spi-nor/core.h | 3 ++- drivers/mtd/spi-nor/micron-st.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index d104c81f22c5..07be81afdc33 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -539,15 +539,16 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, = bool enable) } =20 /** - * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and - * Micron flashes. + * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode = using + * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically = used + * by ST and Micron flashes. * @nor: pointer to 'struct spi_nor'. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte * address mode. * * Return: 0 on success, -errno otherwise. */ -int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool e= nable) { int ret; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index d5cb42245820..d8e3fd60d6ee 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -648,7 +648,8 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); -int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, + bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_prep_and_lock(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 3bbf65234ebd..a75f0f4e1c38 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -425,7 +425,7 @@ static void micron_st_nor_default_init(struct spi_nor *= nor) nor->flags |=3D SNOR_F_HAS_LOCK; nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; nor->params->quad_enable =3D NULL; - nor->params->set_4byte_addr_mode =3D micron_st_nor_set_4byte_addr_mode; + nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4= b_ex4b; } =20 static void micron_st_nor_late_init(struct spi_nor *nor) --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 902E0C6FD18 for ; Fri, 31 Mar 2023 07:46:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231225AbjCaHqi (ORCPT ); Fri, 31 Mar 2023 03:46:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230381AbjCaHqT (ORCPT ); Fri, 31 Mar 2023 03:46:19 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D99351A442 for ; Fri, 31 Mar 2023 00:46:16 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id g19so14675948lfr.9 for ; Fri, 31 Mar 2023 00:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680248775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5pMraFU/tPRiVpv9JeCuToE/iyKjmq4cdy7RBmS30j8=; b=a2xc6P3BIbU9HViqxC5luoJqe1Z5BNokKvWSvidpmBZQN5PNJhVz3uxhS4mrWBLcpg hef4LAuCVpK8v/EBNUUMDskjn01qaaAJ1nIhSRWQTYo4IOAmY5lMLmNe98tDHkWfIlMs oPcADQLgvvqQwX3XhD6G4mFy+L/9CaaLvpUEmbr8RUVaGZ7UTw3tZ9q6vfMjVtgUE7um 1m7mTbjJUbmYyu/i46Ys1VUVzZzfg85pc/nUjZxux1XulbTJl06No2LT2LJIXbond1jO t9sOIpwsVQudNbF5FAr8rpk1YWaBTB0zaZKEEHAqOHZzG8ZMm2pV3L6WxF9Kx28ffJYy GaLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680248775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5pMraFU/tPRiVpv9JeCuToE/iyKjmq4cdy7RBmS30j8=; b=j/EDGytm0q63yCB/uEMQX8jhEk9LJ6FPbP8o5LNFsERHi2klmz0dFPa6bn2slHysZ/ yHFwsli1qlGio94D0zH61bwdSBOr3b9/elo9vw3VePIajrUI3+Z3eVSwjUDkog9+3n3J 7ySpEFkTfuB+EdZM5odtmc8kv3350aAxUaRDn1Lfg8WwlpiBPb/C3PDp37QHzbPMTDg9 qs9XikMaK2WbC0Gp5Rij3Y8h5GKqADdUF/SfG+e8dkb4qu41YgklBJg6rx9Om28iGOWI p3hQ4mwffEihcH/t5v7NwcnhFEklTp0WsLLZtOncYl8sFdc7edhBsfIcyf5LTPSpaSsS X+7A== X-Gm-Message-State: AAQBX9ftNjFAJ0WndWcBvEUADaCvJ1UuowyAX7wArFurabkNYNBzSgCr 4f+Ut2lfUt9D8qPIXZzQlxcf5mQyxtxEHHDyaZGeIg== X-Google-Smtp-Source: AKy350bGAI8Dt1/8LPSgMhIVrpvYp0Y5IEXcym6m0mizAvSfJXRcOZFguoi74BWJ/MBVXaYwXCP2Ww== X-Received: by 2002:a19:c20a:0:b0:4a4:68b9:60ae with SMTP id l10-20020a19c20a000000b004a468b960aemr8189955lfc.57.1680248775241; Fri, 31 Mar 2023 00:46:15 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:14 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 03/10] mtd: spi-nor: core: Update name and description of spansion_set_4byte_addr_mode Date: Fri, 31 Mar 2023 07:45:59 +0000 Message-Id: <20230331074606.3559258-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rename method to spi_nor_set_4byte_addr_mode_brwr and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(28) and BIT(20). Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 07be81afdc33..e8f6141c0ef6 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -564,15 +564,20 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct= spi_nor *nor, bool enable) } =20 /** - * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion - * flashes. + * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using + * SPINOR_OP_BRWR. Typically used by Spansion flashes. * @nor: pointer to 'struct spi_nor'. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte * address mode. * + * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]= ) is + * used to enable/disable 4-byte address mode. When MSB is set to =E2=80= =981=E2=80=99, 4-byte + * address mode is active and A[30:24] bits are don=E2=80=99t care. Write = instruction is + * SPINOR_OP_BRWR(17h) with 1 byte of data. + * * Return: 0 on success, -errno otherwise. */ -static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +static int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enab= le) { int ret; =20 @@ -2964,7 +2969,7 @@ static void spi_nor_init_default_params(struct spi_no= r *nor) struct device_node *np =3D spi_nor_get_flash_node(nor); =20 params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; - params->set_4byte_addr_mode =3D spansion_set_4byte_addr_mode; + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; params->otp.org =3D &info->otp_org; =20 /* Default to 16-bit Write Status (01h) Command */ --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66FF7C77B60 for ; Fri, 31 Mar 2023 07:46:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231238AbjCaHql (ORCPT ); Fri, 31 Mar 2023 03:46:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230403AbjCaHqU (ORCPT ); Fri, 31 Mar 2023 03:46:20 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FC001B34E for ; Fri, 31 Mar 2023 00:46:17 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id h9so22150970ljq.2 for ; Fri, 31 Mar 2023 00:46:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680248776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VskMtKqJo2Tm6jcABPqz9otpp15wXPXFPfERL76lmb8=; b=Elu0oDZbKYEaJk3BPLEWS5s8WTLK+AaaOOVyg0VGUguJTbOOn25MNKzUV3tCoWCCTT BiCRfHHRXXZZfUOACZrGAK/qaOzRs15WE+pgplX+7qZd9dAz9/KW7RTSEq99zR0Gp2x1 DxqR6vFs5pY6d4hICY+TzZynuFIi5us7VYuUJ+I0V6rObnijrCZ+xO6O1skXCrc8zk7j CY/YPA+MFqglO4ThyH56V+xL3ZPK2fnHJND6e1XCMR/BDhrUWqJx6EB4VHdK4GlRkHbw 3mdt1XI4rrMwBJCs61qe3pXW6gUTl1aQr6S1DLRxkrfqFLm5mb9Owc7LYEwPMqNlTF6T 0GYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680248776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VskMtKqJo2Tm6jcABPqz9otpp15wXPXFPfERL76lmb8=; b=0onBUBLdBTGmEqlNGUR+wzOBuOgKsgbMvk7NWqnSEIafLmOuQX/aFae3jIsfjOEMez xqg5aM5WOfpE0ys4mWZY3ABeJTextnkmuiUdxq3IDIdf7PtRPGVjq836wDP0t+JmghnA UtuC4OJrlawa7/H3h78xDO0TkP8nz3BlS0b2HJumGDqUbQSvY6JxLA9Q9PBJJzwwFCEy iQ08OrVeNpsHVBRB20updo1GuOa2rYjhh+023ifimanNqjQzwYjxxcLZiAOBanKMgQ06 lyF6BtOvyvsvuEOnfDiwGIu08U9cNZ6++TDh2/cwytYVinmu2ynBdt/hT6R/bB0fPPhb pxkw== X-Gm-Message-State: AAQBX9cCXJmwEan7Cg8+99RXC3O+UUoEb3EzUO3V+VQ1EQe+ruiXEu0m V3M5g9djH9DyhMzGYMBCJbYLIg== X-Google-Smtp-Source: AKy350aAhXaohE8Hvyy3v/ekKM2Vs2P+IJ8jEz+Nt0k2TBTY5ykvbGfHN5gWB273oUVJ87tLm+i9Rg== X-Received: by 2002:a2e:320a:0:b0:298:b03d:5715 with SMTP id y10-20020a2e320a000000b00298b03d5715mr8307472ljy.25.1680248775893; Fri, 31 Mar 2023 00:46:15 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:15 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 04/10] mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_mode Date: Fri, 31 Mar 2023 07:46:00 +0000 Message-Id: <20230331074606.3559258-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rename method to spi_nor_set_4byte_addr_mode_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(31) and BIT(23). Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 8 +++++--- drivers/mtd/spi-nor/core.h | 2 +- drivers/mtd/spi-nor/macronix.c | 2 +- drivers/mtd/spi-nor/winbond.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index e8f6141c0ef6..4c9264e427ff 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -508,14 +508,16 @@ int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) } =20 /** - * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode. + * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode + * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by + * Winbond and Macronix. * @nor: pointer to 'struct spi_nor'. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte * address mode. * * Return: 0 on success, -errno otherwise. */ -int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable) { int ret; =20 @@ -556,7 +558,7 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct s= pi_nor *nor, bool enable) if (ret) return ret; =20 - ret =3D spi_nor_set_4byte_addr_mode(nor, enable); + ret =3D spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable); if (ret) return ret; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index d8e3fd60d6ee..067945c10023 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -647,7 +647,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, const enum spi_nor_protocol proto); int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); -int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable= ); int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 6853ec9ae65d..91a8fa7d4512 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -105,7 +105,7 @@ static const struct flash_info macronix_nor_parts[] =3D= { static void macronix_nor_default_init(struct spi_nor *nor) { nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; - nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode; + nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex4= b; } =20 static const struct spi_nor_fixups macronix_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index ca39acf4112c..9cea241c204b 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -188,7 +188,7 @@ static int winbond_nor_set_4byte_addr_mode(struct spi_n= or *nor, bool enable) { int ret; =20 - ret =3D spi_nor_set_4byte_addr_mode(nor, enable); + ret =3D spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable); if (ret || enable) return ret; =20 --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F582C6FD18 for ; Fri, 31 Mar 2023 07:46:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231260AbjCaHqq (ORCPT ); Fri, 31 Mar 2023 03:46:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230522AbjCaHqU (ORCPT ); Fri, 31 Mar 2023 03:46:20 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97E921A964 for ; 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[35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:16 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 05/10] mtd: spi-nor: core: Make spi_nor_set_4byte_addr_mode_brwr public Date: Fri, 31 Mar 2023 07:46:01 +0000 Message-Id: <20230331074606.3559258-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This method can be retrieved at BFPT parsing time. The method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(28) and BIT(20). Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4c9264e427ff..75d28224ec62 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -579,7 +579,7 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct s= pi_nor *nor, bool enable) * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enab= le) +int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable) { int ret; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 067945c10023..8953ddeb8625 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -650,6 +650,7 @@ int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable= ); int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_prep_and_lock(struct spi_nor *nor); --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7AD6C77B60 for ; Fri, 31 Mar 2023 07:46:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231153AbjCaHq5 (ORCPT ); Fri, 31 Mar 2023 03:46:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46848 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231146AbjCaHqW (ORCPT ); Fri, 31 Mar 2023 03:46:22 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F6BF1A977 for ; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id a44so3487151ljr.10 for ; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680248777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z0sigra06UdM0F1urZc+vocV5eG5WzPi+hGexEngKTU=; b=X1ikQu7cdVcNDirIDWCbHY2Av890uHn1f8iauR36T1CANNByjkJ1iiwjbcMyepMkhy 3zHuugsWwW1UD5blKh/Y6ow0NvoRRAFjhxte2PhIYV9od2DIPk1RnShAaB5yQhJtTuun Jqx4AhYxg9AeQ5RZ3SY1+XlHMcvxszYR2H4+4+sH4vK4RHEoLeV1WSd7m305olcjd8de QAO0EloURtLBc8lM9d42gTGYGsL45Jqo/5fdHRTh0yhWdb4QAn4dC0bn5Ul4050sKEmy 3/xkSRbzi/v2OJF1rY4drkWQ2AYkBiZ1b0roO/GJtoA7RBhCYLBW9oENWCxJH8mjpiyY 6BRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680248777; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z0sigra06UdM0F1urZc+vocV5eG5WzPi+hGexEngKTU=; b=0n6NeDxnkuL2OsBIsoTvIvsRZCUJ/WcoXL5P3ktZC2sjqDoe/FiPqPYWXDjo75ODTf kOzRpn3TOC22dbNH1ruQl69pkEBrVsBuu+EdEJnrlCGmrWT3MscasA2TGjwFn/bYuro9 zbf7B9B7qNQDuYjn5g6Dy8806Rga4dkPeKgsHxQSbDepT6ZZEk9b5SF9GJtcF0m4eIyS Y3R0HMQE2Ii9CvP29ElyzMPXpaJ/xrfkcF7k2nK9rHlDhsvU9VzXnHIzeEXE2w86CWmZ FnEj2zu9pF6gO/lvf46zqSd7Ytvklw1gEgYUkC7KZvr6PlRnn7wrgBo8gsCtZuU9zanN ti5Q== X-Gm-Message-State: AAQBX9c4rK/KDkY0r1tyHfCjtoVQD2U7Q7ra6FARg24bBJ1kdt0QJOYv B8PDyuYq+PZUHdIpiRGzU1zzew== X-Google-Smtp-Source: AKy350b8r2jFMVrBia6qxne7eebOupqk+Y/4dq1+p1jUD2XO6Xp/Gssupf4yzEwsAJP4WCXH7pslYA== X-Received: by 2002:a2e:9cd2:0:b0:29d:76c9:9803 with SMTP id g18-20020a2e9cd2000000b0029d76c99803mr8500974ljj.37.1680248777441; Fri, 31 Mar 2023 00:46:17 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:17 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 06/10] mtd: spi-nor: Set the 4-Byte Address Mode method based on SFDP data Date: Fri, 31 Mar 2023 07:46:02 +0000 Message-Id: <20230331074606.3559258-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" JESD216 SFDP defines in BFPT methods to enter and exit the 4-Byte Address Mode. The flash parameters and settings that are retrieved from SFDP have higher precedence than the static initialized ones, because they should be more accurate and less error prone than those initialized statically. Parse and favor the BFPT-parsed set_4byte_addr_mode methods. Some regressions may be introduced by this patch, because the params->set_4byte_addr_mode method that was set either in spi_nor_init_default_params() or later overwritten in default_init() hooks, are now be overwritten with a different value based on the BFPT data. If that's the case, the fix is to introduce a post_bfpt fixup hook where one should fix the wrong BFPT info. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 7 ++++++- drivers/mtd/spi-nor/macronix.c | 8 +++++++- drivers/mtd/spi-nor/micron-st.c | 8 ++++++-- drivers/mtd/spi-nor/sfdp.c | 11 +++++++++++ drivers/mtd/spi-nor/sfdp.h | 27 +++++++++++++++++++++++++++ drivers/mtd/spi-nor/winbond.c | 22 ++++++++++++++-------- 6 files changed, 71 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 75d28224ec62..50297be98d1b 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2898,6 +2898,8 @@ static void spi_nor_init_fixup_flags(struct spi_nor *= nor) */ static void spi_nor_late_init_params(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; + if (nor->manufacturer && nor->manufacturer->fixups && nor->manufacturer->fixups->late_init) nor->manufacturer->fixups->late_init(nor); @@ -2905,6 +2907,10 @@ static void spi_nor_late_init_params(struct spi_nor = *nor) if (nor->info->fixups && nor->info->fixups->late_init) nor->info->fixups->late_init(nor); =20 + /* Default method kept for backward compatibility. */ + if (!params->set_4byte_addr_mode) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; + spi_nor_init_flags(nor); spi_nor_init_fixup_flags(nor); =20 @@ -2971,7 +2977,6 @@ static void spi_nor_init_default_params(struct spi_no= r *nor) struct device_node *np =3D spi_nor_get_flash_node(nor); =20 params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; - params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; params->otp.org =3D &info->otp_org; =20 /* Default to 16-bit Write Status (01h) Command */ diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 91a8fa7d4512..075a26945f2d 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -105,11 +105,17 @@ static const struct flash_info macronix_nor_parts[] = =3D { static void macronix_nor_default_init(struct spi_nor *nor) { nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; - nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex4= b; +} + +static void macronix_nor_late_init(struct spi_nor *nor) +{ + if (!nor->params->set_4byte_addr_mode) + nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex= 4b; } =20 static const struct spi_nor_fixups macronix_nor_fixups =3D { .default_init =3D macronix_nor_default_init, + .late_init =3D macronix_nor_late_init, }; =20 const struct spi_nor_manufacturer spi_nor_macronix =3D { diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index a75f0f4e1c38..a6f080112a51 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -425,13 +425,17 @@ static void micron_st_nor_default_init(struct spi_nor= *nor) nor->flags |=3D SNOR_F_HAS_LOCK; nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; nor->params->quad_enable =3D NULL; - nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4= b_ex4b; } =20 static void micron_st_nor_late_init(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; + if (nor->info->mfr_flags & USE_FSR) - nor->params->ready =3D micron_st_nor_ready; + params->ready =3D micron_st_nor_ready; + + if (!params->set_4byte_addr_mode) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4b_ex= 4b; } =20 static const struct spi_nor_fixups micron_st_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 298ab5e53a8c..69e47c9778a2 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -438,6 +438,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, size_t len; int i, cmd, err; u32 addr, val; + u32 dword; u16 half; u8 erase_mask; =20 @@ -607,6 +608,16 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; } =20 + dword =3D bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_4B_ADDR_MODE_MASK; + if (SFDP_MASK_CHECK(dword, BFPT_DWORD16_4B_ADDR_MODE_BRWR)) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; + else if (SFDP_MASK_CHECK(dword, BFPT_DWORD16_4B_ADDR_MODE_WREN_EN4B_EX4B)) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4b_ex= 4b; + else if (SFDP_MASK_CHECK(dword, BFPT_DWORD16_4B_ADDR_MODE_EN4B_EX4B)) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex4b; + else + dev_dbg(nor->dev, "BFPT: 4-Byte Address Mode method is not recognized or= not implemented\n"); + /* Soft Reset support. */ if (bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_SWRST_EN_RST) nor->flags |=3D SNOR_F_SOFT_RESET; diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index 500659b35655..6eb99e1cdd61 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -15,6 +15,7 @@ =20 /* SFDP DWORDS are indexed from 1 but C arrays are indexed from 0. */ #define SFDP_DWORD(i) ((i) - 1) +#define SFDP_MASK_CHECK(dword, mask) (((dword) & (mask)) =3D=3D (mask)) =20 /* Basic Flash Parameter Table */ =20 @@ -89,6 +90,32 @@ struct sfdp_bfpt { #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ =20 +#define BFPT_DWORD16_EN4B_MASK GENMASK(31, 24) +#define BFPT_DWORD16_EN4B_ALWAYS_4B BIT(30) +#define BFPT_DWORD16_EN4B_4B_OPCODES BIT(29) +#define BFPT_DWORD16_EN4B_16BIT_NV_CR BIT(28) +#define BFPT_DWORD16_EN4B_BRWR BIT(27) +#define BFPT_DWORD16_EN4B_WREAR BIT(26) +#define BFPT_DWORD16_EN4B_WREN_EN4B BIT(25) +#define BFPT_DWORD16_EN4B_EN4B BIT(24) +#define BFPT_DWORD16_EX4B_MASK GENMASK(18, 14) +#define BFPT_DWORD16_EX4B_16BIT_NV_CR BIT(18) +#define BFPT_DWORD16_EX4B_BRWR BIT(17) +#define BFPT_DWORD16_EX4B_WREAR BIT(16) +#define BFPT_DWORD16_EX4B_WREN_EX4B BIT(15) +#define BFPT_DWORD16_EX4B_EX4B BIT(14) +#define BFPT_DWORD16_4B_ADDR_MODE_MASK \ + (BFPT_DWORD16_EN4B_MASK | BFPT_DWORD16_EX4B_MASK) +#define BFPT_DWORD16_4B_ADDR_MODE_16BIT_NV_CR \ + (BFPT_DWORD16_EN4B_16BIT_NV_CR | BFPT_DWORD16_EX4B_16BIT_NV_CR) +#define BFPT_DWORD16_4B_ADDR_MODE_BRWR \ + (BFPT_DWORD16_EN4B_BRWR | BFPT_DWORD16_EX4B_BRWR) +#define BFPT_DWORD16_4B_ADDR_MODE_WREAR \ + (BFPT_DWORD16_EN4B_WREAR | BFPT_DWORD16_EX4B_WREAR) +#define BFPT_DWORD16_4B_ADDR_MODE_WREN_EN4B_EX4B \ + (BFPT_DWORD16_EN4B_WREN_EN4B | BFPT_DWORD16_EX4B_WREN_EX4B) +#define BFPT_DWORD16_4B_ADDR_MODE_EN4B_EX4B \ + (BFPT_DWORD16_EN4B_EN4B | BFPT_DWORD16_EX4B_EX4B) #define BFPT_DWORD16_SWRST_EN_RST BIT(12) =20 #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 9cea241c204b..834d6ba5ce70 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -216,19 +216,25 @@ static const struct spi_nor_otp_ops winbond_nor_otp_o= ps =3D { .is_locked =3D spi_nor_otp_is_locked_sr2, }; =20 -static void winbond_nor_default_init(struct spi_nor *nor) -{ - nor->params->set_4byte_addr_mode =3D winbond_nor_set_4byte_addr_mode; -} - static void winbond_nor_late_init(struct spi_nor *nor) { - if (nor->params->otp.org->n_regions) - nor->params->otp.ops =3D &winbond_nor_otp_ops; + struct spi_nor_flash_parameter *params =3D nor->params; + + if (params->otp.org->n_regions) + params->otp.ops =3D &winbond_nor_otp_ops; + + /* + * Winbond seems to require that the Extended Address Register to be set + * to zero when exiting the 4-Byte Address Mode, at least for W25Q256FV. + * This requirement is not described in the JESD216 SFDP standard, thus + * it is Winbond specific. Since we do not know if other Winbond flashes + * have the same requirement, play safe and overwrite the method parsed + * from BFPT, if any. + */ + params->set_4byte_addr_mode =3D winbond_nor_set_4byte_addr_mode; } =20 static const struct spi_nor_fixups winbond_nor_fixups =3D { - .default_init =3D winbond_nor_default_init, .late_init =3D winbond_nor_late_init, }; =20 --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F506C6FD18 for ; Fri, 31 Mar 2023 07:47:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231295AbjCaHq7 (ORCPT ); Fri, 31 Mar 2023 03:46:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231147AbjCaHqW (ORCPT ); Fri, 31 Mar 2023 03:46:22 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBA751A97E for ; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id q14so22125553ljm.11 for ; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680248778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/7NTWdMiStTh7vkRgScnjQ7EbMR0iuczOZLyK0JYbPQ=; b=ZzrZyDZBZ1t0pXXxbwNRoDoE5Wox+GfU6DC9vGhIspumjRbyQ3pimGPHzXGWbzejig HgYXv4RV4Yn3HaMO/KrjknoYMNhnnIjQz86P6E5FvpjmobP1U0TZLNgVU6d/G8LsH7qF o6cuwxQ5NcCAvkElGJXIYh06JLKiGjcVEVHP1FbXnbz7VEXEe4yzU3rGXO5zI/3Bp35j zyM7+DhEV8aR+OhpnwkTyCzr3SWsRaAQ15+1EAZB0RvYIlr//XbxrySwzlqhixMtmXa+ tQkc9a+kvzIu+xcSAVHc+KKfPDcXe+B1RzatxceQfGRtlPwBWoW7Kgaj8WlX/xesldVi IyjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680248778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/7NTWdMiStTh7vkRgScnjQ7EbMR0iuczOZLyK0JYbPQ=; b=6kCVIEN7dz9mjQKnW1RX5phKUKYnRIrZYnS6U0aHJVVo+a0+hfQyfoXcKwqNkUyqQc dHbpk7fl+e2c0tLg2ggkWa52ltVn7xS8LwvAVzIQOs/e47E9ohAAkH+McDa9gHcuzrSv JcLDblfh5q6of4wkdG0jAG4cYEhxHnYDrvsWNOmywyhGeYc/wW+lQr0teLLb/kKVaVOv vAp9WcawUwxQn+ItZGz38gPZo7HWs15Pxcg73JsQCJ/ZHhBoDcEtfQInDsqSOB/ccsPO aBg1SmNLhJL6A5knEqL+/1TTnqbByQMu//mp1K4d3G1lRaFF0YxlnddwMRcYxh70HU3Q OoXw== X-Gm-Message-State: AAQBX9d76cCR1LVMBmsiRAGBBKbgN7puMoyDpDxnEZsqqc4GaWMfVjY6 s8A5q4sV/dJOlNrIbKpq2iPwAQ== X-Google-Smtp-Source: AKy350b7Rp9xYw4Le0T0/Q/T8sfqMkHE7nRnYiZQqUEzTRpsyzDyIr9arnAwVh1Txj4yztxzNHgtIA== X-Received: by 2002:a2e:9d4d:0:b0:2a0:202c:93b3 with SMTP id y13-20020a2e9d4d000000b002a0202c93b3mr7078739ljj.49.1680248778304; Fri, 31 Mar 2023 00:46:18 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:17 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 07/10] mtd: spi-nor: Stop exporting spi_nor_restore() Date: Fri, 31 Mar 2023 07:46:03 +0000 Message-Id: <20230331074606.3559258-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some SPI NOR controllers that used this method were moved to drivers/spi/. We don't accept new support for the existing SPI NOR controllers drivers under drivers/mtd/spi-nor/controllers/ and we encourage their owners to move the drivers under drivers/spi/. Make spi_nor_restore() private as we're going to use it just in core.c. Signed-off-by: Tudor Ambarus --- Documentation/driver-api/mtd/spi-nor.rst | 3 --- drivers/mtd/spi-nor/core.c | 3 +-- include/linux/mtd/spi-nor.h | 6 ------ 3 files changed, 1 insertion(+), 11 deletions(-) diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/drive= r-api/mtd/spi-nor.rst index 4a3adca417fd..c22f8c0f7950 100644 --- a/Documentation/driver-api/mtd/spi-nor.rst +++ b/Documentation/driver-api/mtd/spi-nor.rst @@ -63,6 +63,3 @@ The main API is spi_nor_scan(). Before you call the hook,= a driver should initialize the necessary fields for spi_nor{}. Please see drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to spi-fsl-qsp= i.c when you want to write a new driver for a SPI NOR controller. -Another API is spi_nor_restore(), this is used to restore the status of SPI -flash chip such as addressing mode. Call it whenever detach the driver from -device or reboot the system. diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 50297be98d1b..0517a61975e4 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3290,7 +3290,7 @@ static void spi_nor_put_device(struct mtd_info *mtd) module_put(dev->driver->owner); } =20 -void spi_nor_restore(struct spi_nor *nor) +static void spi_nor_restore(struct spi_nor *nor) { int ret; =20 @@ -3310,7 +3310,6 @@ void spi_nor_restore(struct spi_nor *nor) if (nor->flags & SNOR_F_SOFT_RESET) spi_nor_soft_reset(nor); } -EXPORT_SYMBOL_GPL(spi_nor_restore); =20 static const struct flash_info *spi_nor_match_name(struct spi_nor *nor, const char *name) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 82547b4b3708..cdcfe0fd2e7d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -450,10 +450,4 @@ static inline struct device_node *spi_nor_get_flash_no= de(struct spi_nor *nor) int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps); =20 -/** - * spi_nor_restore_addr_mode() - restore the status of SPI NOR - * @nor: the spi_nor structure - */ -void spi_nor_restore(struct spi_nor *nor); - #endif --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5EBCC77B60 for ; Fri, 31 Mar 2023 07:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231265AbjCaHqx (ORCPT ); Fri, 31 Mar 2023 03:46:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231144AbjCaHqW (ORCPT ); Fri, 31 Mar 2023 03:46:22 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ECAD1A97C for ; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id a44so3487208ljr.10 for ; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680248779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Gpe4Snyz/bF2fGxRf14cYZlO6UgYfzmd/ba/DWV9Gk=; b=vPj7iUbeg6atcpAE6Rmc2T3cT1CuQ6hI5sL6TzGToU3udLUOVtkSFe4aAbQEDkauGg UOTaUcX/VA/YEwdi/Uv/0tHEEsz3my21x0o09Y5+MMxSeV3Y/+0nCm1n/za4OHVbejob il5LLGPceI3Dy2br6XN05H6fddm/OfImZXd4W4xidDzWOB6pt1sifY9JJ4uzltVdf7FO J+tUbVDGJkqyn4QRoMRN5GtuzXwaupf1wDIVjF+aIUdMXZHm5vOU8zpcRhXktOAREfan ctpopLklTeOkeiyciCJnb8Oydzxd2Okqvf75PKv8FGJe23RYfOBg6Vte/c5nRfrAkxfu xpDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680248779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Gpe4Snyz/bF2fGxRf14cYZlO6UgYfzmd/ba/DWV9Gk=; b=W0RVcGcvLRuyp4pNQp2q4m2c6mKxyhTYdBZgxE9/IoinU5cuhFib9i5dtvGi1bLCy6 Kl0lYjaND9ZN7TKwDkGzvEPioUBly+W7OgfzmNAC3WdYadoTuzjnhx6126LCwH+AJLYn BuNsXswIsRu3PYrrZIXBhvuMvtOEdLgi70Mtcx2JvhZmJsWb8XptdW0ALmcUYijjqEkh YFu7Sm4f7fShALoaDwg6lhtkQSb4gU+0s//sJ6AsfWbyZDazFifw1LXMaYHrRY+q0AAd ik2iyPRTag7FZR3Uc8fq2D9HFngqu+Cd/PEFMC90IgvMUBtinVsV21x6oRyvD5M84LWr bMtw== X-Gm-Message-State: AAQBX9froOrLExfWGzPqVSvLlOvkiQQ/SmQsEZZU5PnG3WJRS0itb6sO vAOqobl1HChOtMB1xp+YivhMzQ== X-Google-Smtp-Source: AKy350bSzjL91WtFWl1PE43B7dIJUbkMTgBFFknQ0K7k/cM/h+/38F1qZmY/xMT76WPQrlNjZa1lJw== X-Received: by 2002:a2e:984e:0:b0:293:4b60:419c with SMTP id e14-20020a2e984e000000b002934b60419cmr2359613ljj.18.1680248779228; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:18 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus , stable@vger.kernel.org Subject: [PATCH v5 08/10] mtd: spi-nor: core: Update flash's current address mode when changing address mode Date: Fri, 31 Mar 2023 07:46:04 +0000 Message-Id: <20230331074606.3559258-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The bug was obswerved while reading code. There are not many users of addr_mode_nbytes. Anyway, we should update the flash's current address mode when changing the address mode, fix it. We don't care for now about the set_4byte_addr_mode(nor, false) from spi_nor_restore(), as it is used at driver remove and shutdown. Fixes: d7931a215063 ("mtd: spi-nor: core: Track flash's internal address mo= de") Signed-off-by: Tudor Ambarus Cc: stable@vger.kernel.org --- drivers/mtd/spi-nor/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 0517a61975e4..4f0d90d3dad5 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3135,6 +3135,7 @@ static int spi_nor_quad_enable(struct spi_nor *nor) =20 static int spi_nor_init(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; int err; =20 err =3D spi_nor_octal_dtr_enable(nor, true); @@ -3176,9 +3177,10 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - err =3D nor->params->set_4byte_addr_mode(nor, true); + err =3D params->set_4byte_addr_mode(nor, true); if (err && err !=3D -ENOTSUPP) return err; + params->addr_mode_nbytes =3D 4; } =20 return 0; --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4CD3C6FD18 for ; Fri, 31 Mar 2023 07:47:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231176AbjCaHrI (ORCPT ); Fri, 31 Mar 2023 03:47:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230463AbjCaHqY (ORCPT ); Fri, 31 Mar 2023 03:46:24 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91C9F1B350 for ; Fri, 31 Mar 2023 00:46:21 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 20so22177857lju.0 for ; Fri, 31 Mar 2023 00:46:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680248780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PcXZcEx2eHoNQSwUs7M5JpMhYFB2VWPVVcMYUPnoHZs=; b=fAQTJA4yiXJKR22sZnpyJp55Cbmo39ruuDQt/ifHXraID6hjnHAWydLebCsDFGp0RQ XmzY81Cl+sTaKK+5kJXrVHl8Qe3NRiN+edOAkaZQZGOznBNI0GTBdpx8RdojbAN/EABY hIuKD7OuCXnZ3DZjDWzAzEJzc376rWz7r/Z//97JO7vWme7+lV4+5V5/J5LDTOSzWyhL 8SQ7fb1Yp3rqIBNwW0XVvS0HuNQii4wdAZIownfUCmcOABFlZ9g4B5LRQxpi+sq/EzXO 92o25th8GGuW2k8416veMKdg2wFl70PUCf7xv26RLrPyDg4sxWkoiEvoQ2dPAQg3Ogwe 8KFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680248780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PcXZcEx2eHoNQSwUs7M5JpMhYFB2VWPVVcMYUPnoHZs=; b=JyoCvxKiVixl3Umsli6lIlW80ircsgWrtJtN+6Da+71yL9jfv6Isa9Q7BYqgidcLLo ndbL3Tao0Zr1Bs97Q8OQKB9QdHRE5CehNUDxMvHc4VK7vyyrzsH02L8MveqXDhhgLBTx EL3UrHzGngAzYC5iXhco5Zw2Pwuwqc9PYgovj1A2AP9wmG0+v3IOwTxOydb7GO0riw/X iSDgpJO8RbiXrXolI4cf8naW9sFDDcwwQALZYkalSNJw0kCaFBiSYKTsnx+OxPSgk2Gv DVP/4d5Ms9JDjszX7afzjFOVzN+daFPhkIuR4Wpqq/qi3K9rsbUSzsIXLCoGD1bNp7Zi Upxw== X-Gm-Message-State: AAQBX9ewrtdaA0RZ/3zTrBeEM1YS5aNKm9yj8khUkYRDrTqsZd9NhK7J e9j43/pfCaDBQYDoLm6PdOnA8g== X-Google-Smtp-Source: AKy350YcfCQ/0BL7AU0CYA2k/XkYYE7mIAgMrX3aB/4nmGiGkNyK2nacuzwEX+L2RB8CFF+VZ6MPFw== X-Received: by 2002:a2e:87c4:0:b0:2a6:1bd3:4f72 with SMTP id v4-20020a2e87c4000000b002a61bd34f72mr1301996ljj.0.1680248779942; Fri, 31 Mar 2023 00:46:19 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:19 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 09/10] mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode() Date: Fri, 31 Mar 2023 07:46:05 +0000 Message-Id: <20230331074606.3559258-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make the method public, as it will be used as a last resort to enable 4byte address mode when we can't determine the address mode at runtime. Update the addr_nbytes and current address mode while exiting the 4byte address mode too, as it may be used in the future by manufacturer drivers. No functional change. spi_nor_restore didn't update the address mode nbytes, but updating them now doesn't harm as the method is called in the driver's remove and shutdown paths. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 35 ++++++++++++++++++++++++++++++----- drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 4f0d90d3dad5..c67369815fde 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3133,9 +3133,35 @@ static int spi_nor_quad_enable(struct spi_nor *nor) return nor->params->quad_enable(nor); } =20 -static int spi_nor_init(struct spi_nor *nor) +/** + * spi_nor_set_4byte_addr_mode() - Set address mode. + * @nor: pointer to a 'struct spi_nor'. + * @enable: enable/disable 4 byte address mode. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) { struct spi_nor_flash_parameter *params =3D nor->params; + int ret; + + ret =3D params->set_4byte_addr_mode(nor, enable); + if (ret && ret !=3D -ENOTSUPP) + return ret; + + if (enable) { + params->addr_nbytes =3D 4; + params->addr_mode_nbytes =3D 4; + } else { + params->addr_nbytes =3D 3; + params->addr_mode_nbytes =3D 3; + } + + return 0; +} + +static int spi_nor_init(struct spi_nor *nor) +{ int err; =20 err =3D spi_nor_octal_dtr_enable(nor, true); @@ -3177,10 +3203,9 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - err =3D params->set_4byte_addr_mode(nor, true); - if (err && err !=3D -ENOTSUPP) + err =3D spi_nor_set_4byte_addr_mode(nor, true); + if (err) return err; - params->addr_mode_nbytes =3D 4; } =20 return 0; @@ -3299,7 +3324,7 @@ static void spi_nor_restore(struct spi_nor *nor) /* restore the addressing mode */ if (nor->addr_nbytes =3D=3D 4 && !(nor->flags & SNOR_F_4B_OPCODES) && nor->flags & SNOR_F_BROKEN_RESET) { - ret =3D nor->params->set_4byte_addr_mode(nor, false); + ret =3D spi_nor_set_4byte_addr_mode(nor, false); if (ret) /* * Do not stop the execution in the hope that the flash diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 8953ddeb8625..ea9033cb0a01 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -651,6 +651,7 @@ int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_no= r *nor, bool enable); int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable); int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_prep_and_lock(struct spi_nor *nor); --=20 2.40.0.348.gf938b09366-goog From nobody Sun Feb 8 20:17:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50256C76196 for ; Fri, 31 Mar 2023 07:47:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231315AbjCaHrF (ORCPT ); Fri, 31 Mar 2023 03:47:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230231AbjCaHqX (ORCPT ); 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[35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020a2e8794000000b0029573844d03sm241201lji.109.2023.03.31.00.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Mar 2023 00:46:20 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v5 10/10] mtd: spi-nor: spansion: Determine current address mode Date: Fri, 31 Mar 2023 07:46:06 +0000 Message-Id: <20230331074606.3559258-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230331074606.3559258-1-tudor.ambarus@linaro.org> References: <20230331074606.3559258-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Internal address mode (3- or 4-byte) affects to the address length in Read Any Reg op. Read Any Reg op is used in SMPT parse and other setup functions. Current driver assumes that address mode is factory default but users can change it via volatile and non-volatile registers. Current address mode can be checked by CFR2V[7] but Read Any Reg op is needed to read CFR2V (chicken-and-egg). Introduce a way to determine current address mode by comparing status register 1 values read by different address length. Suggested-by: Tudor Ambarus Signed-off-by: Takahiro Kuwano Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano --- drivers/mtd/spi-nor/spansion.c | 131 ++++++++++++++++++++++++++++++++- 1 file changed, 128 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 1678b7b2e9f7..352c40dd3864 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -14,10 +14,12 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ +#define SPINOR_REG_CYPRESS_STR1V 0x00800000 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb +#define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 @@ -188,6 +190,117 @@ static int cypress_nor_quad_enable_volatile(struct sp= i_nor *nor) return 0; } =20 +/** + * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mo= de + * (3 or 4-byte) by querying st= atus + * register 1 (SR1). + * @nor: pointer to a 'struct spi_nor' + * @addr_mode: ponter to a buffer where we return the determined + * address mode. + * + * This function tries to determine current address mode by comparing SR1 = value + * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address). + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor, + u8 *addr_mode) +{ + struct spi_mem_op op =3D + CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0, + nor->bouncebuf); + bool is3byte, is4byte; + int ret; + + ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[1]); + if (ret) + return ret; + + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + is3byte =3D (nor->bouncebuf[0] =3D=3D nor->bouncebuf[1]); + + op =3D (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0, + nor->bouncebuf); + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + is4byte =3D (nor->bouncebuf[0] =3D=3D nor->bouncebuf[1]); + + if (is3byte =3D=3D is4byte) + return -EIO; + if (is3byte) + *addr_mode =3D 3; + else + *addr_mode =3D 4; + + return 0; +} + +/** + * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mo= de of + * current address mode. + * @nor: pointer to a 'struct spi_nor' + * + * Determine current address mode by reading SR1 with different methods, t= hen + * query CFR2V[7] to confirm. If determination is failed, force enter to 4= -byte + * address mode. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor) +{ + struct spi_mem_op op; + u8 addr_mode; + int ret; + + /* + * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable + * that sets bit-1 in SR1. + */ + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D cypress_nor_determine_addr_mode_by_sr1(nor, &addr_mode); + if (ret) { + ret =3D spi_nor_set_4byte_addr_mode(nor, true); + if (ret) + return ret; + return spi_nor_write_disable(nor); + } + ret =3D spi_nor_write_disable(nor); + if (ret) + return ret; + + /* + * Query CFR2V and make sure no contradiction between determined address + * mode and CFR2V[7]. + */ + op =3D (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode, SPINOR_REG_CYPRESS_CFR2V, + 0, nor->bouncebuf); + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { + if (addr_mode !=3D 4) + return spi_nor_set_4byte_addr_mode(nor, true); + } else { + if (addr_mode !=3D 3) + return spi_nor_set_4byte_addr_mode(nor, true); + } + + nor->params->addr_nbytes =3D addr_mode; + nor->params->addr_mode_nbytes =3D addr_mode; + + return 0; +} + /** * cypress_nor_set_page_size() - Set page size which corresponds to the fl= ash * configuration. @@ -227,9 +340,9 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor, struct spi_mem_op op; int ret; =20 - /* 4-byte address mode is enabled by default */ - nor->params->addr_nbytes =3D 4; - nor->params->addr_mode_nbytes =3D 4; + ret =3D cypress_nor_set_addr_mode_nbytes(nor); + if (ret) + return ret; =20 /* Read Architecture Configuration Register (ARCFN) */ op =3D (struct spi_mem_op) @@ -280,6 +393,12 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt) { + int ret; + + ret =3D cypress_nor_set_addr_mode_nbytes(nor); + if (ret) + return ret; + /* Replace Quad Enable with volatile version */ nor->params->quad_enable =3D cypress_nor_quad_enable_volatile; =20 @@ -375,6 +494,12 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt) { + int ret; + + ret =3D cypress_nor_set_addr_mode_nbytes(nor); + if (ret) + return ret; + return cypress_nor_set_page_size(nor); } =20 --=20 2.40.0.348.gf938b09366-goog