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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:15:02 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:53 +0200 Subject: [PATCH v3 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230331-topic-konahana_speedbin-v3-5-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=2769; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HqeX7I3FOTetdcP/eoIjPXuTw8wHKioKrQWO9/sbbPc=; b=wzgrdutbTKX9FfrY9LFUPMhDjNDEo4+SrLkqMv6V5PfX6iNaQWch4PLuJxwHXTHk7g1MsMg5kOBI ityYCqGcCx2USD9ZceGCCesjVdZrImYG7qWWu2UepIAf9GLUYALJ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8250 has (at least) four GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Tested-by: Marijn Suijten # On Sony Xperia = 5 II (speed bin 0x7) Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 7b78761f2041..65e6fcff2d6c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -962,6 +962,18 @@ ipcc: mailbox@408000 { #mbox-cells =3D <2>; }; =20 + qfprom: efuse@784000 { + compatible =3D "qcom,sm8250-qfprom", "qcom,qfprom"; + reg =3D <0 0x00784000 0 0x8ff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gpu_speed_bin: gpu_speed_bin@19b { + reg =3D <0x19b 0x1>; + bits =3D <5 3>; + }; + }; + rng: rng@793000 { compatible =3D "qcom,prng-ee"; reg =3D <0 0x00793000 0 0x1000>; @@ -2559,49 +2571,58 @@ gpu: gpu@3d00000 { =20 qcom,gmu =3D <&gmu>; =20 + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + status =3D "disabled"; =20 zap-shader { memory-region =3D <&gpu_mem>; }; =20 - /* note: downstream checks gpu binning for 670 Mhz */ gpu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-670000000 { opp-hz =3D /bits/ 64 <670000000>; opp-level =3D ; + opp-supported-hw =3D <0xa>; }; =20 opp-587000000 { opp-hz =3D /bits/ 64 <587000000>; opp-level =3D ; + opp-supported-hw =3D <0xb>; }; =20 opp-525000000 { opp-hz =3D /bits/ 64 <525000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-490000000 { opp-hz =3D /bits/ 64 <490000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-441600000 { opp-hz =3D /bits/ 64 <441600000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-400000000 { opp-hz =3D /bits/ 64 <400000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-305000000 { opp-hz =3D /bits/ 64 <305000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; }; }; --=20 2.40.0