From nobody Mon Feb 9 16:47:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 988D6C7619A for ; Fri, 31 Mar 2023 01:15:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229518AbjCaBPG (ORCPT ); Thu, 30 Mar 2023 21:15:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229640AbjCaBPA (ORCPT ); Thu, 30 Mar 2023 21:15:00 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0151EF89 for ; Thu, 30 Mar 2023 18:14:58 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id bx10so3159156ljb.8 for ; Thu, 30 Mar 2023 18:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680225297; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=p4o6oBmHnEhp5oKh/mixd7WOHYgf5ln4PuMXkA7t4Yg=; b=ilIG2XmxB/j7n7ATeF8zJTqz4zU2CrZAhUg7m4fK8Ct9T3JCf+UojRN2STUA6fj/N8 e/MkIBwAqqo6YeNmch6+KcXlbjkcMAUlfRa7Xldldwc8qjrMo5N6relst0oYtxTgE2Jk QTkBQuHpXE/gWpk6a9g+S85Dybzo2/bHMMSUMJIdIGTEzZ7XzGN2Vta/lJAQHImrjJhl JFTY+vhLgHk578tIAu3AAKZnL/UnaAcT770w/MeJW706mdvvAWDujHuW4esZOhIxHUsQ 8xqhryyHkDC92IcC+aQ/sbPw3jEVGQzL4EJ9NK+PHwlmSVNlNqlKVNK3JErawbNLRb8n OS9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680225297; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p4o6oBmHnEhp5oKh/mixd7WOHYgf5ln4PuMXkA7t4Yg=; b=yrYZg/NVv4HlaWbCTIulUT65463yi7RtyvllCOgtaMWJgfU/2WVr4WIql4zJxBCCJy SfbkT23WeBb3bTNveMl7CZMBHnTzWJ1IyiOkZvf86f86z497g7F6o4HY59TZkneUHvE3 Y5Q8u836u92KTOBNSZnBYlYMfKw3CdwelDJ3LH/fYyUSvsi+1Nuwc9SU2ZmUxiGXPsaV tLY8ojHFu3PzukmI4FNbMke8M2FcZnL+F/MwKU1okrqk3lfqDBjjvE/rYb+Viybbvfb4 unkeQ6D8zB0twfGi9ruHJ56s09pW1CAXcR8rhbYZrRC+g8jI2B0MbndQ5ioXnZGygbDN OFyw== X-Gm-Message-State: AAQBX9eKz4gRuAXKl1jYzoYF7zM6HlMzKYEFqtlSASLB9v4TfPVxHwUr tF2aIhUJOe8hr031Ub7cx8eiKg== X-Google-Smtp-Source: AKy350Y8pbW2rnifmrFP6LIvKRu4SZkzHXfmhAHRIISb+6+uRa6c0W7ynL15+xedRsg87Zo3jeaRGA== X-Received: by 2002:a2e:aa1c:0:b0:2a1:9b6a:72b9 with SMTP id bf28-20020a2eaa1c000000b002a19b6a72b9mr2513568ljb.13.1680225297167; Thu, 30 Mar 2023 18:14:57 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:14:56 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:49 +0200 Subject: [PATCH v3 1/5] drm/msm/a6xx: Add support for A640 speed binning MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230331-topic-konahana_speedbin-v3-1-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Akhil P Oommen X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=1296; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=VXMxl1zaALk2VQGZ0SUWZWF+pL7ypf/TNwlzN5n8NSU=; b=kdwkwRFUtJBE2RUvooae/psy8PkBqKZzpIRLEnDz0bWAFsqckUPcG6f+uXQfdlVlK+Uu7jLRej2i 6iCqX4j7AjGitZ8xuD3j/PrE/IF9redU8LaK+IiBz+VU46aV/KQr X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for matching QFPROM fuse values to get the correct speed bin on A640 (SM8150) GPUs. Reviewed-by: Akhil P Oommen Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 1e09777cce3f..663090973c1b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1890,6 +1890,16 @@ static u32 a619_get_speed_bin(u32 fuse) return UINT_MAX; } =20 +static u32 a640_get_speed_bin(u32 fuse) +{ + if (fuse =3D=3D 0) + return 0; + else if (fuse =3D=3D 1) + return 1; + + return UINT_MAX; +} + static u32 adreno_7c3_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -1915,6 +1925,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev)) val =3D adreno_7c3_get_speed_bin(fuse); =20 + if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) + val =3D a640_get_speed_bin(fuse); + if (val =3D=3D UINT_MAX) { DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by h= ardware\n", --=20 2.40.0 From nobody Mon Feb 9 16:47:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72635C6FD1D for ; Fri, 31 Mar 2023 01:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229924AbjCaBPI (ORCPT ); Thu, 30 Mar 2023 21:15:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229760AbjCaBPB (ORCPT ); Thu, 30 Mar 2023 21:15:01 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39DAFCDCF for ; Thu, 30 Mar 2023 18:15:00 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id s20so1179168ljp.7 for ; Thu, 30 Mar 2023 18:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680225298; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=G6mdNQhMjpxcMUaJ/7JOM8PZFmH0MT/DI0sUdW8J0P0=; b=FmDWo+WsUIEzWEh69oAza5U9SDuhi3vg0vzqbUw0sWTdtjcYoB77tqOV1xw/aRJp2h nIA+QrGZrOvn48wti32AyLqxLRSpTNvo9mk+apQCn2aQ5/9H+qVDf1JkML7Zbfv/sHb7 iOGNvJXH1iV3g4CNdnjGiegN3Fmc3fnWp9IiTfqZBZI4sSI2UPRpu7XxHQQ3Z+FVWvOP MNBpfofj7fBU1nX7YjFPl9+PavvifqTcm2A3qAJ+mPt4bI96y+2aa1MvAh1od1in5MXQ nD5g1NlUavkUmwLwKzHUbqg7uzesaUSgdV5QqHw7PN/5T8XRiEagR/3Re5v+8BDRqrS0 u3pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680225298; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G6mdNQhMjpxcMUaJ/7JOM8PZFmH0MT/DI0sUdW8J0P0=; b=Yrru+UnsQtq+cyfqOiCprb53Cvo8QpwHl+JvXkd+xsTUpErTL/4ppVKHxrNQ6wX+LV asB2UAZtSkbHPfdUnoMozAzV8BtPQysDU14JlaD7J5CDfWmzZjNjZFz0mryAjcFHWc1Y dWlfiXZfKXwMNZI3t4mDVCzyQTJBzf0kYXhDp4XVn10Den/641mRrD1bDWpV7u8okq2y 3f+65OAok1kwEDAmkW2Gpgc63/+a9u+iUDJ5xROQq88ibW1tPPBrpEqBnZK0xLXjdbh8 TV5Y/4L0kQ0joUIgHmehFlp7dBHyZgSSArLrszLo0HQ5ZTY8ZBCYhGHhV+T90n3DZ9vz R9xg== X-Gm-Message-State: AAQBX9c/GWpm2uR55vs5s+Wj6mmAeSKhoDbuhorJGZWAlSDU2nvyyPF/ nFsi8TWJXOC/M5jyMwdIx456Og== X-Google-Smtp-Source: AKy350Zb9up3yCkQCc7qcN3sJjC3uSGuYzAqAKbJxUDI1C3urvSdsIL2EvRVpITAQvJpt+zhH8FBcA== X-Received: by 2002:a2e:7c10:0:b0:298:b333:4267 with SMTP id x16-20020a2e7c10000000b00298b3334267mr8693032ljc.18.1680225298531; Thu, 30 Mar 2023 18:14:58 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:14:58 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:50 +0200 Subject: [PATCH v3 2/5] drm/msm/a6xx: Add support for A650 speed binning MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230331-topic-konahana_speedbin-v3-2-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=1412; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=42U2yCRDQAALlywjy8FiLoqbAeo9f7qbW4rrzl+BgmY=; b=dwyPUzW5kyB7cpYIsra0jqgoc9iICEbp333fN21/hW1uI9eAgh9lyZx3qLIhTqeBJe7Uf2/WSJLw 8UXuc7NcD4q+iFYH51Ld8y73WVcYc3NMkKeHz0Kfjv8gbc3apCoK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for matching QFPROM fuse values to get the correct speed bin on A650 (SM8250) GPUs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 663090973c1b..2afc160cf06a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1900,6 +1900,21 @@ static u32 a640_get_speed_bin(u32 fuse) return UINT_MAX; } =20 +static u32 a650_get_speed_bin(u32 fuse) +{ + if (fuse =3D=3D 0) + return 0; + else if (fuse =3D=3D 1) + return 1; + /* Yep, 2 and 3 are swapped! :/ */ + else if (fuse =3D=3D 2) + return 3; + else if (fuse =3D=3D 3) + return 2; + + return UINT_MAX; +} + static u32 adreno_7c3_get_speed_bin(u32 fuse) { if (fuse =3D=3D 0) @@ -1928,6 +1943,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct= adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val =3D a640_get_speed_bin(fuse); =20 + if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + val =3D a650_get_speed_bin(fuse); + if (val =3D=3D UINT_MAX) { DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. 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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:14:59 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:51 +0200 Subject: [PATCH v3 3/5] arm64: dts: qcom: sm8150: Don't start Adreno in headless mode MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230331-topic-konahana_speedbin-v3-3-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=2441; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=0bRNNECqfQgn0pE7kzclN0Aj6mArWM+WKgBFrwJE5/c=; b=rY3AlxaGIds0zRkZc6EUU8QyjZ2q/ehkONWRm0jX7zPOtPLrGM+GM/crsgiPjJVlzNqZTedPu68T dRs/eZDgB18cMnsKLK17usLH/teBLab307MB3WtKpMfneulMWUq4 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that there's display support, there is no reason to assume the default mode for Adreno should be headless. Keep it like that for boards that previously enabled it, so as not to create regressions though. Tested-by: Marijn Suijten # On Sony Xperia 5 Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 5 +++++ arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 5 +++++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +--------- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8150-hdk.dts index 8f014a232526..c0200e7f3f74 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -359,6 +359,11 @@ &gmu { }; =20 &gpu { + /* + * NOTE: "amd,imageon" makes Adreno start in headless mode, remove it + * after display support is added on this board. + */ + compatible =3D "qcom,adreno-640.1", "qcom,adreno", "amd,imageon"; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8150-mtp.dts index eff995a07ab7..34ec84916bdd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -354,6 +354,11 @@ &gmu { }; =20 &gpu { + /* + * NOTE: "amd,imageon" makes Adreno start in headless mode, remove it + * after display support is added on this board. + */ + compatible =3D "qcom,adreno-640.1", "qcom,adreno", "amd,imageon"; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 9491be4a6bf0..880483922f22 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2157,15 +2157,7 @@ compute-cb@3 { }; =20 gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible =3D "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - + compatible =3D "qcom,adreno-640.1", "qcom,adreno"; reg =3D <0 0x02c00000 0 0x40000>; reg-names =3D "kgsl_3d0_reg_memory"; =20 --=20 2.40.0 From nobody Mon Feb 9 16:47:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1473C761AF for ; Fri, 31 Mar 2023 01:15:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229901AbjCaBPO (ORCPT ); Thu, 30 Mar 2023 21:15:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229790AbjCaBPD (ORCPT ); Thu, 30 Mar 2023 21:15:03 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D826D1204C for ; Thu, 30 Mar 2023 18:15:01 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id q14so21475574ljm.11 for ; Thu, 30 Mar 2023 18:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680225301; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LYSzPLydtmK2JKcRhPPJf/WCaXdAIMHqEJnKMvnOMFk=; b=QB9AJhVUigoXflzaqK7rWan9FMupoyp/wjPCEWPrRuOD6jYiWwHo82ekHqx8y7Y4c6 XGMdr2D1+kFtG4J0IJ2gdzEMiwAhFJQus3wIcHXSOsspm+P2L8mTLnaJ3up3yWo1iu2J QTR240DGs6kRd2Gk0jOFqRqS1/A3CBnNJcyYdapa/aFt+/jC3Kk/oUbZH+BXd8maBZKz gF0R61U6wNxSJ+S03+AdTG8HT3oh99Cb1WtFSo3Kmhll/6/udnBPTRVoIZkEV8XNdVMU AzADUEQ9zV3iW4zeySzI4KNJaCD3WmsAD3S9OwPwhwOHa0P7U6jbaVSDOe024omWVN0C hJ0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680225301; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LYSzPLydtmK2JKcRhPPJf/WCaXdAIMHqEJnKMvnOMFk=; b=ZQvsZLKVBaYkqDoF7JvsIlLUNyLsZG8MKC+9bnSPLJQU/PjzZvadp5KVM5hYJ1D9g7 di2b9mh2fyjm2x4MYLyMQPkpEIe4Uy1Gn+8QF9hUIi/ydwGmhbzthKQEehowOzNcCgyr vxVHwp2xK17Jz/p9P2AJf5L0Z9JisDEQQNZLs/RNhUbAL60MZ1BhZaM+7giZqxWzBBIH ilgqqKVbl4CgAcMFtbH4IQ6fLd9uYcrzOF8gFcnsJM8VT/J6uNiT2ousWGilbokk2+RV GR/ba8HsTAbSKJSP5qeZ295zNM7HeP3IIyC6agVXUt19vg/F7qp9VtCZSnL9rmsykGzT 8z5Q== X-Gm-Message-State: AAQBX9fx4b6Zlq5GKDbcDMgUK8kbtnytN9XAtntgh0BpiS+DXLO0z1bo fbaYtIv+sUKF180sGwly2wtJYw== X-Google-Smtp-Source: AKy350bM6SamDQIPnoK5ZV65Xwd526bmZB2kbPdT3rNXJMHLa+/Z0XO3jm3EO29ULFIcPuQvnUET+w== X-Received: by 2002:a2e:888f:0:b0:299:a8e2:2181 with SMTP id k15-20020a2e888f000000b00299a8e22181mr8005791lji.43.1680225301285; Thu, 30 Mar 2023 18:15:01 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:15:00 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:52 +0200 Subject: [PATCH v3 4/5] arm64: dts: qcom: sm8150: Add GPU speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230331-topic-konahana_speedbin-v3-4-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=2592; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=koZEmO1fkF/bnaYkvF93NsF8DQclVperHMMUdURxE4o=; b=j2Z9eJ2Mqm4KOtIUJKp9MRUSZpdT9SbI2GcYYME7XSdmYXJ3KKnNeJZ2tOf0YD3GBAikO/WhSGNM fPPJDeCQD3HadP8gcr+3JLBcWjvTqcN/z0+zY0kYv64lwnnN4BDp X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8150 has (at least) two GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Tested-by: Marijn Suijten # On Sony Xperia = 5 (speed bin 0x3) Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 880483922f22..e4230877555d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -952,6 +952,17 @@ ethernet: ethernet@20000 { status =3D "disabled"; }; =20 + qfprom: efuse@784000 { + compatible =3D "qcom,sm8150-qfprom", "qcom,qfprom"; + reg =3D <0 0x00784000 0 0x8ff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gpu_speed_bin: gpu_speed_bin@133 { + reg =3D <0x133 0x1>; + bits =3D <5 3>; + }; + }; =20 qupv3_id_0: geniqup@8c0000 { compatible =3D "qcom,geni-se-qup"; @@ -2169,44 +2180,52 @@ gpu: gpu@2c00000 { =20 qcom,gmu =3D <&gmu>; =20 + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + status =3D "disabled"; =20 zap-shader { memory-region =3D <&gpu_mem>; }; =20 - /* note: downstream checks gpu binning for 675 Mhz */ gpu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-675000000 { opp-hz =3D /bits/ 64 <675000000>; opp-level =3D ; + opp-supported-hw =3D <0x2>; }; =20 opp-585000000 { opp-hz =3D /bits/ 64 <585000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-499200000 { opp-hz =3D /bits/ 64 <499200000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-427000000 { opp-hz =3D /bits/ 64 <427000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-345000000 { opp-hz =3D /bits/ 64 <345000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; =20 opp-257000000 { opp-hz =3D /bits/ 64 <257000000>; opp-level =3D ; + opp-supported-hw =3D <0x3>; }; }; }; --=20 2.40.0 From nobody Mon Feb 9 16:47:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D015C6FD1D for ; Fri, 31 Mar 2023 01:15:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229995AbjCaBPZ (ORCPT ); Thu, 30 Mar 2023 21:15:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229934AbjCaBPK (ORCPT ); Thu, 30 Mar 2023 21:15:10 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7191511EBD for ; Thu, 30 Mar 2023 18:15:04 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id bx10so3159305ljb.8 for ; Thu, 30 Mar 2023 18:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680225302; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WZJsQk57WCVUIMbRGpk5EuvDlLybqOtHtI+G2nbIFso=; b=D8KSFSBSSGJFqOMXNNOCiuFF6cLNDqJKI3vB+hkEF3HG9Z4wdz5wamtmc/RGHCtK6E cNlqMOkHIkQlkuLr4cRP3HMT6YFhLwaQ4vY7UlTVShKqxvMhjnHmct0UQljIFIA8Jz6x tJidFb0nOjsIFwaiMGtBIFGI7TOPKrwn2mDKUPGphnbmwGsGInaRtFR8LSnmKbPnrSIi mAoKVYncjGXyRZ1S/GkgEPk3QWHDNcLN1+rUwI72h5gFHQYgjJhVcGbkVLhW2pfKHHB8 yUFJcm9xm4Sc4BLoY3XYtb7zFIsVGg4OCRwqgk2zRWJWX38wOkmX09oU3+uHX5rz70/M Jbgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680225302; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WZJsQk57WCVUIMbRGpk5EuvDlLybqOtHtI+G2nbIFso=; b=qHYv9ahWKT6PK6rtRtN/h5mGYwJLobDqvHrwGmIQU7FrfRyWYqcE8UNTkVpvwsjW8c yh/XWr14IHzd9XKA/vxS7T53XmvBlE/opaslQilWS5aX0HdxRzeDGekhJRlmrBhe3ymJ f3Ef9IS6JjOSFByOHIvmm5POaauj2iskyU4icEyN30skHIYl1YiWVEAwGB8xs6Tyy2A2 RvJzOry5JwNHaxmS14RqbOQQjL7wf2Zu8FMrZd+GL0ZyYXdURNy4zxLm2RCa0EIaMmVu apvjhH1YG+LrwpyTFboRoIC5U8Tl4/JLkkNU+nfdLBKPV5YnTkpov8fK4jnMnCWTsi23 Qabg== X-Gm-Message-State: AAQBX9d2CrS2RJIkuDvLhjVjdfSAN6ei8elxWvBwT3+hF1gsep+8kda3 55J2kpD+dpIA5Qw545gltvhkdA== X-Google-Smtp-Source: AKy350bN0vRHkarTfj7p+kxI/vAsesl0IlFFrVaUkbwYyU89Bm/V8kvmoZ7yf2tzzcmzSHxtnwWS/A== X-Received: by 2002:a2e:998f:0:b0:2a6:16b5:2fc1 with SMTP id w15-20020a2e998f000000b002a616b52fc1mr1579576lji.23.1680225302618; Thu, 30 Mar 2023 18:15:02 -0700 (PDT) Received: from [192.168.1.101] (abxj225.neoplus.adsl.tpnet.pl. [83.9.3.225]) by smtp.gmail.com with ESMTPSA id n7-20020a2e7207000000b002986854f27dsm134573ljc.23.2023.03.30.18.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 18:15:02 -0700 (PDT) From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:53 +0200 Subject: [PATCH v3 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230331-topic-konahana_speedbin-v3-5-2dede22dd7f7@linaro.org> References: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> In-Reply-To: <20230331-topic-konahana_speedbin-v3-0-2dede22dd7f7@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680225294; l=2769; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HqeX7I3FOTetdcP/eoIjPXuTw8wHKioKrQWO9/sbbPc=; b=wzgrdutbTKX9FfrY9LFUPMhDjNDEo4+SrLkqMv6V5PfX6iNaQWch4PLuJxwHXTHk7g1MsMg5kOBI ityYCqGcCx2USD9ZceGCCesjVdZrImYG7qWWu2UepIAf9GLUYALJ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SM8250 has (at least) four GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Tested-by: Marijn Suijten # On Sony Xperia = 5 II (speed bin 0x7) Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 7b78761f2041..65e6fcff2d6c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -962,6 +962,18 @@ ipcc: mailbox@408000 { #mbox-cells =3D <2>; }; =20 + qfprom: efuse@784000 { + compatible =3D "qcom,sm8250-qfprom", "qcom,qfprom"; + reg =3D <0 0x00784000 0 0x8ff>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gpu_speed_bin: gpu_speed_bin@19b { + reg =3D <0x19b 0x1>; + bits =3D <5 3>; + }; + }; + rng: rng@793000 { compatible =3D "qcom,prng-ee"; reg =3D <0 0x00793000 0 0x1000>; @@ -2559,49 +2571,58 @@ gpu: gpu@3d00000 { =20 qcom,gmu =3D <&gmu>; =20 + nvmem-cells =3D <&gpu_speed_bin>; + nvmem-cell-names =3D "speed_bin"; + status =3D "disabled"; =20 zap-shader { memory-region =3D <&gpu_mem>; }; =20 - /* note: downstream checks gpu binning for 670 Mhz */ gpu_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-670000000 { opp-hz =3D /bits/ 64 <670000000>; opp-level =3D ; + opp-supported-hw =3D <0xa>; }; =20 opp-587000000 { opp-hz =3D /bits/ 64 <587000000>; opp-level =3D ; + opp-supported-hw =3D <0xb>; }; =20 opp-525000000 { opp-hz =3D /bits/ 64 <525000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-490000000 { opp-hz =3D /bits/ 64 <490000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-441600000 { opp-hz =3D /bits/ 64 <441600000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-400000000 { opp-hz =3D /bits/ 64 <400000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; =20 opp-305000000 { opp-hz =3D /bits/ 64 <305000000>; opp-level =3D ; + opp-supported-hw =3D <0xf>; }; }; }; --=20 2.40.0