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Thu, 30 Mar 2023 10:06:40 -0700 From: Petlozu Pravareshwar To: , , , , , , , , , CC: , Viswanath L Subject: [PATCH v2] soc/tegra: pmc: Support software wake-up for SPE Date: Thu, 30 Mar 2023 17:06:21 +0000 Message-ID: <20230330170621.258068-1-petlozup@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D3:EE_|BL0PR12MB4850:EE_ X-MS-Office365-Filtering-Correlation-Id: a10e8144-aa59-40ad-e6d6-08db31412840 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ohtG1q+rT1HqqOmZWuWjgrih33N6xguGgcq1keXRZA+2dFQmuPFudWKV2Y9r1LIvRPKo4eXyPLGT+mTjZocTx9V4lDzfP/KNKEAe8Lah792ytOtkjEqVTP7txCgaVyiZF5wLqjRNPUj8yr1q2k3XgGRxrzZ1E9TlAApEfmvusF5N4Nq857sqIwdDUPF6tfguK7rNtrZ9huQq/9dfyspXnaRomysS25qFwiAKrJQcqfz1aVJWLgz3Aqx/TRakbNoS7QZZ1Pl9Ireia+RJujsNzJZI6sZZrxoNIm6WQfEX0R4lp+EGhUtsJgpTdeyuvhOwQFpgzikUS296JFaop8QgFrWvADeKGwLy0iyylFY0BL6NU7jHwStAL7z2F7nJel2FCtfyU7oM6gjq3OmlRbgJ5+zd/kCwEOw9JZeDqjlrxUbVfGHiztc3JiPB+hfJOlY+1UbA1qvNd8P+Nl4hen9DZm92Jo8srqtVBUcL1p5bCjAFh9T8jom1a9ko+0t6bUdw37ff6q7iTl5uYalUq1I19nO/jM1FvCCeY1fK9q3gCHtElnwulDASMKD3KyMv173MUg4KJKMlRBkDK12qiFAbJYnSjZDFWjURSEvAFpbfNkJSh7XgNrv4nzIsdWjocrq2bNeNiSgtYEC8Y0GQzW3I1U07CJDyF0B3W2pMDKL6V45ICkImOC/2R222jGlDZt85yQ4rutxiPsyOL/OMbDMdDVT0bF1vQw5g71FbByHBpdQ= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199021)(36840700001)(46966006)(70206006)(70586007)(82310400005)(186003)(4326008)(8676002)(478600001)(54906003)(316002)(110136005)(36860700001)(6666004)(40480700001)(107886003)(1076003)(26005)(36756003)(7696005)(8936002)(5660300002)(47076005)(336012)(86362001)(83380400001)(2906002)(426003)(921005)(356005)(41300700001)(82740400003)(2616005)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2023 17:06:51.8846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a10e8144-aa59-40ad-e6d6-08db31412840 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4850 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Sensor Processing Engine(SPE) can trigger a software wake-up of the device. To support this wake-up for the SPE, set SR_CAPTURE_EN bit in WAKE_AOWAKE_CNTRL register associated with the wake-up for the SPE. This SR capturing logic is expected to be enabled for wakes with short pulse signalling requirements. Signed-off-by: Viswanath L Signed-off-by: Petlozu Pravareshwar --- v1->v2: * Rebase the change on latest code. --- drivers/soc/tegra/pmc.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index cf4cfbf9f7c5..2a2342eff622 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3,7 +3,7 @@ * drivers/soc/tegra/pmc.c * * Copyright (c) 2010 Google, Inc - * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * * Author: * Colin Cross @@ -177,6 +177,7 @@ /* Tegra186 and later */ #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) +#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) @@ -191,6 +192,8 @@ #define WAKE_AOWAKE_CTRL 0x4f4 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) =20 +#define SW_WAKE_ID 83 /* wake83 */ + /* for secure PMC */ #define TEGRA_SMC_PMC 0xc2fffe00 #define TEGRA_SMC_PMC_READ 0xaa @@ -355,6 +358,7 @@ struct tegra_pmc_soc { void (*setup_irq_polarity)(struct tegra_pmc *pmc, struct device_node *np, bool invert); + void (*set_wake_filters)(struct tegra_pmc *pmc); int (*irq_set_wake)(struct irq_data *data, unsigned int on); int (*irq_set_type)(struct irq_data *data, unsigned int type); int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, @@ -2416,6 +2420,17 @@ static int tegra210_pmc_irq_set_type(struct irq_data= *data, unsigned int type) return 0; } =20 +static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) +{ + u32 value; + + /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ + value =3D readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); + value |=3D WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; + writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); + dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 =3D 0x%x\n", value); +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int o= n) { struct tegra_pmc *pmc =3D irq_data_get_irq_chip_data(data); @@ -3042,6 +3057,10 @@ static int tegra_pmc_probe(struct platform_device *p= dev) platform_set_drvdata(pdev, pmc); tegra_pm_init_suspend(); =20 + /* Some wakes require specific filter configuration */ + if (pmc->soc->set_wake_filters) + pmc->soc->set_wake_filters(pmc); + return 0; =20 cleanup_powergates: @@ -3938,6 +3957,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = =3D { .regs =3D &tegra186_pmc_regs, .init =3D tegra186_pmc_init, .setup_irq_polarity =3D tegra186_pmc_setup_irq_polarity, + .set_wake_filters =3D tegra186_pmc_set_wake_filters, .irq_set_wake =3D tegra186_pmc_irq_set_wake, .irq_set_type =3D tegra186_pmc_irq_set_type, .reset_sources =3D tegra186_reset_sources, @@ -4122,6 +4142,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = =3D { .regs =3D &tegra194_pmc_regs, .init =3D tegra186_pmc_init, .setup_irq_polarity =3D tegra186_pmc_setup_irq_polarity, + .set_wake_filters =3D tegra186_pmc_set_wake_filters, .irq_set_wake =3D tegra186_pmc_irq_set_wake, .irq_set_type =3D tegra186_pmc_irq_set_type, .reset_sources =3D tegra194_reset_sources, @@ -4247,6 +4268,7 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = =3D { .regs =3D &tegra234_pmc_regs, .init =3D tegra186_pmc_init, .setup_irq_polarity =3D tegra186_pmc_setup_irq_polarity, + .set_wake_filters =3D tegra186_pmc_set_wake_filters, .irq_set_wake =3D tegra186_pmc_irq_set_wake, .irq_set_type =3D tegra186_pmc_irq_set_type, .reset_sources =3D tegra234_reset_sources, --=20 2.17.1