From nobody Tue Feb 10 05:17:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D0ABC77B6D for ; Thu, 30 Mar 2023 14:15:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232197AbjC3OPz (ORCPT ); Thu, 30 Mar 2023 10:15:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232006AbjC3OPx (ORCPT ); Thu, 30 Mar 2023 10:15:53 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA7758A5A; Thu, 30 Mar 2023 07:15:51 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32UEFaCZ021541; Thu, 30 Mar 2023 09:15:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680185737; bh=aVGHt1tNgSRDuypNWJ2WFD4INriqP7ZqOIDcBGhcX9Y=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=s/fxS7tROtiOzDEDfkCMrrDm1TBKHXtTZ4uFHCvkscvm+8zijIY6dPTmdp5Dv83mx PqmGJMJCAGNk+weE2WYDpE8rrsv6ptT7weMcLen4i0wxar8InibmA0AzNewCV2PLRI f0UDcvZzRTL3QxUahQH6rnRSltE9RiU9cTuICqEY= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32UEFaFU022900 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 30 Mar 2023 09:15:36 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 30 Mar 2023 09:15:36 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 30 Mar 2023 09:15:36 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32UEFaM0087889; Thu, 30 Mar 2023 09:15:36 -0500 From: Hari Nagalla To: , CC: , , , , , Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j784s4-main: Add C71x DSP nodes Date: Thu, 30 Mar 2023 09:15:36 -0500 Message-ID: <20230330141536.22480-3-hnagalla@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230330141536.22480-1-hnagalla@ti.com> References: <20230330141536.22480-1-hnagalla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage domain. The functionality of these DSP subsystems is similar to the C71x DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem has a CMMU but is not currently used. The inter-processor communication between the main A72 cores and the C71x DSPs is achieved through shared memory and mailboxes. Add the DT nodes for these DSP processor sub-systems. Signed-off-by: Hari Nagalla --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 3c785cef4f20..7277bf6eda09 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1232,4 +1232,52 @@ ti,loczrama =3D <1>; }; }; + + c71_0: dsp@64800000 { + compatible =3D "ti,j721s2-c71-dsp"; + reg =3D <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names =3D "l2sram", "l1dram"; + ti,sci =3D <&sms>; + ti,sci-dev-id =3D <30>; + ti,sci-proc-ids =3D <0x30 0xff>; + resets =3D <&k3_reset 30 1>; + firmware-name =3D "j784s4-c71_0-fw"; + }; + + c71_1: dsp@65800000 { + compatible =3D "ti,j721s2-c71-dsp"; + reg =3D <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names =3D "l2sram", "l1dram"; + ti,sci =3D <&sms>; + ti,sci-dev-id =3D <33>; + ti,sci-proc-ids =3D <0x31 0xff>; + resets =3D <&k3_reset 33 1>; + firmware-name =3D "j784s4-c71_1-fw"; + }; + + c71_2: dsp@66800000 { + compatible =3D "ti,j721s2-c71-dsp"; + reg =3D <0x00 0x66800000 0x00 0x00080000>, + <0x00 0x66e00000 0x00 0x0000c000>; + reg-names =3D "l2sram", "l1dram"; + ti,sci =3D <&sms>; + ti,sci-dev-id =3D <37>; + ti,sci-proc-ids =3D <0x32 0xff>; + resets =3D <&k3_reset 37 1>; + firmware-name =3D "j784s4-c71_2-fw"; + }; + + c71_3: dsp@67800000 { + compatible =3D "ti,j721s2-c71-dsp"; + reg =3D <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names =3D "l2sram", "l1dram"; + ti,sci =3D <&sms>; + ti,sci-dev-id =3D <40>; + ti,sci-proc-ids =3D <0x33 0xff>; + resets =3D <&k3_reset 40 1>; + firmware-name =3D "j784s4-c71_3-fw"; + }; }; --=20 2.17.1