From nobody Mon Feb 9 09:08:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1D90C761AF for ; Wed, 29 Mar 2023 15:40:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230422AbjC2PkS (ORCPT ); Wed, 29 Mar 2023 11:40:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231159AbjC2Pj5 (ORCPT ); Wed, 29 Mar 2023 11:39:57 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B99C344A2; Wed, 29 Mar 2023 08:39:52 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C699C2F4; Wed, 29 Mar 2023 08:40:36 -0700 (PDT) Received: from e120937-lin.. (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDE033F663; Wed, 29 Mar 2023 08:39:50 -0700 (PDT) From: Cristian Marussi To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: sudeep.holla@arm.com, cristian.marussi@arm.com, vincent.guittot@linaro.org, souvik.chakravarty@arm.com, nicola.mazzucato@arm.com, Tushar.Khandelwal@arm.com, viresh.kumar@linaro.org, jassisinghbrar@gmail.com, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: mailbox : arm,mhuv2: Allow for more RX interrupts Date: Wed, 29 Mar 2023 16:39:35 +0100 Message-Id: <20230329153936.394911-2-cristian.marussi@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230329153936.394911-1-cristian.marussi@arm.com> References: <20230329153936.394911-1-cristian.marussi@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ARM MHUv2 Receiver block can indeed support more interrupts, up to the maximum number of available channels, but anyway no more than the maximum number of supported interrupt for an AMBA device. Signed-off-by: Cristian Marussi --- Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: devicetree@vger.kernel.org .../devicetree/bindings/mailbox/arm,mhuv2.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml b/Doc= umentation/devicetree/bindings/mailbox/arm,mhuv2.yaml index a4f1fe63659a..5a57f4e2a623 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml @@ -69,10 +69,15 @@ properties: =20 interrupts: description: | - The MHUv2 controller always implements an interrupt in the "receiver" - mode, while the interrupt in the "sender" mode was not available in = the - version MHUv2.0, but the later versions do have it. - maxItems: 1 + The MHUv2 controller always implements at least an interrupt in the + "receiver" mode, while the interrupt in the "sender" mode was not + available in the version MHUv2.0, but the later versions do have it. + In "receiver" mode, beside a single combined interrupt, there could = be + multiple interrupts, up to the number of implemented channels but an= yway + no more than the maximum number of interrupts potentially supported = by + AMBA. + minItems: 1 + maxItems: 9 =20 clocks: maxItems: 1 --=20 2.34.1 From nobody Mon Feb 9 09:08:39 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E843EC6FD18 for ; Wed, 29 Mar 2023 15:40:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230508AbjC2PkO (ORCPT ); Wed, 29 Mar 2023 11:40:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231184AbjC2Pj7 (ORCPT ); Wed, 29 Mar 2023 11:39:59 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 62286135 for ; Wed, 29 Mar 2023 08:39:54 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7023E1570; Wed, 29 Mar 2023 08:40:38 -0700 (PDT) Received: from e120937-lin.. (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC0D03F663; Wed, 29 Mar 2023 08:39:52 -0700 (PDT) From: Cristian Marussi To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: sudeep.holla@arm.com, cristian.marussi@arm.com, vincent.guittot@linaro.org, souvik.chakravarty@arm.com, nicola.mazzucato@arm.com, Tushar.Khandelwal@arm.com, viresh.kumar@linaro.org, jassisinghbrar@gmail.com Subject: [PATCH 2/2] mailbox: arm_mhuv2: Add support for multiple rx interrupt Date: Wed, 29 Mar 2023 16:39:36 +0100 Message-Id: <20230329153936.394911-3-cristian.marussi@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230329153936.394911-1-cristian.marussi@arm.com> References: <20230329153936.394911-1-cristian.marussi@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ARM MHUv2 can be configured to receive multiple interrupt related to the receiver block, up to the maximum number of available channels, and not necessarily grouped into a single combined interrupt. Allow to register more interrupt for the RX block up to the maximum number of interrupts supported by an AMBA device. Signed-off-by: Cristian Marussi --- drivers/mailbox/arm_mhuv2.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c index c6d4957c4da8..89060bee1fb0 100644 --- a/drivers/mailbox/arm_mhuv2.c +++ b/drivers/mailbox/arm_mhuv2.c @@ -163,7 +163,6 @@ enum mhuv2_frame { * @send: Base address of the register mapping region. * @recv: Base address of the register mapping region. * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME. - * @irq: Interrupt. * @windows: Channel windows implemented by the platform. * @minor: Minor version of the controller. * @length: Length of the protocols array in bytes. @@ -178,7 +177,6 @@ struct mhuv2 { struct mhu2_recv_frame_reg __iomem *recv; }; enum mhuv2_frame frame; - unsigned int irq; unsigned int windows; unsigned int minor; unsigned int length; @@ -991,7 +989,6 @@ static int mhuv2_tx_init(struct amba_device *adev, stru= ct mhuv2 *mhu, } else { mhu->mbox.txdone_irq =3D true; mhu->mbox.txdone_poll =3D false; - mhu->irq =3D adev->irq[0]; =20 writel_relaxed_bitfield(1, &mhu->send->int_en, struct int_en_t, chcomb); =20 @@ -1029,18 +1026,23 @@ static int mhuv2_rx_init(struct amba_device *adev, = struct mhuv2 *mhu, mhu->windows =3D readl_relaxed_bitfield(&mhu->recv->mhu_cfg, struct mhu_c= fg_t, num_ch); mhu->minor =3D readl_relaxed_bitfield(&mhu->recv->aidr, struct aidr_t, ar= ch_minor_rev); =20 - mhu->irq =3D adev->irq[0]; - if (!mhu->irq) { - dev_err(dev, "Missing receiver IRQ\n"); - return -EINVAL; - } + for (i =3D 0; i < min_t(unsigned int, mhu->windows, AMBA_NR_IRQS); i++) { + if (!adev->irq[i]) { + /* At least one receiver IRQ is needed */ + if (i =3D=3D 0) { + dev_err(dev, "Missing receiver IRQ\n"); + return -EINVAL; + } + continue; + } =20 - ret =3D devm_request_threaded_irq(dev, mhu->irq, NULL, - mhuv2_receiver_interrupt, IRQF_ONESHOT, - "mhuv2-rx", mhu); - if (ret) { - dev_err(dev, "Failed to request rx IRQ\n"); - return ret; + ret =3D devm_request_threaded_irq(dev, adev->irq[i], NULL, + mhuv2_receiver_interrupt, IRQF_ONESHOT, + "mhuv2-rx", mhu); + if (ret) { + dev_err(dev, "Failed to request rx IRQ\n"); + return ret; + } } =20 /* Mask all the channel windows */ --=20 2.34.1