From nobody Fri May 3 20:14:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F3BC77B60 for ; Tue, 28 Mar 2023 11:22:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232440AbjC1LWh (ORCPT ); Tue, 28 Mar 2023 07:22:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231126AbjC1LWf (ORCPT ); Tue, 28 Mar 2023 07:22:35 -0400 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7690110FA; Tue, 28 Mar 2023 04:22:23 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.35]) by gateway (Coremail) with SMTP id _____8DxE0zuzSJkOA8TAA--.29399S3; Tue, 28 Mar 2023 19:22:22 +0800 (CST) Received: from user-pc.202.106.0.20 (unknown [10.20.42.35]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxOL3kzSJkalgPAA--.9160S3; Tue, 28 Mar 2023 19:22:20 +0800 (CST) From: Yinbo Zhu To: Mark Brown , Rob Herring , Krzysztof Kozlowski , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jianmin Lv , wanghongliang@loongson.cn, Liu Peibao , loongson-kernel@lists.loongnix.cn, Yinbo Zhu Subject: [PATCH v4 1/2] dt-bindings: spi: add loongson spi Date: Tue, 28 Mar 2023 19:22:09 +0800 Message-Id: <20230328112210.23089-2-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230328112210.23089-1-zhuyinbo@loongson.cn> References: <20230328112210.23089-1-zhuyinbo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8CxOL3kzSJkalgPAA--.9160S3 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoW7Cr43Aw47ur17Zry7CFWUtwb_yoW8uFW8pF nrCrs7GFWIqF17Aws3Ka48Cw4rZr95C3ZrWFW2yw1jkas8K3Z8Za13Kr1UZanrAF18XFW7 ZF92kr4UK3WUXF7anT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bVAFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64 kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28E F7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxdM2kKe7AKxVWUXVWUAwAS0I0E0xvYzxvE 52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc02F40EFcxC0VAKzVAqx4xG6I 80ewAv7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCj c4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7VAKI48JMxAIw28IcVCjz48v1s IEY20_WwCFx2IqxVCFs4IE7xkEbVWUJVW8JwCFI7km07C267AKxVWUXVWUAwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GF ylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r 4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07jY zuAUUUUU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the Loongson platform spi binding with DT schema format using json-schema. Signed-off-by: Yinbo Zhu --- .../bindings/spi/loongson,ls-spi.yaml | 43 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/loongson,ls-spi.y= aml diff --git a/Documentation/devicetree/bindings/spi/loongson,ls-spi.yaml b/D= ocumentation/devicetree/bindings/spi/loongson,ls-spi.yaml new file mode 100644 index 000000000000..ee80049b1258 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/loongson,ls-spi.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/loongson,ls-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson SPI controller + +maintainers: + - Yinbo Zhu + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - loongson,ls2k-spi + - loongson,ls7a-spi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + spi0: spi@1fff0220{ + compatible =3D "loongson,ls2k-spi"; + reg =3D <0x1fff0220 0x10>; + clocks =3D <&clk LOONGSON2_BOOT_CLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 25a0981c74b6..9bc2158c735d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12157,6 +12157,12 @@ S: Maintained F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml F: include/dt-bindings/clock/loongson,ls2k-clk.h =20 +LOONGSON SPI DRIVER +M: Yinbo Zhu +L: linux-spi@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/spi/loongson,ls-spi.yaml + LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash M: Sreekanth Reddy --=20 2.20.1 From nobody Fri May 3 20:14:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45F58C76196 for ; Tue, 28 Mar 2023 11:22:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232563AbjC1LWn (ORCPT ); Tue, 28 Mar 2023 07:22:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230526AbjC1LWi (ORCPT ); Tue, 28 Mar 2023 07:22:38 -0400 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8A6217AB4; Tue, 28 Mar 2023 04:22:24 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.35]) by gateway (Coremail) with SMTP id _____8Ax69nvzSJkPg8TAA--.29002S3; Tue, 28 Mar 2023 19:22:23 +0800 (CST) Received: from user-pc.202.106.0.20 (unknown [10.20.42.35]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxOL3kzSJkalgPAA--.9160S4; Tue, 28 Mar 2023 19:22:22 +0800 (CST) From: Yinbo Zhu To: Mark Brown , Rob Herring , Krzysztof Kozlowski , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jianmin Lv , wanghongliang@loongson.cn, Liu Peibao , loongson-kernel@lists.loongnix.cn, Yinbo Zhu Subject: [PATCH v4 2/2] spi: loongson: add bus driver for the loongson spi controller Date: Tue, 28 Mar 2023 19:22:10 +0800 Message-Id: <20230328112210.23089-3-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20230328112210.23089-1-zhuyinbo@loongson.cn> References: <20230328112210.23089-1-zhuyinbo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8CxOL3kzSJkalgPAA--.9160S4 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvAXoW3Zry3tF4DJF4kCr48XF4fZrb_yoW8CFWruo WxZ3Z5Xr48ur18GF1jqr1FqFy7Xa45WrZ0yrs3A3WkJay5tFyDJr9xJrW7CF18Z3W3JFy3 AFySgFW8KF4IgrWkn29KB7ZKAUJUUUUr529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnRJU UU9j1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jrv_JF1l8cAvFV AK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2 z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr 1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWln4kS14v26r1Y6r17M2AIxVAIcxkE cVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F4 0Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC 6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l42xK82IY6x8Erc xFaVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbckI1I0E14v26r1Y6r17MI8I3I0E 5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtV W8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r4j6ryUMIIF0xvE2Ix0cI8IcVCY 1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI 0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7I U8QzVUUUUUU== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This bus driver supports the Loongson spi hardware controller in the Loongson platforms and supports to use DTS and PCI framework to register spi device resources. Signed-off-by: Yinbo Zhu --- MAINTAINERS | 4 + drivers/spi/Kconfig | 31 ++++ drivers/spi/Makefile | 3 + drivers/spi/spi-loongson-core.c | 304 ++++++++++++++++++++++++++++++++ drivers/spi/spi-loongson-pci.c | 89 ++++++++++ drivers/spi/spi-loongson-plat.c | 66 +++++++ drivers/spi/spi-loongson.h | 41 +++++ 7 files changed, 538 insertions(+) create mode 100644 drivers/spi/spi-loongson-core.c create mode 100644 drivers/spi/spi-loongson-pci.c create mode 100644 drivers/spi/spi-loongson-plat.c create mode 100644 drivers/spi/spi-loongson.h diff --git a/MAINTAINERS b/MAINTAINERS index 9bc2158c735d..f2b1ad2c785a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12162,6 +12162,10 @@ M: Yinbo Zhu L: linux-spi@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/spi/loongson,ls-spi.yaml +F: drivers/spi/spi-loongson-core.c +F: drivers/spi/spi-loongson-pci.c +F: drivers/spi/spi-loongson-plat.c +F: drivers/spi/spi-loongson.h =20 LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index cbf60b6a931c..87f87ee35d27 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -509,6 +509,37 @@ config SPI_LM70_LLP which interfaces to an LM70 temperature sensor using a parallel port. =20 +config SPI_LOONGSON_CORE + tristate "Loongson SPI Controller Core Driver Support" + depends on LOONGARCH || COMPILE_TEST + help + This core driver supports the Loongson spi hardware controller in + the Loongson platforms. + Say Y or M here if you want to use the SPI controller on + Loongson platform. + +config SPI_LOONGSON_PCI + tristate "Loongson SPI Controller PCI Driver Support" + select SPI_LOONGSON_CORE + depends on PCI && (LOONGARCH || COMPILE_TEST) + help + This bus driver supports the Loongson spi hardware controller in + the Loongson platforms and supports to use PCI framework to + register spi device resources. + Say Y or M here if you want to use the SPI controller on + Loongson platform. + +config SPI_LOONGSON_PLATFORM + tristate "Loongson SPI Controller Platform Driver Support" + select SPI_LOONGSON_CORE + depends on OF && (LOONGARCH || COMPILE_TEST) + help + This bus driver supports the Loongson spi hardware controller in + the Loongson platforms and supports to use DTS framework to + register spi device resources. + Say Y or M here if you want to use the SPI controller on + Loongson platform. + config SPI_LP8841_RTC tristate "ICP DAS LP-8841 SPI Controller for RTC" depends on MACH_PXA27X_DT || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d87cf75bee6a..a4931aa64476 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -70,6 +70,9 @@ obj-$(CONFIG_SPI_INTEL_PLATFORM) +=3D spi-intel-platform.o obj-$(CONFIG_SPI_LANTIQ_SSC) +=3D spi-lantiq-ssc.o obj-$(CONFIG_SPI_JCORE) +=3D spi-jcore.o obj-$(CONFIG_SPI_LM70_LLP) +=3D spi-lm70llp.o +obj-$(CONFIG_SPI_LOONGSON_CORE) +=3D spi-loongson-core.o +obj-$(CONFIG_SPI_LOONGSON_PCI) +=3D spi-loongson-pci.o +obj-$(CONFIG_SPI_LOONGSON_PLATFORM) +=3D spi-loongson-plat.o obj-$(CONFIG_SPI_LP8841_RTC) +=3D spi-lp8841-rtc.o obj-$(CONFIG_SPI_MESON_SPICC) +=3D spi-meson-spicc.o obj-$(CONFIG_SPI_MESON_SPIFC) +=3D spi-meson-spifc.o diff --git a/drivers/spi/spi-loongson-core.c b/drivers/spi/spi-loongson-cor= e.c new file mode 100644 index 000000000000..2e52e8048e3f --- /dev/null +++ b/drivers/spi/spi-loongson-core.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Loongson SPI Support +// Copyright (C) 2023 Loongson Technology Corporation Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spi-loongson.h" + +static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsign= ed char reg, + unsigned char data) +{ + writeb(data, spi->base + reg); +} + +static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigne= d char reg) +{ + return readb(spi->base + reg); +} + +static void loongson_spi_set_cs(struct spi_device *spi, bool val) +{ + int cs; + struct loongson_spi *loongson_spi =3D spi_master_get_devdata(spi->master); + + if (loongson_spi->mode & SPI_NO_CS) + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_SFCS_REG, 0); + else { + cs =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_SFCS_REG) + & ~(0x11 << spi->chip_select); + loongson_spi_write_reg(loongson_spi, + LOONGSON_SPI_SFCS_REG, + (val ? (0x11 << spi->chip_select) : + (0x1 << spi->chip_select)) | cs); + } +} + +static int loongson_spi_update_state(struct loongson_spi *loongson_spi, + struct spi_device *spi, struct spi_transfer *t) +{ + unsigned int hz; + unsigned int div, div_tmp; + unsigned int bit; + unsigned char val; + const char rdiv[12] =3D {0, 1, 4, 2, 3, 5, 6, 7, 8, 9, 10, 11}; + + if (t) + hz =3D t->speed_hz; + + if ((hz && loongson_spi->hz !=3D hz) || + ((spi->mode ^ loongson_spi->mode) & (SPI_CPOL | SPI_CPHA))) { + div =3D DIV_ROUND_UP_ULL(loongson_spi->clk_rate, hz); + if (div < 2) + div =3D 2; + if (div > 4096) + div =3D 4096; + + bit =3D fls(div) - 1; + if ((1<dev, "clk_rate =3D %llu hz =3D %d div_tmp =3D %d bit =3D %= d\n", + loongson_spi->clk_rate, hz, div_tmp, bit); + + loongson_spi->hz =3D hz; + loongson_spi->spcr =3D div_tmp & 3; + loongson_spi->sper =3D (div_tmp >> 2) & 3; + val =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_SPCR_REG); + val &=3D ~0xc; + if (spi->mode & SPI_CPOL) + val |=3D 8; + if (spi->mode & SPI_CPHA) + val |=3D 4; + + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_SPCR_REG, (val & ~3) | + loongson_spi->spcr); + val =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_SPER_REG); + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_SPER_REG, (val & ~3) | + loongson_spi->sper); + loongson_spi->mode &=3D SPI_NO_CS; + loongson_spi->mode |=3D spi->mode; + } + + return 0; +} + +static int loongson_spi_setup(struct spi_device *spi) +{ + struct loongson_spi *loongson_spi; + + loongson_spi =3D spi_master_get_devdata(spi->master); + if (spi->bits_per_word % 8) + return -EINVAL; + + if (spi->chip_select >=3D spi->master->num_chipselect) + return -EINVAL; + + loongson_spi->hz =3D 0; + loongson_spi->mode &=3D SPI_NO_CS; + loongson_spi_set_cs(spi, 1); + + return 0; +} + +static int loongson_spi_write_read_8bit(struct spi_device *spi, const u8 *= *tx_buf, + u8 **rx_buf, unsigned int num) +{ + struct loongson_spi *loongson_spi =3D spi_master_get_devdata(spi->master); + unsigned long timeout =3D jiffies + SPI_COMPLETION_TIMEOUT; + + if (tx_buf && *tx_buf) { + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_FIFO_REG, *((*tx_buf)+= +)); + while ((loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_SPSR_REG) & 0x1= ) =3D=3D 1 && + time_after(timeout, jiffies)) + cpu_relax(); + } else { + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_FIFO_REG, 0); + while ((loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_SPSR_REG) & 0x1= ) =3D=3D 1 && + time_after(timeout, jiffies)) + cpu_relax(); + } + + if (rx_buf && *rx_buf) + *(*rx_buf)++ =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_FIFO_R= EG); + else + loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_FIFO_REG); + + return 0; +} + +static unsigned int loongson_spi_write_read(struct spi_device *spi, struct= spi_transfer *xfer) +{ + unsigned int count; + const u8 *tx =3D xfer->tx_buf; + u8 *rx =3D xfer->rx_buf; + + count =3D xfer->len; + + do { + if (loongson_spi_write_read_8bit(spi, &tx, &rx, count) < 0) + goto out; + count--; + } while (count); + +out: + return xfer->len - count; +} + +static int loongson_spi_prepare_message(struct spi_controller *ctlr, struc= t spi_message *m) +{ + struct loongson_spi *loongson_spi =3D spi_controller_get_devdata(ctlr); + + loongson_spi->para =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_P= ARA_REG); + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_PARA_REG, loongson_spi-= >para & ~1); + + return 0; +} + +static int loongson_spi_transfer_one(struct spi_controller *ctrl, struct s= pi_device *spi, + struct spi_transfer *xfer) +{ + struct loongson_spi *loongson_spi =3D spi_master_get_devdata(spi->master); + + loongson_spi_update_state(loongson_spi, spi, xfer); + if (xfer->len) + xfer->len =3D loongson_spi_write_read(spi, xfer); + + return 0; +} + +static int loongson_spi_unprepare_message(struct spi_controller *ctrl, str= uct spi_message *m) +{ + struct loongson_spi *loongson_spi =3D spi_controller_get_devdata(ctrl); + + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_PARA_REG, loongson_spi-= >para); + + return 0; +} + +static void loongson_spi_reginit(struct loongson_spi *loongson_spi_dev) +{ + unsigned char val; + + val =3D loongson_spi_read_reg(loongson_spi_dev, LOONGSON_SPI_SPCR_REG); + val &=3D ~LOONGSON_SPI_SPCR_SPE; + loongson_spi_write_reg(loongson_spi_dev, LOONGSON_SPI_SPCR_REG, val); + + loongson_spi_write_reg(loongson_spi_dev, LOONGSON_SPI_SPSR_REG, + (LOONGSON_SPI_SPSR_SPIF | LOONGSON_SPI_SPSR_WCOL)); + + val =3D loongson_spi_read_reg(loongson_spi_dev, LOONGSON_SPI_SPCR_REG); + val |=3D LOONGSON_SPI_SPCR_SPE; + loongson_spi_write_reg(loongson_spi_dev, LOONGSON_SPI_SPCR_REG, val); +} + +int loongson_spi_init_master(struct device *dev, struct resource *res) +{ + struct spi_master *master; + struct loongson_spi *spi; + struct clk *clk; + int ret; + + master =3D spi_alloc_master(dev, sizeof(struct loongson_spi)); + if (master =3D=3D NULL) { + dev_dbg(dev, "master allocation failed\n"); + return -ENOMEM; + } + + master->mode_bits =3D SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + master->setup =3D loongson_spi_setup; + master->prepare_message =3D loongson_spi_prepare_message; + master->transfer_one =3D loongson_spi_transfer_one; + master->unprepare_message =3D loongson_spi_unprepare_message; + master->set_cs =3D loongson_spi_set_cs; + master->num_chipselect =3D 4; + master->dev.of_node =3D of_node_get(dev->of_node); + dev_set_drvdata(dev, master); + + spi =3D spi_master_get_devdata(master); + + spi->master =3D master; + + spi->base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (spi->base =3D=3D NULL) { + dev_err(dev, "cannot map io\n"); + ret =3D -ENXIO; + goto free_master; + } + + clk =3D devm_clk_get(dev, NULL); + if (!IS_ERR(clk)) + spi->clk_rate =3D clk_get_rate(clk); + + loongson_spi_reginit(spi); + + spi->mode =3D 0; + if (of_get_property(dev->of_node, "spi-nocs", NULL)) + spi->mode |=3D SPI_NO_CS; + + ret =3D spi_register_master(master); + if (ret < 0) + goto free_master; + + return ret; + +free_master: + kfree(master); + spi_master_put(master); + + return ret; +} +EXPORT_SYMBOL_GPL(loongson_spi_init_master); + +static int __maybe_unused loongson_spi_suspend(struct device *dev) +{ + struct loongson_spi *loongson_spi; + struct spi_master *master; + + master =3D dev_get_drvdata(dev); + loongson_spi =3D spi_master_get_devdata(master); + + loongson_spi->spcr =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_S= PCR_REG); + loongson_spi->sper =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_S= PER_REG); + loongson_spi->spsr =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_S= PSR_REG); + loongson_spi->para =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_P= ARA_REG); + loongson_spi->sfcs =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_S= FCS_REG); + loongson_spi->timi =3D loongson_spi_read_reg(loongson_spi, LOONGSON_SPI_T= IMI_REG); + + return 0; +} + +static int __maybe_unused loongson_spi_resume(struct device *dev) +{ + struct loongson_spi *loongson_spi; + struct spi_master *master; + + master =3D dev_get_drvdata(dev); + loongson_spi =3D spi_master_get_devdata(master); + + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_SPCR_REG, loongson_spi-= >spcr); + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_SPER_REG, loongson_spi-= >sper); + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_SPSR_REG, loongson_spi-= >spsr); + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_PARA_REG, loongson_spi-= >para); + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_SFCS_REG, loongson_spi-= >sfcs); + loongson_spi_write_reg(loongson_spi, LOONGSON_SPI_TIMI_REG, loongson_spi-= >timi); + + return 0; +} + +const struct dev_pm_ops loongson_spi_dev_pm_ops =3D { + .suspend =3D loongson_spi_suspend, + .resume =3D loongson_spi_resume, +}; +EXPORT_SYMBOL_GPL(loongson_spi_dev_pm_ops); + +MODULE_DESCRIPTION("Loongson spi core driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi-loongson-pci.c b/drivers/spi/spi-loongson-pci.c new file mode 100644 index 000000000000..b811de769ecb --- /dev/null +++ b/drivers/spi/spi-loongson-pci.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +// PCI interface driver for Loongson SPI Support +// Copyright (C) 2023 Loongson Technology Corporation Limited + +#include + +#include "spi-loongson.h" + +static int loongson_spi_pci_register(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + int ret; + unsigned char v8; + struct resource res[2]; + struct device *dev =3D &pdev->dev; + + ret =3D pci_enable_device(pdev); + if (ret < 0) { + dev_err(dev, "cannot enable pci device\n"); + goto err_out; + } + + ret =3D pci_request_region(pdev, 0, "loongson-spi io"); + if (ret < 0) { + dev_err(dev, "cannot request region 0.\n"); + goto err_out; + } + + res[0].start =3D pci_resource_start(pdev, 0); + res[0].end =3D pci_resource_end(pdev, 0); + ret =3D pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &v8); + + if (ret =3D=3D PCIBIOS_SUCCESSFUL) { + res[1].start =3D v8; + res[1].end =3D v8; + } + + ret =3D loongson_spi_init_master(dev, res); + if (ret) + dev_err(dev, "failed to initialize master\n"); + +err_out: + return ret; +} + +static void loongson_spi_pci_unregister(struct pci_dev *pdev) +{ + pci_release_region(pdev, 0); +} + +static struct pci_device_id loongson_spi_devices[] =3D { + {PCI_DEVICE(0x14, 0x7a0b)}, + {PCI_DEVICE(0x14, 0x7a1b)}, + {0, 0, 0, 0, 0, 0, 0} +}; +MODULE_DEVICE_TABLE(pci, loongson_spi_devices); + +static struct pci_driver loongson_spi_pci_driver =3D { + .name =3D "loongson-spi-pci", + .id_table =3D loongson_spi_devices, + .probe =3D loongson_spi_pci_register, + .remove =3D loongson_spi_pci_unregister, + .driver =3D { + .bus =3D &pci_bus_type, + .pm =3D &loongson_spi_dev_pm_ops, + }, +}; + +static int __init loongson_spi_pci_init(void) +{ + int ret; + + ret =3D pci_register_driver(&loongson_spi_pci_driver); + if (ret) + return ret; + + return 0; +} + +static void __exit loongson_spi_pci_exit(void) +{ + pci_unregister_driver(&loongson_spi_pci_driver); +} + +module_init(loongson_spi_pci_init); +module_exit(loongson_spi_pci_exit); + +MODULE_DESCRIPTION("Loongson spi pci driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi-loongson-plat.c b/drivers/spi/spi-loongson-pla= t.c new file mode 100644 index 000000000000..8f4aa70168f3 --- /dev/null +++ b/drivers/spi/spi-loongson-plat.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Platform driver for Loongson SPI Support +// Copyright (C) 2023 Loongson Technology Corporation Limited + +#include +#include + +#include "spi-loongson.h" + +static int loongson_spi_platform_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct resource *res; + int ret; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res =3D=3D NULL) { + dev_err(dev, "cannot get io resource memory\n"); + return -ENOENT; + } + + ret =3D loongson_spi_init_master(dev, res); + if (ret) + dev_err(dev, "failed to initialize master\n"); + + return ret; +} + +static const struct of_device_id loongson_spi_id_table[] =3D { + { .compatible =3D "loongson,ls2k-spi", }, + { } +}; +MODULE_DEVICE_TABLE(of, loongson_spi_id_table); + +static struct platform_driver loongson_spi_plat_driver =3D { + .probe =3D loongson_spi_platform_probe, + .driver =3D { + .name =3D "loongson-spi", + .owner =3D THIS_MODULE, + .bus =3D &platform_bus_type, + .pm =3D &loongson_spi_dev_pm_ops, + .of_match_table =3D loongson_spi_id_table, + }, +}; + +static int __init loongson_spi_plat_init(void) +{ + int ret; + + ret =3D platform_driver_register(&loongson_spi_plat_driver); + if (ret) + return ret; + + return 0; +} + +static void __exit loongson_spi_plat_exit(void) +{ + platform_driver_unregister(&loongson_spi_plat_driver); +} + +module_init(loongson_spi_plat_init); +module_exit(loongson_spi_plat_exit); + +MODULE_DESCRIPTION("Loongson spi platform driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/spi/spi-loongson.h b/drivers/spi/spi-loongson.h new file mode 100644 index 000000000000..44818340188d --- /dev/null +++ b/drivers/spi/spi-loongson.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Header File for Loongson SPI Driver. */ +/* Copyright (C) 2023 Loongson Technology Corporation Limited */ + +#ifndef __LINUX_SPI_LOONGSON_H +#define __LINUX_SPI_LOONGSON_H + +#define LOONGSON_SPI_SPCR_REG 0x00 +#define LOONGSON_SPI_SPSR_REG 0x01 +#define LOONGSON_SPI_FIFO_REG 0x02 +#define LOONGSON_SPI_SPER_REG 0x03 +#define LOONGSON_SPI_PARA_REG 0x04 +#define LOONGSON_SPI_SFCS_REG 0x05 +#define LOONGSON_SPI_TIMI_REG 0x06 + +/* Bits definition for Loongson SPI register */ +#define LOONGSON_SPI_PARA_MEM_EN BIT(0) +#define LOONGSON_SPI_SPSR_SPIF BIT(7) +#define LOONGSON_SPI_SPSR_WCOL BIT(6) +#define LOONGSON_SPI_SPCR_SPE BIT(6) + +#define SPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000) + +struct loongson_spi { + struct spi_master *master; + void __iomem *base; + int cs_active; + unsigned int hz; + unsigned char spcr; + unsigned char sper; + unsigned char spsr; + unsigned char para; + unsigned char sfcs; + unsigned char timi; + unsigned int mode; + u64 clk_rate; +}; + +extern int loongson_spi_init_master(struct device *dev, struct resource *r= es); +extern const struct dev_pm_ops loongson_spi_dev_pm_ops; +#endif /* __LINUX_SPI_LOONGSON_H */ --=20 2.20.1