From nobody Tue Sep 16 14:09:22 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1EAFC76196 for ; Tue, 28 Mar 2023 03:54:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232575AbjC1DyF (ORCPT ); Mon, 27 Mar 2023 23:54:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232842AbjC1Dxk (ORCPT ); Mon, 27 Mar 2023 23:53:40 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 817642723 for ; Mon, 27 Mar 2023 20:53:12 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id p13-20020a17090a284d00b0023d2e945aebso796392pjf.0 for ; Mon, 27 Mar 2023 20:53:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679975592; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y7s+91AtfNZFr11BBB79AwltySbIUEsIHQ1Gjnv2r90=; b=GEjjNtl9m0uaQ14T5Cp1Xzcub+kVAmI1XQP1g3dY3m8lo5LAKKLNNVYVlxv7+bKlMA aRe3MlgyoNB6TZOAM3CmHphWZB7MwQpq0xEz1SPLpc9j43+L+WzMCZhR2jJHCsZrxxBg oauGLWdq3+weB5U+6utGq3PfFDXlHAfL36MmLcIh4IxAF9oCkYpIUhILDb6O1c2kMBCC GkI1ZvIh6E/Zh4Qbn3Jz8fcQj3inLGLdNzP3RyHR3tiTE9dzWt6EdvPV+wzYExHZX7ZE ZMoysS6lt4jlK4loF2zpDXRDDPEoWJaT5LhD8kuYoUoxU0iK7elxFMScvp0V6EnJi2lE yPKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679975592; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y7s+91AtfNZFr11BBB79AwltySbIUEsIHQ1Gjnv2r90=; b=cKNTfxl8G1XBiiFve1D3GSZlT2x15TmZQlDwWpHQ4tRUafqczsQVVx56RH235NNrCa 3M7PzGvBWZk1YyumDYFQX+lKXbjimlVel4GcXHZxqdOdztk0cmOqS4mrwzx8rau+ZA2m V+YkUztS6UpiJqnkbARzdownHIRePhduJt9TAdaBgIIEcacCkzO3h89KM2KP1x40uxc6 vxxpyFAXLTzzWHHrsddOllxCAxnN1UiF6xpTl+yu6e/7yiXf1duPEq0PWiR/fHf6A5n4 wVfZ3lfhsEMMh+ZGkHLudhh1gpihWNZfyt+BgEW7ow1AmFlHd6tXhpX9ejKLpz9PLxNS uHEQ== X-Gm-Message-State: AAQBX9cNa7dDifpFC6zIFsRL1PJIL1fmOkT73TBkWAWvt3eiHT4Gy2Jm DxgwXtaF9WiSdwC3ZnPWar2pfw== X-Google-Smtp-Source: AKy350blb+cJVDOCRTgjKfm7KJqOhQzjeIhTlA8ZV+SWnKT1CdLB9KsiVTmjKDZxHKrOPWQ3G5xUKw== X-Received: by 2002:a17:90b:3b90:b0:23f:a674:dc0b with SMTP id pc16-20020a17090b3b9000b0023fa674dc0bmr16062620pjb.15.1679975591902; Mon, 27 Mar 2023 20:53:11 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.82.104]) by smtp.gmail.com with ESMTPSA id g6-20020a170902740600b0019cb534a824sm19880278pll.172.2023.03.27.20.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 20:53:11 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Palmer Dabbelt Subject: [PATCH v18 7/7] irqchip/riscv-intc: Add empty irq_eoi() for chained irq handlers Date: Tue, 28 Mar 2023 09:22:23 +0530 Message-Id: <20230328035223.1480939-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230328035223.1480939-1-apatel@ventanamicro.com> References: <20230328035223.1480939-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We add empty irq_eoi() in RISC-V INTC driver for child irqchip drivers (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) which implement chained handlers for parent per-HART local interrupts. This hels us avoid unnecessary mask/unmask of per-HART local interrupts at the time of handling interrupts. Signed-off-by: Anup Patel Acked-by: Palmer Dabbelt --- drivers/irqchip/irq-riscv-intc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 784d25645704..f229e3e66387 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -46,10 +46,27 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } =20 +static void riscv_intc_irq_eoi(struct irq_data *d) +{ + /* + * The RISC-V INTC driver uses handle_percpu_devid_irq() flow + * for the per-HART local interrupts and child irqchip drivers + * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement + * chained handlers for the per-HART local interrupts. + * + * In the absence of irq_eoi(), the chained_irq_enter() and + * chained_irq_exit() functions (used by child irqchip drivers) + * will do unnecessary mask/unmask of per-HART local interrupts + * at the time of handling interrupts. To avoid this, we provide + * an empty irq_eoi() callback for RISC-V INTC irqchip. + */ +} + static struct irq_chip riscv_intc_chip =3D { .name =3D "RISC-V INTC", .irq_mask =3D riscv_intc_irq_mask, .irq_unmask =3D riscv_intc_irq_unmask, + .irq_eoi =3D riscv_intc_irq_eoi, }; =20 static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, --=20 2.34.1