From nobody Tue Sep 16 14:09:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B0AAC76196 for ; Tue, 28 Mar 2023 03:53:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232884AbjC1Dxr (ORCPT ); Mon, 27 Mar 2023 23:53:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232795AbjC1DxR (ORCPT ); Mon, 27 Mar 2023 23:53:17 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 904C230E2 for ; Mon, 27 Mar 2023 20:53:03 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id e15-20020a17090ac20f00b0023d1b009f52so13890370pjt.2 for ; Mon, 27 Mar 2023 20:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679975583; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a2tND4+OZFie8n8iNE7DZHGFfCkqDurrEJT4noc8Afo=; b=LUWh1K+PyVs1rXPdYzIcKHG3d2DqIoNvHunWDZ2aAsc+VJGJIscCSWu7a041Mox94H Oqb0gWGjD52jhvykiDpPYoNqWMGsAtyEGQnn6GqGkau7LNVU3RO03yUVkJHZE3bKVW/c mwD8L66sui6Qsbf/m3mRhqM+763sLzRmYglGhdEzuu0OpqfVWT/IdP+JuFETiL+hMCyq 9ztDMqz/6BFBlW2zN4iycf5U+IgKsPikbOIgq5y1yGjih21bzWwI5D6sJ2SkOy2YzE1W Q++6D+ZmMXbLzVAGMQ/ZD/0IfIi72rWaK2XsFLtrvZNRWFrlGYh7fmHM5680Xau8eSyx Efnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679975583; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a2tND4+OZFie8n8iNE7DZHGFfCkqDurrEJT4noc8Afo=; b=mtPMICkzBfr890V57TGdkZ6Nt5/d7GhcUd4eX79ImlRlIqrxHkse0+Fxswn3V/D+22 YScxDOe8D0S8QvgL9bfW7QiJ7xlnjTNXXJAAgBq0WHg0tj5kMtCIkafjEnoe08LwJxTZ KOpDtLV5G2/S2xm7HssTx3xSpYB0lKbfpOyD37DtZDEOZiCgdcHa0i3E9W7OWptkqFwa FCmsNMPAzXuFoDpLwmXysip3Hz9Ze+jPI6sirLZvATtmx9A+h44AZLNYTOHaE7paHHSA WtYD7Vqz9TlJYLMCt4CaLHT+f3Ii/TkljNFg3PDhcBBg8zoNQfp7cYN8ZkwSEfCKKVae rT/g== X-Gm-Message-State: AAQBX9fpFj7XTahNCoLb9EiflOds/+5RyCvRjKQAJu91+J3Th/zewMy5 5Qdnlc/f+holJaPiFuJl3Y/nDg== X-Google-Smtp-Source: AKy350ac+F60romXUhiPhc1CAN9WKBTbifYJq4pb2vHGoxq1DEY0sxRmPX3cY/opN76O8vIBqzJljw== X-Received: by 2002:a17:902:eecc:b0:1a0:6bd4:ea78 with SMTP id h12-20020a170902eecc00b001a06bd4ea78mr12280592plb.31.1679975582804; Mon, 27 Mar 2023 20:53:02 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.82.104]) by smtp.gmail.com with ESMTPSA id g6-20020a170902740600b0019cb534a824sm19880278pll.172.2023.03.27.20.52.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 20:53:02 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Palmer Dabbelt Subject: [PATCH v18 5/7] RISC-V: Use IPIs for remote TLB flush when possible Date: Tue, 28 Mar 2023 09:22:21 +0530 Message-Id: <20230328035223.1480939-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230328035223.1480939-1-apatel@ventanamicro.com> References: <20230328035223.1480939-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we have specialized interrupt controller (such as AIA IMSIC) which allows supervisor mode to directly inject IPIs without any assistance from M-mode or HS-mode then using such specialized interrupt controller, we can do remote TLB flushes directly from supervisor mode instead of using the SBI RFENCE calls. This patch extends remote TLB flush functions to use supervisor mode IPIs whenever direct supervisor mode IPIs.are supported by interrupt controller. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Acked-by: Palmer Dabbelt --- arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++++++++------- 1 file changed, 78 insertions(+), 15 deletions(-) diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c index ef701fa83f36..77be59aadc73 100644 --- a/arch/riscv/mm/tlbflush.c +++ b/arch/riscv/mm/tlbflush.c @@ -23,14 +23,62 @@ static inline void local_flush_tlb_page_asid(unsigned l= ong addr, : "memory"); } =20 +static inline void local_flush_tlb_range(unsigned long start, + unsigned long size, unsigned long stride) +{ + if (size <=3D stride) + local_flush_tlb_page(start); + else + local_flush_tlb_all(); +} + +static inline void local_flush_tlb_range_asid(unsigned long start, + unsigned long size, unsigned long stride, unsigned long asid) +{ + if (size <=3D stride) + local_flush_tlb_page_asid(start, asid); + else + local_flush_tlb_all_asid(asid); +} + +static void __ipi_flush_tlb_all(void *info) +{ + local_flush_tlb_all(); +} + void flush_tlb_all(void) { - sbi_remote_sfence_vma(NULL, 0, -1); + if (riscv_use_ipi_for_rfence()) + on_each_cpu(__ipi_flush_tlb_all, NULL, 1); + else + sbi_remote_sfence_vma(NULL, 0, -1); +} + +struct flush_tlb_range_data { + unsigned long asid; + unsigned long start; + unsigned long size; + unsigned long stride; +}; + +static void __ipi_flush_tlb_range_asid(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid); +} + +static void __ipi_flush_tlb_range(void *info) +{ + struct flush_tlb_range_data *d =3D info; + + local_flush_tlb_range(d->start, d->size, d->stride); } =20 -static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long star= t, - unsigned long size, unsigned long stride) +static void __flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long size, unsigned long stride) { + struct flush_tlb_range_data ftd; struct cpumask *cmask =3D mm_cpumask(mm); unsigned int cpuid; bool broadcast; @@ -45,19 +93,34 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm,= unsigned long start, unsigned long asid =3D atomic_long_read(&mm->context.id) & asid_mask; =20 if (broadcast) { - sbi_remote_sfence_vma_asid(cmask, start, size, asid); - } else if (size <=3D stride) { - local_flush_tlb_page_asid(start, asid); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D asid; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range_asid, + &ftd, 1); + } else + sbi_remote_sfence_vma_asid(cmask, + start, size, asid); } else { - local_flush_tlb_all_asid(asid); + local_flush_tlb_range_asid(start, size, stride, asid); } } else { if (broadcast) { - sbi_remote_sfence_vma(cmask, start, size); - } else if (size <=3D stride) { - local_flush_tlb_page(start); + if (riscv_use_ipi_for_rfence()) { + ftd.asid =3D 0; + ftd.start =3D start; + ftd.size =3D size; + ftd.stride =3D stride; + on_each_cpu_mask(cmask, + __ipi_flush_tlb_range, + &ftd, 1); + } else + sbi_remote_sfence_vma(cmask, start, size); } else { - local_flush_tlb_all(); + local_flush_tlb_range(start, size, stride); } } =20 @@ -66,23 +129,23 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm= , unsigned long start, =20 void flush_tlb_mm(struct mm_struct *mm) { - __sbi_tlb_flush_range(mm, 0, -1, PAGE_SIZE); + __flush_tlb_range(mm, 0, -1, PAGE_SIZE); } =20 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { - __sbi_tlb_flush_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE); } =20 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PAGE_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE); } #ifdef CONFIG_TRANSPARENT_HUGEPAGE void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - __sbi_tlb_flush_range(vma->vm_mm, start, end - start, PMD_SIZE); + __flush_tlb_range(vma->vm_mm, start, end - start, PMD_SIZE); } #endif --=20 2.34.1