From nobody Tue Sep 16 14:09:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1200AC761A6 for ; Tue, 28 Mar 2023 03:52:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232598AbjC1Dw4 (ORCPT ); Mon, 27 Mar 2023 23:52:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232245AbjC1Dwu (ORCPT ); Mon, 27 Mar 2023 23:52:50 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13B9212E for ; Mon, 27 Mar 2023 20:52:49 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id r7-20020a17090b050700b002404be7920aso9854624pjz.5 for ; Mon, 27 Mar 2023 20:52:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679975568; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uVwIHEbuY4DYODvnj/1FGLFLezToqvIrfjUoJVxDh6c=; b=Qzmof5TkaDy435vR/2kdsApGTqv2LymvEK6dsVYIQuJpI6ie6+HAuEc1aygTQHkWBQ cj7ZXNIjJglW33iyom/Mczv2lRROzXQLXr2X5OKmJrhqt3Dkrx/aniA5W/kJdQHQYkhR cEPASv/mY7OjD3KHCs+xKTey0sijUaC/EDeWIJ0WdmxRmkKupgHN5qHwvbLli5Wgfrt8 IB7Y91bKDfIngKvahPezqU6zSbtFAfTuwe5MfQpzyTONZkUNBE70T2Lb6/9h2OXMB96G fzpnxxnxh1pYfcnMf3u7yRg6LwVUwpI6bm0DnfJ5ZlrMWQ+5hURFvNXnn20hL3k/veGS g9jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679975568; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uVwIHEbuY4DYODvnj/1FGLFLezToqvIrfjUoJVxDh6c=; b=NWbueSHQYPXoIgbEgGWjI/dpL3h1N8RJ8/y76hjq7PmdhryO1JJ8slkwdrJhcQDbeN M/5JoQ2QxIYGHEfHTcW2TgOyFcpt+jyO3h91FU6zojZkXa3k2C9+9uBzGXu8JYEM+q+X G4KaVOaFd6MFacAZ4VmepfWvJwNDDVQzjHxEtUpwUY1Rl7in/1Son39O7GEXI9QWpND9 DbMM1qtmU2DyNbvyDBJIQO/hb9CooAtGaouncKGYgLSneDEEdpfX2eC9iZhaAhudQ3bW vlk5DfPuUsCwDxhwKty1oX/Rtx0moAXfuX2gvhC4QvR8JiqXT1bbRgfVNyslwqd+pD3g V2DQ== X-Gm-Message-State: AAQBX9cCta9AczA+Xp0ya/oFUFGH9quXCUjQHU3Oha10o0QxfHCElAbq URm+1XFWb9nvP/TMGxCHJj0pOA== X-Google-Smtp-Source: AKy350b7z4snJDo+nMhmAw4uX0lNVsqOnCcXqLC6MBmrd3iAX0+lwbhL8A2ul7tG7f9gnaGPJF+fgQ== X-Received: by 2002:a17:902:fa47:b0:1a2:3e05:8efc with SMTP id lb7-20020a170902fa4700b001a23e058efcmr6840148plb.33.1679975568486; Mon, 27 Mar 2023 20:52:48 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.82.104]) by smtp.gmail.com with ESMTPSA id g6-20020a170902740600b0019cb534a824sm19880278pll.172.2023.03.27.20.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 20:52:48 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Daniel Lezcano Cc: Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Palmer Dabbelt Subject: [PATCH v18 2/7] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Date: Tue, 28 Mar 2023 09:22:18 +0530 Message-Id: <20230328035223.1480939-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230328035223.1480939-1-apatel@ventanamicro.com> References: <20230328035223.1480939-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Various RISC-V drivers (such as SBI IPI, SBI Timer, SBI PMU, and KVM RISC-V) don't have associated DT node but these drivers need standard per-CPU (local) interrupts defined by the RISC-V privileged specification. We add riscv_get_intc_hwnode() in arch/riscv which allows RISC-V drivers not having DT node to discover INTC hwnode which in-turn helps these drivers to map per-CPU (local) interrupts provided by the INTC driver. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Acked-by: Palmer Dabbelt --- arch/riscv/include/asm/irq.h | 4 ++++ arch/riscv/kernel/irq.c | 18 ++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 7 +++++++ 3 files changed, 29 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index e4c435509983..43b9ebfbd943 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,6 +12,10 @@ =20 #include =20 +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); + +struct fwnode_handle *riscv_get_intc_hwnode(void); + extern void __init init_IRQ(void); =20 #endif /* _ASM_RISCV_IRQ_H */ diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 7207fa08d78f..96d3171f0ca1 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -7,9 +7,27 @@ =20 #include #include +#include +#include #include #include =20 +static struct fwnode_handle *(*__get_intc_node)(void); + +void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) +{ + __get_intc_node =3D fn; +} + +struct fwnode_handle *riscv_get_intc_hwnode(void) +{ + if (__get_intc_node) + return __get_intc_node(); + + return NULL; +} +EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index 499e5f81b3fe..9066467e99e4 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -92,6 +92,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops= =3D { .xlate =3D irq_domain_xlate_onecell, }; =20 +static struct fwnode_handle *riscv_intc_hwnode(void) +{ + return intc_domain->fwnode; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -126,6 +131,8 @@ static int __init riscv_intc_init(struct device_node *n= ode, return rc; } =20 + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + cpuhp_setup_state(CPUHP_AP_IRQ_RISCV_STARTING, "irqchip/riscv/intc:starting", riscv_intc_cpu_starting, --=20 2.34.1