From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81BCCC761A6 for ; Tue, 28 Mar 2023 02:28:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232604AbjC1C2N (ORCPT ); Mon, 27 Mar 2023 22:28:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231925AbjC1C2I (ORCPT ); Mon, 27 Mar 2023 22:28:08 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 778E019A0; Mon, 27 Mar 2023 19:28:02 -0700 (PDT) X-UUID: 2648fca4cd1011eda9a90f0bb45854f4-20230328 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=X5BMOUCftBqUoS89OY1vJghk0U8zsFcVshTFWmsRm4E=; b=Te6hZgZxmE+9ZlNp0EIBpyaoKkkJx2zzUlGOalF4wWVQYjNnDSgF4DKtv/RTrO+iW5U9SRvAjmsb+I5wwWsItxEffFumVsz+KdLsQHABJMOLUmGJf36IkKZ8YPzF2HgOo6rOhaPw9MlC6dfNEWpklEWAdobHp8agJFTQ7JBxBJQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:8cccf62e-6d00-4d0a-b45c-672bcf2be83e,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22,REQID:8cccf62e-6d00-4d0a-b45c-672bcf2be83e,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c,CLOUDID:94e98db4-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:23032810275947VRII9Y,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: 2648fca4cd1011eda9a90f0bb45854f4-20230328 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1933316158; Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:54 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 01/11] dt-bindings: remoteproc: mediatek: Improve the rpmsg subnode definition Date: Tue, 28 Mar 2023 10:27:23 +0800 Message-ID: <20230328022733.29910-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Improve the definition of the rpmsg subnode by assigning a distinct node name and adding the definition source of node properties. Signed-off-by: Tinghan Shen Acked-by: Rob Herring --- .../bindings/remoteproc/mtk,scp.yaml | 31 +++++++++---------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Do= cumentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 895415772d1d..271081df0e46 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -58,6 +58,18 @@ properties: memory-region: maxItems: 1 =20 + cros-ec-rpmsg: + $ref: /schemas/mfd/google,cros-ec.yaml + description: + This subnode represents the rpmsg device. The properties + of this node are defined by the individual bindings for + the rpmsg devices. + + required: + - mediatek,rpmsg-name + + unevaluatedProperties: false + required: - compatible - reg @@ -89,21 +101,7 @@ allOf: reg-names: maxItems: 2 =20 -additionalProperties: - type: object - description: - Subnodes of the SCP represent rpmsg devices. The names of the devices - are not important. The properties of these nodes are defined by the - individual bindings for the rpmsg devices. - properties: - mediatek,rpmsg-name: - $ref: /schemas/types.yaml#/definitions/string-array - description: - Contains the name for the rpmsg device. Used to match - the subnode to rpmsg device announced by SCP. - - required: - - mediatek,rpmsg-name +additionalProperties: false =20 examples: - | @@ -118,7 +116,8 @@ examples: clocks =3D <&infracfg CLK_INFRA_SCPSYS>; clock-names =3D "main"; =20 - cros_ec { + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; }; --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9CB3C6FD1D for ; Tue, 28 Mar 2023 02:28:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231717AbjC1C2a (ORCPT ); Mon, 27 Mar 2023 22:28:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232115AbjC1C2L (ORCPT ); Mon, 27 Mar 2023 22:28:11 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9352219BA; Mon, 27 Mar 2023 19:28:08 -0700 (PDT) X-UUID: 266431d6cd1011edb6b9f13eb10bd0fe-20230328 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6RFdGCQH8CwMl3cCS8uEv83UelcwU4aqIgZl9J6q30U=; b=Oy5kob+RkQps7huHw82voMwAa67bll06OScjMma7GiD0A0EgfpmS44rtviwHHDfODcvA621fOUxEHbAddS/QLbYFV6DkPlW3nF+jTu3mhAKTEIov60XvkAscIGFr+Pm67YQa5lvTcTgtD9SKnpfnr5fU/rLbf2UXHbSwVav/4dY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:77a87fa5-e34d-4718-a7da-a3c1728263ae,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22,REQID:77a87fa5-e34d-4718-a7da-a3c1728263ae,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c,CLOUDID:6bc8ac29-564d-42d9-9875-7c868ee415ec,B ulkID:230328102759ZL8K3IWQ,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 266431d6cd1011edb6b9f13eb10bd0fe-20230328 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1155895560; Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:55 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 02/11] arm64: dts: mediatek: Update the node name of SCP rpmsg subnode Date: Tue, 28 Mar 2023 10:27:24 +0800 Message-ID: <20230328022733.29910-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Align the node name with the definition in SCP bindings. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Acked-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/bo= ot/dts/mediatek/mt8183-kukui.dtsi index fbe14b13051a..a259eb043de5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -810,7 +810,7 @@ pinctrl-names =3D "default"; pinctrl-0 =3D <&scp_pins>; =20 - cros_ec { + cros-ec-rpmsg { compatible =3D "google,cros-ec-rpmsg"; mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/= boot/dts/mediatek/mt8192-asurada.dtsi index 9f12257ab4e7..8f14b633c1e1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1260,7 +1260,7 @@ pinctrl-names =3D "default"; pinctrl-0 =3D <&scp_pins>; =20 - cros-ec { + cros-ec-rpmsg { compatible =3D "google,cros-ec-rpmsg"; mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA77BC6FD1D for ; Tue, 28 Mar 2023 02:28:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232715AbjC1C2h (ORCPT ); Mon, 27 Mar 2023 22:28:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232606AbjC1C2N (ORCPT ); Mon, 27 Mar 2023 22:28:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 929D7199E; Mon, 27 Mar 2023 19:28:06 -0700 (PDT) X-UUID: 26719128cd1011edb6b9f13eb10bd0fe-20230328 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mHZvfrM0o5UaIt01vL+X0Xi78aCQjddfdApBpcmPqT8=; b=YfxyTaxO2DohYv6Fq83k4+cGcXI/baBwFjSSI7pynx95JQEc3ExdkBLA/WcOQm/UyS5auv4X9fvGrfB36ANbRp6BvSKRiCWxaWByqr5f81BfBX3wn+HcDrXcsZjFvt2m9TLxhWtqU0pDWWvdNlDggTU5oAxVrHEniWa++DE8XD0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:79d98bda-4b24-4fb2-990a-c6fe624fea99,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22,REQID:79d98bda-4b24-4fb2-990a-c6fe624fea99,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c,CLOUDID:91e98db4-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230328102759U2HMDMM3,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 26719128cd1011edb6b9f13eb10bd0fe-20230328 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1266171292; Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:55 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 03/11] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Date: Tue, 28 Mar 2023 10:27:25 +0800 Message-ID: <20230328022733.29910-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the SCP binding to describe the MT8195 dual-core SCP. Under different applications, the MT8195 SCP can be used as single-core or dual-core. This change keeps the single-core definitions and adds new definitions for the dual-core use case. Signed-off-by: Tinghan Shen Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/remoteproc/mtk,scp.yaml | 145 +++++++++++++++++- 1 file changed, 141 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Do= cumentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 271081df0e46..09102dda4942 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -21,6 +21,7 @@ properties: - mediatek,mt8188-scp - mediatek,mt8192-scp - mediatek,mt8195-scp + - mediatek,mt8195-scp-dual =20 reg: description: @@ -31,10 +32,7 @@ properties: =20 reg-names: minItems: 2 - items: - - const: sram - - const: cfg - - const: l1tcm + maxItems: 3 =20 clocks: description: @@ -70,6 +68,81 @@ properties: =20 unevaluatedProperties: false =20 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: + description: + Standard ranges definition providing address translations for + local SCP SRAM address spaces to bus addresses. + +patternProperties: + "^scp@[a-f0-9]+$": + type: object + description: + The MediaTek SCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address sp= ace + for the processor. + + Each SCP core has own cache memory. The SRAM and L1TCM are shared by + cores. The power of cache, SRAM and L1TCM power should be enabled + before booting SCP cores. The size of cache, SRAM, and L1TCM are var= ied + on differnt SoCs. + + The SCP cores do not use an MMU, but has a set of registers to + control the translations between 32-bit CPU addresses into system bus + addresses. Cache and memory access settings are provided through a + Memory Protection Unit (MPU), programmable only from the SCP. + + properties: + compatible: + enum: + - mediatek,scp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing sub cores of multi-core SCP. + + memory-region: + maxItems: 1 + + cros-ec-rpmsg: + $ref: /schemas/mfd/google,cros-ec.yaml + description: + This subnode represents the rpmsg device. The properties + of this node are defined by the individual bindings for + the rpmsg devices. + + required: + - mediatek,rpmsg-name + + unevaluatedProperties: false + + required: + - compatible + - reg + - reg-names + + additionalProperties: false + required: - compatible - reg @@ -99,7 +172,37 @@ allOf: reg: maxItems: 2 reg-names: + items: + - const: sram + - const: cfg + - if: + properties: + compatible: + enum: + - mediatek,mt8192-scp + - mediatek,mt8195-scp + then: + properties: + reg: + maxItems: 3 + reg-names: + items: + - const: sram + - const: cfg + - const: l1tcm + - if: + properties: + compatible: + enum: + - mediatek,mt8195-scp-dual + then: + properties: + reg: maxItems: 2 + reg-names: + items: + - const: cfg + - const: l1tcm =20 additionalProperties: false =20 @@ -121,3 +224,37 @@ examples: mediatek,rpmsg-name =3D "cros-ec-rpmsg"; }; }; + + - | + scp@10500000 { + compatible =3D "mediatek,mt8195-scp-dual"; + reg =3D <0x10720000 0xe0000>, + <0x10700000 0x8000>; + reg-names =3D "cfg", "l1tcm"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x10500000 0x100000>; + + scp@0 { + compatible =3D "mediatek,scp-core"; + reg =3D <0x0 0xa0000>; + reg-names =3D "sram"; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; + }; + + scp@a0000 { + compatible =3D "mediatek,scp-core"; + reg =3D <0xa0000 0x20000>; + reg-names =3D "sram"; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; + }; + }; --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7866CC76195 for ; Tue, 28 Mar 2023 02:28:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232799AbjC1C2o (ORCPT ); Mon, 27 Mar 2023 22:28:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232626AbjC1C2N (ORCPT ); Mon, 27 Mar 2023 22:28:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91E602696; Mon, 27 Mar 2023 19:28:10 -0700 (PDT) X-UUID: 26672788cd1011edb6b9f13eb10bd0fe-20230328 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=cMNTIJZmGwYCT3gi3BFOionOLTyJOICMUovIktXwWP4=; b=bnctapdHUyRcp5I5ijFr5TqsArgXQLvUUzLnCWWHUJey2QOEoXL7OZullujO+hlJVfK52rqck243+HiILbijt/31qFv/mGGiDsevQ+jLFDyfkWqxGwHEgwJkJd3G/PDpfoG+JX0v3nGHsiBwsHAx149Exbl6OXd0LhEKQq6Tntg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:ececd07a-288b-403e-a50c-50a67fb45ee0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22,REQID:ececd07a-288b-403e-a50c-50a67fb45ee0,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c,CLOUDID:89e98db4-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230328102759KIOO0OL2,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 26672788cd1011edb6b9f13eb10bd0fe-20230328 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 862668222; Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:55 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 04/11] remoteproc: mediatek: Add MT8195 SCP core 1 operations Date: Tue, 28 Mar 2023 10:27:26 +0800 Message-ID: <20230328022733.29910-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SCP rproc driver has a set of chip dependent callbacks for boot sequence and IRQ handling. Implement these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 9 ++++++ drivers/remoteproc/mtk_scp.c | 56 +++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index ea6fa1100a00..c0905aec3b4b 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) =20 #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -56,6 +57,14 @@ =20 #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) =20 +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_CFG 0x20034 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 =20 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 0861b76f185f..a3b9bc158cd9 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -176,6 +176,16 @@ static void mt8192_scp_reset_deassert(struct mtk_scp *= scp) writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); } =20 +static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); +} + +static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); +} + static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -212,6 +222,18 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } =20 +static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host =3D readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) + scp_ipi_handler(scp); + + writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp =3D priv; @@ -453,6 +475,19 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) return 0; } =20 +static int mt8195_scp_c1_before_load(struct mtk_scp *scp) +{ + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* hold SCP in reset while loading FW. */ + scp->data->scp_reset_assert(scp); + + /* enable MPU for all memory regions */ + writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + + return 0; +} + static int scp_load(struct rproc *rproc, const struct firmware *fw) { struct mtk_scp *scp =3D rproc->priv; @@ -625,6 +660,15 @@ static void mt8195_scp_stop(struct mtk_scp *scp) writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); } =20 +static void mt8195_scp_c1_stop(struct mtk_scp *scp) +{ + /* Power off CPU SRAM */ + scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); +} + static int scp_stop(struct rproc *rproc) { struct mtk_scp *scp =3D (struct mtk_scp *)rproc->priv; @@ -991,6 +1035,18 @@ static const struct mtk_scp_of_data mt8195_of_data = =3D { .host_to_scp_int_bit =3D MT8192_HOST_IPC_INT_BIT, }; =20 +static const struct mtk_scp_of_data mt8195_of_data_c1 =3D { + .scp_clk_get =3D mt8195_scp_clk_get, + .scp_before_load =3D mt8195_scp_c1_before_load, + .scp_irq_handler =3D mt8195_scp_c1_irq_handler, + .scp_reset_assert =3D mt8195_scp_c1_reset_assert, + .scp_reset_deassert =3D mt8195_scp_c1_reset_deassert, + .scp_stop =3D mt8195_scp_c1_stop, + .scp_da_to_va =3D mt8192_scp_da_to_va, + .host_to_scp_reg =3D MT8192_GIPC_IN_SET, + .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, +}; + static const struct of_device_id mtk_scp_of_match[] =3D { { .compatible =3D "mediatek,mt8183-scp", .data =3D &mt8183_of_data }, { .compatible =3D "mediatek,mt8186-scp", .data =3D &mt8186_of_data }, --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01CDDC6FD1D for ; Tue, 28 Mar 2023 02:28:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232718AbjC1C21 (ORCPT ); Mon, 27 Mar 2023 22:28:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232287AbjC1C2L (ORCPT ); Mon, 27 Mar 2023 22:28:11 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 951C619A8; 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Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:55 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 05/11] remoteproc: mediatek: Extract remoteproc initialization flow Date: Tue, 28 Mar 2023 10:27:27 +0800 Message-ID: <20230328022733.29910-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is the preparation for probing multi-core SCP. The remoteproc initialization flow is similar on cores and is reused to avoid redundant code. The registers of config and l1tcm are shared for multi-core SCP. Reuse the mapped addresses for all cores. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 64 +++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 19 deletions(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index a3b9bc158cd9..32ecd1450c6f 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -23,6 +23,13 @@ #define MAX_CODE_SIZE 0x500000 #define SECTION_NAME_IPI_BUFFER ".ipi_buffer" =20 +struct mtk_scp_of_regs { + void __iomem *reg_base; + void __iomem *l1tcm_base; + size_t l1tcm_size; + phys_addr_t l1tcm_phys; +}; + /** * scp_get() - get a reference to SCP. * @@ -855,7 +862,8 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } } =20 -static int scp_probe(struct platform_device *pdev) +static int scp_rproc_init(struct platform_device *pdev, + struct mtk_scp_of_regs *of_regs) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; @@ -879,6 +887,11 @@ static int scp_probe(struct platform_device *pdev) scp->data =3D of_device_get_match_data(dev); platform_set_drvdata(pdev, scp); =20 + scp->reg_base =3D of_regs->reg_base; + scp->l1tcm_base =3D of_regs->l1tcm_base; + scp->l1tcm_size =3D of_regs->l1tcm_size; + scp->l1tcm_phys =3D of_regs->l1tcm_phys; + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); scp->sram_base =3D devm_ioremap_resource(dev, res); if (IS_ERR(scp->sram_base)) @@ -888,24 +901,6 @@ static int scp_probe(struct platform_device *pdev) scp->sram_size =3D resource_size(res); scp->sram_phys =3D res->start; =20 - /* l1tcm is an optional memory region */ - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm"); - scp->l1tcm_base =3D devm_ioremap_resource(dev, res); - if (IS_ERR(scp->l1tcm_base)) { - ret =3D PTR_ERR(scp->l1tcm_base); - if (ret !=3D -EINVAL) { - return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n"); - } - } else { - scp->l1tcm_size =3D resource_size(res); - scp->l1tcm_phys =3D res->start; - } - - scp->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "cfg"); - if (IS_ERR(scp->reg_base)) - return dev_err_probe(dev, PTR_ERR(scp->reg_base), - "Failed to parse and map cfg memory\n"); - ret =3D scp->data->scp_clk_get(scp); if (ret) return ret; @@ -957,6 +952,37 @@ static int scp_probe(struct platform_device *pdev) return ret; } =20 +static int scp_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_scp_of_regs scp_regs; + struct resource *res; + int ret; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + scp_regs.reg_base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(scp_regs.reg_base)) + return dev_err_probe(dev, PTR_ERR(scp_regs.reg_base), + "Failed to parse and map cfg memory\n"); + + /* l1tcm is an optional memory region */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "l1tcm"); + scp_regs.l1tcm_base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(scp_regs.l1tcm_base)) { + ret =3D PTR_ERR(scp_regs.l1tcm_base); + if (ret !=3D -EINVAL) + return dev_err_probe(dev, ret, "Failed to map l1tcm memory\n"); + + scp_regs.l1tcm_size =3D 0; + scp_regs.l1tcm_phys =3D 0; + } else { + scp_regs.l1tcm_size =3D resource_size(res); + scp_regs.l1tcm_phys =3D res->start; + } + + return scp_rproc_init(pdev, &scp_regs); +} + static int scp_remove(struct platform_device *pdev) { struct mtk_scp *scp =3D platform_get_drvdata(pdev); --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE96DC6FD1D for ; Tue, 28 Mar 2023 02:28:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232648AbjC1C2U (ORCPT ); Mon, 27 Mar 2023 22:28:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232531AbjC1C2K (ORCPT ); Mon, 27 Mar 2023 22:28:10 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 770F0DD; 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Tue, 28 Mar 2023 10:27:57 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:55 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 06/11] remoteproc: mediatek: Probe multi-core SCP Date: Tue, 28 Mar 2023 10:27:28 +0800 Message-ID: <20230328022733.29910-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The difference of single-core SCP and multi-core SCP device tree is the presence of child device nodes described SCP cores. The SCP driver populates the platform device and checks the child nodes to identify whether it's a single-core SCP or a multi-core SCP. Add the remoteproc instances for single-core SCP and multi-core SCP to the new added SCP cluster list. When the SCP driver is removed, it cleanup resources by walking through the cluster list. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 3 + drivers/remoteproc/mtk_scp.c | 150 ++++++++++++++++++++++++++++---- 2 files changed, 137 insertions(+), 16 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index c0905aec3b4b..b73b60c22ea1 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -128,6 +128,9 @@ struct mtk_scp { size_t dram_size; =20 struct rproc_subdev *rpmsg_subdev; + + struct list_head elem; + struct list_head *cluster; }; =20 /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 32ecd1450c6f..71882ed31e16 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -30,6 +30,8 @@ struct mtk_scp_of_regs { phys_addr_t l1tcm_phys; }; =20 +static struct list_head cluster_cores; + /** * scp_get() - get a reference to SCP. * @@ -863,7 +865,8 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) } =20 static int scp_rproc_init(struct platform_device *pdev, - struct mtk_scp_of_regs *of_regs) + struct mtk_scp_of_regs *of_regs, + const struct mtk_scp_of_data *of_data) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; @@ -884,7 +887,7 @@ static int scp_rproc_init(struct platform_device *pdev, scp =3D (struct mtk_scp *)rproc->priv; scp->rproc =3D rproc; scp->dev =3D dev; - scp->data =3D of_device_get_match_data(dev); + scp->data =3D of_data; platform_set_drvdata(pdev, scp); =20 scp->reg_base =3D of_regs->reg_base; @@ -934,10 +937,6 @@ static int scp_rproc_init(struct platform_device *pdev, goto remove_subdev; } =20 - ret =3D rproc_add(rproc); - if (ret) - goto remove_subdev; - return 0; =20 remove_subdev: @@ -952,6 +951,109 @@ static int scp_rproc_init(struct platform_device *pde= v, return ret; } =20 +static void scp_rproc_free(struct mtk_scp *scp) +{ + int i; + + scp_remove_rpmsg_subdev(scp); + scp_ipi_unregister(scp, SCP_IPI_INIT); + scp_unmap_memory_region(scp); + for (i =3D 0; i < SCP_IPI_MAX; i++) + mutex_destroy(&scp->ipi_desc[i].lock); + mutex_destroy(&scp->send_lock); +} + +static int scp_cluster_init(struct platform_device *pdev, + struct mtk_scp_of_regs *of_regs) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev_of_node(dev); + struct platform_device *cpdev; + struct device_node *child; + const struct mtk_scp_of_data **cluster_of_data; + struct list_head *cluster =3D &cluster_cores; + struct mtk_scp *scp, *temp; + int core_id =3D 0, num_cores; + int ret; + + child =3D of_get_next_available_child(np, NULL); + if (!child) + return dev_err_probe(dev, -ENODEV, "No child node\n"); + + of_node_put(child); + if (of_node_name_eq(child, "cros-ec-rpmsg")) { + dev_dbg(dev, "single-core scp\n"); + + ret =3D scp_rproc_init(pdev, of_regs, of_device_get_match_data(dev)); + if (ret) + return dev_err_probe(dev, ret, "Failed to initialize single-core scp\n"= ); + + /* the single-core drvdata is intended to be the mtk_scp object. + * the mtk_scp object is used by APIs in mtk_scp_rpmsg_info. + */ + scp =3D platform_get_drvdata(pdev); + list_add_tail(&scp->elem, cluster); + scp->cluster =3D cluster; + } else { + dev_dbg(dev, "multi-core scp\n"); + + cluster_of_data =3D (const struct mtk_scp_of_data **)of_device_get_match= _data(dev); + + num_cores =3D of_get_available_child_count(np); + + for_each_available_child_of_node(np, child) { + if (core_id >=3D num_cores || !cluster_of_data[core_id]) { + ret =3D -EINVAL; + dev_err(dev, "Not support core %d\n", core_id); + of_node_put(child); + goto init_fail; + } + + cpdev =3D of_find_device_by_node(child); + if (!cpdev) { + ret =3D -ENODEV; + dev_err(dev, "Not found platform device for core %d\n", core_id); + of_node_put(child); + goto init_fail; + } + + ret =3D scp_rproc_init(cpdev, of_regs, cluster_of_data[core_id]); + if (ret) { + dev_err(dev, "Failed to initialize core %d rproc\n", core_id); + put_device(&cpdev->dev); + of_node_put(child); + goto init_fail; + } + scp =3D platform_get_drvdata(cpdev); + list_add_tail(&scp->elem, cluster); + scp->cluster =3D cluster; + put_device(&cpdev->dev); + + core_id++; + } + } + + list_for_each_entry_safe_reverse(scp, temp, cluster, elem) { + ret =3D rproc_add(scp->rproc); + if (ret) + goto add_fail; + } + + return 0; + +add_fail: + list_for_each_entry_continue(scp, cluster, elem) { + rproc_del(scp->rproc); + } +init_fail: + list_for_each_entry_safe_reverse(scp, temp, cluster, elem) { + list_del(&scp->elem); + scp_rproc_free(scp); + } + + return ret; +} + static int scp_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -980,21 +1082,30 @@ static int scp_probe(struct platform_device *pdev) scp_regs.l1tcm_phys =3D res->start; } =20 - return scp_rproc_init(pdev, &scp_regs); + ret =3D devm_of_platform_populate(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to populate platform devices\n"); + + INIT_LIST_HEAD(&cluster_cores); + platform_set_drvdata(pdev, &cluster_cores); + + ret =3D scp_cluster_init(pdev, &scp_regs); + if (ret) + return dev_err_probe(dev, ret, "Failed to initialize scp cluster\n"); + + return 0; } =20 static int scp_remove(struct platform_device *pdev) { - struct mtk_scp *scp =3D platform_get_drvdata(pdev); - int i; + struct list_head *cluster =3D &cluster_cores; + struct mtk_scp *scp, *temp; =20 - rproc_del(scp->rproc); - scp_remove_rpmsg_subdev(scp); - scp_ipi_unregister(scp, SCP_IPI_INIT); - scp_unmap_memory_region(scp); - for (i =3D 0; i < SCP_IPI_MAX; i++) - mutex_destroy(&scp->ipi_desc[i].lock); - mutex_destroy(&scp->send_lock); + list_for_each_entry_safe_reverse(scp, temp, cluster, elem) { + list_del(&scp->elem); + rproc_del(scp->rproc); + scp_rproc_free(scp); + } =20 return 0; } @@ -1073,12 +1184,19 @@ static const struct mtk_scp_of_data mt8195_of_data_= c1 =3D { .host_to_scp_int_bit =3D MT8195_CORE1_HOST_IPC_INT_BIT, }; =20 +static const struct mtk_scp_of_data *mt8195_of_data_cores[] =3D { + &mt8195_of_data, + &mt8195_of_data_c1, + NULL +}; + static const struct of_device_id mtk_scp_of_match[] =3D { { .compatible =3D "mediatek,mt8183-scp", .data =3D &mt8183_of_data }, { .compatible =3D "mediatek,mt8186-scp", .data =3D &mt8186_of_data }, { .compatible =3D "mediatek,mt8188-scp", .data =3D &mt8188_of_data }, { .compatible =3D "mediatek,mt8192-scp", .data =3D &mt8192_of_data }, { .compatible =3D "mediatek,mt8195-scp", .data =3D &mt8195_of_data }, + { .compatible =3D "mediatek,mt8195-scp-dual", .data =3D &mt8195_of_data_c= ores }, {}, }; MODULE_DEVICE_TABLE(of, mtk_scp_of_match); --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 154C7C77B6E for ; Tue, 28 Mar 2023 02:28:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232699AbjC1C2X (ORCPT ); Mon, 27 Mar 2023 22:28:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232536AbjC1C2K (ORCPT ); Mon, 27 Mar 2023 22:28:10 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFE47196; Mon, 27 Mar 2023 19:28:04 -0700 (PDT) X-UUID: 26742d66cd1011edb6b9f13eb10bd0fe-20230328 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:55 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 07/11] remoteproc: mediatek: Control SCP core 1 by rproc subdevice Date: Tue, 28 Mar 2023 10:27:29 +0800 Message-ID: <20230328022733.29910-8-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register SCP core 1 as a subdevice of core 0 for the boot sequence and watchdog timeout handling. The core 1 has to boot after core 0 because the SCP clock and SRAM power is controlled by SCP core 0. As for watchdog timeout handling, the remoteproc framework helps to stop/start subdevices automatically when SCP driver receives watchdog timeout event. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 9 +++++ drivers/remoteproc/mtk_scp.c | 66 +++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index b73b60c22ea1..f1a021ad7f66 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -100,6 +100,13 @@ struct mtk_scp_of_data { size_t ipi_buf_offset; }; =20 +struct mtk_scp_core_subdev { + struct rproc_subdev subdev; + struct mtk_scp *scp; +}; + +#define to_core_subdev(d) container_of(d, struct mtk_scp_core_subdev, subd= ev) + struct mtk_scp { struct device *dev; struct rproc *rproc; @@ -131,6 +138,8 @@ struct mtk_scp { =20 struct list_head elem; struct list_head *cluster; + + struct mtk_scp_core_subdev *core_subdev; }; =20 /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 71882ed31e16..ba931d550c1e 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -864,6 +864,60 @@ static void scp_remove_rpmsg_subdev(struct mtk_scp *sc= p) } } =20 +static int scp_core_subdev_start(struct rproc_subdev *subdev) +{ + struct mtk_scp_core_subdev *core_subdev =3D to_core_subdev(subdev); + struct mtk_scp *scp =3D core_subdev->scp; + + rproc_boot(scp->rproc); + + return 0; +} + +static void scp_core_subdev_stop(struct rproc_subdev *subdev, bool crashed) +{ + struct mtk_scp_core_subdev *core_subdev =3D to_core_subdev(subdev); + struct mtk_scp *scp =3D core_subdev->scp; + + rproc_shutdown(scp->rproc); +} + +static int scp_core_subdev_register(struct mtk_scp *scp) +{ + struct device *dev =3D scp->dev; + struct mtk_scp_core_subdev *core_subdev; + struct mtk_scp *scp_c0; + + scp_c0 =3D list_first_entry(scp->cluster, struct mtk_scp, elem); + if (!scp_c0) + return -ENODATA; + + core_subdev =3D devm_kzalloc(dev, sizeof(*core_subdev), GFP_KERNEL); + if (!core_subdev) + return -ENOMEM; + + core_subdev->scp =3D scp; + core_subdev->subdev.start =3D scp_core_subdev_start; + core_subdev->subdev.stop =3D scp_core_subdev_stop; + + scp->core_subdev =3D core_subdev; + rproc_add_subdev(scp_c0->rproc, &scp->core_subdev->subdev); + + return 0; +} + +static void scp_core_subdev_unregister(struct mtk_scp *scp) +{ + struct mtk_scp *scp_c0; + + if (scp->core_subdev) { + scp_c0 =3D list_first_entry(scp->cluster, struct mtk_scp, elem); + rproc_remove_subdev(scp_c0->rproc, &scp->core_subdev->subdev); + devm_kfree(scp->dev, scp->core_subdev); + scp->core_subdev =3D NULL; + } +} + static int scp_rproc_init(struct platform_device *pdev, struct mtk_scp_of_regs *of_regs, const struct mtk_scp_of_data *of_data) @@ -955,6 +1009,7 @@ static void scp_rproc_free(struct mtk_scp *scp) { int i; =20 + scp_core_subdev_unregister(scp); scp_remove_rpmsg_subdev(scp); scp_ipi_unregister(scp, SCP_IPI_INIT); scp_unmap_memory_region(scp); @@ -1034,6 +1089,17 @@ static int scp_cluster_init(struct platform_device *= pdev, } =20 list_for_each_entry_safe_reverse(scp, temp, cluster, elem) { + if (!list_is_first(&scp->elem, cluster)) { + ret =3D scp_core_subdev_register(scp); + if (ret) { + dev_err_probe(scp->dev, ret, "Failed to register as subdev\n"); + goto add_fail; + } + + /* sub cores are booted as subdevices of core 0 */ + scp->rproc->auto_boot =3D false; + } + ret =3D rproc_add(scp->rproc); if (ret) goto add_fail; --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA13EC76195 for ; Tue, 28 Mar 2023 02:28:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232723AbjC1C2s (ORCPT ); Mon, 27 Mar 2023 22:28:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232630AbjC1C2O (ORCPT ); Mon, 27 Mar 2023 22:28:14 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A148026B7; Mon, 27 Mar 2023 19:28:11 -0700 (PDT) X-UUID: 26765320cd1011edb6b9f13eb10bd0fe-20230328 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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charset="utf-8" Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and have the same viewpoint of SRAM, SCP has a "core 1 SRAM offset" configuration to control the access destination of SCP core 1 to boot core 1 from different SRAM location. The "core 1 SRAM offset" configuration is composed by a range and an offset. It works like a simple memory mapped mechanism. When SCP core 1 accesses a SRAM address located in the range, the SCP bus adds the configured offset to the address to shift the physical destination address on SCP SRAM. This shifting is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 7 +++++++ drivers/remoteproc/mtk_scp.c | 27 +++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index f1a021ad7f66..6861543a0825 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -65,6 +65,13 @@ #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 #define MT8195_CORE1_WDT_CFG 0x20034 =20 +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 =20 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index ba931d550c1e..f74ee80838e9 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -486,6 +486,9 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) =20 static int mt8195_scp_c1_before_load(struct mtk_scp *scp) { + u32 sec_ctrl; + struct mtk_scp *scp_c0; + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); =20 /* hold SCP in reset while loading FW. */ @@ -494,6 +497,30 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *s= cp) /* enable MPU for all memory regions */ writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); =20 + /* + * The L2TCM_OFFSET_RANGE and L2TCM_OFFSET shift the destination address + * on SRAM when SCP core 1 accesses SRAM. + * + * This configuration solves booting the SCP core 0 and core 1 from + * different SRAM address because core 0 and core 1 both boot from + * the head of SRAM by default. this must be configured before boot SCP c= ore 1. + * + * The value of L2TCM_OFFSET_RANGE is from the viewpoint of SCP core 1. + * When SCP core 1 issues address within the range (L2TCM_OFFSET_RANGE), + * the address will be added with a fixed offset (L2TCM_OFFSET) on the bu= s. + * The shift action is tranparent to software. + */ + writel(0, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH); + + scp_c0 =3D list_first_entry(scp->cluster, struct mtk_scp, elem); + writel(scp->sram_phys - scp_c0->sram_phys, scp->reg_base + MT8195_L2TCM_O= FFSET); + + /* enable SRAM offset when fetching instruction and data */ + sec_ctrl =3D readl(scp->reg_base + MT8195_SEC_CTRL); + sec_ctrl |=3D MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->reg_base + MT8195_SEC_CTRL); + return 0; } =20 --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 648F6C6FD1D for ; Tue, 28 Mar 2023 02:28:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232796AbjC1C2l (ORCPT ); Mon, 27 Mar 2023 22:28:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232617AbjC1C2N (ORCPT ); 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charset="utf-8" The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_common.h | 5 +++++ drivers/remoteproc/mtk_scp.c | 25 ++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_commo= n.h index 6861543a0825..1e148cbad0fb 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -55,6 +55,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 =20 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) =20 #define MT8195_CPU1_SRAM_PD 0x1084 @@ -63,6 +67,7 @@ #define MT8195_CORE1_SW_RSTN_CLR 0x20000 #define MT8195_CORE1_SW_RSTN_SET 0x20004 #define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 #define MT8195_CORE1_WDT_CFG 0x20034 =20 #define MT8195_SEC_CTRL 0x85000 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index f74ee80838e9..d08f21c1f947 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -231,6 +231,29 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } =20 +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host =3D readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + } else { + u32 reason =3D readl(scp->reg_base + MT8195_SYS_STATUS); + + if (reason & MT8195_CORE0_WDT) + writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); + + if (reason & MT8195_CORE1_WDT) + writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); + + scp_wdt_handler(scp, reason); + } + + writel(scp_to_host, scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); +} + static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -1256,7 +1279,7 @@ static const struct mtk_scp_of_data mt8192_of_data = =3D { static const struct mtk_scp_of_data mt8195_of_data =3D { .scp_clk_get =3D mt8195_scp_clk_get, .scp_before_load =3D mt8195_scp_before_load, - .scp_irq_handler =3D mt8192_scp_irq_handler, + .scp_irq_handler =3D mt8195_scp_irq_handler, .scp_reset_assert =3D mt8192_scp_reset_assert, .scp_reset_deassert =3D mt8192_scp_reset_deassert, .scp_stop =3D mt8195_scp_stop, --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2BD5C6FD1D for ; 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Tue, 28 Mar 2023 10:27:57 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:56 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 10/11] remoteproc: mediatek: Refine ipi handler error message Date: Tue, 28 Mar 2023 10:27:32 +0800 Message-ID: <20230328022733.29910-11-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The error message doesn't accurately reflect the cause of the error. The error is due to a handler not being found, not an invalid IPI ID. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- drivers/remoteproc/mtk_scp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d08f21c1f947..fec74631557a 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -115,7 +115,7 @@ static void scp_ipi_handler(struct mtk_scp *scp) scp_ipi_lock(scp, id); handler =3D ipi_desc[id].handler; if (!handler) { - dev_err(scp->dev, "No such ipi id =3D %d\n", id); + dev_err(scp->dev, "No handler for ipi id =3D %d\n", id); scp_ipi_unlock(scp, id); return; } --=20 2.18.0 From nobody Sat Sep 21 00:04:28 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7F6BC761A6 for ; Tue, 28 Mar 2023 02:28:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232646AbjC1C2Q (ORCPT ); Mon, 27 Mar 2023 22:28:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231976AbjC1C2I (ORCPT ); Mon, 27 Mar 2023 22:28:08 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77F6119A9; Mon, 27 Mar 2023 19:28:03 -0700 (PDT) X-UUID: 26b7ce90cd1011eda9a90f0bb45854f4-20230328 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=da8xtj3GEK5PCXWnakDtGHNuxmDl0f1XqfPRmZJ45xk=; b=MxtvDsih3SE9tRK/C5yeiagliwpFHG07AIKTGqs0ErAZmZsua/nJI69Oz8Pplk12sOxbd0LRQgfb2HP+h3dBwb5Yf+aKyw5RB0KDDDB1gTVMP2I83P/XLfpvmCP2uNmE45m/E0fAZbBugoKLdQIla2MF8D31gd9zuqYVI8mG+rs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:7cc04742-36b0-4118-a6d8-fce49b49cd4f,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22,REQID:7cc04742-36b0-4118-a6d8-fce49b49cd4f,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c,CLOUDID:96e98db4-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230328102759ICX4TM7P,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 26b7ce90cd1011eda9a90f0bb45854f4-20230328 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 722749702; Tue, 28 Mar 2023 10:27:57 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Tue, 28 Mar 2023 10:27:56 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Tue, 28 Mar 2023 10:27:56 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen CC: , , , , , Subject: [PATCH v9 11/11] arm64: dts: mediatek: mt8195: Add SCP 2nd core Date: Tue, 28 Mar 2023 10:27:33 +0800 Message-ID: <20230328022733.29910-12-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230328022733.29910-1-tinghan.shen@mediatek.com> References: <20230328022733.29910-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rewrite the MT8195 SCP device node as a cluster and add the SCP 2nd core in it. Since the SCP device node is changed to multi-core structure, enable SCP cluster to enable probing SCP core 0. Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 6 +++- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 32 ++++++++++++++----- 2 files changed, 29 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/b= oot/dts/mediatek/mt8195-cherry.dtsi index 56749cfe7c33..31415d71b6a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -933,7 +933,11 @@ interrupts-extended =3D <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; =20 -&scp { +&scp_cluster { + status =3D "okay"; +}; + +&scp_c0 { status =3D "okay"; =20 firmware-name =3D "mediatek/mt8195/scp.img"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 8fc527570791..5fe5fb32261e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -826,14 +826,30 @@ clocks =3D <&infracfg_ao CLK_INFRA_AO_GCE2>; }; =20 - scp: scp@10500000 { - compatible =3D "mediatek,mt8195-scp"; - reg =3D <0 0x10500000 0 0x100000>, - <0 0x10720000 0 0xe0000>, - <0 0x10700000 0 0x8000>; - reg-names =3D "sram", "cfg", "l1tcm"; - interrupts =3D ; + scp_cluster: scp@10500000 { + compatible =3D "mediatek,mt8195-scp-dual"; + reg =3D <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>; + reg-names =3D "cfg", "l1tcm"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0 0x10500000 0x100000>; status =3D "disabled"; + + scp_c0: scp@0 { + compatible =3D "mediatek,scp-core"; + reg =3D <0x0 0xa0000>; + reg-names =3D "sram"; + interrupts =3D ; + status =3D "disabled"; + }; + + scp_c1: scp@a0000 { + compatible =3D "mediatek,scp-core"; + reg =3D <0xa0000 0x20000>; + reg-names =3D "sram"; + interrupts =3D ; + status =3D "disabled"; + }; }; =20 scp_adsp: clock-controller@10720000 { @@ -2309,7 +2325,7 @@ <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; interrupts =3D ; - mediatek,scp =3D <&scp>; + mediatek,scp =3D <&scp_c0>; clocks =3D <&vencsys CLK_VENC_VENC>; clock-names =3D "venc_sel"; assigned-clocks =3D <&topckgen CLK_TOP_VENC>; --=20 2.18.0