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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id mb22-20020a170906eb1600b009fc0c42098csm5855150ejb.173.2023.11.27.07.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:52:31 -0800 (PST) From: Konrad Dybcio Date: Mon, 27 Nov 2023 16:52:12 +0100 Subject: [PATCH v7 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230328-topic-msgram_mpm-v7-1-6ee2bfeaac2c@linaro.org> References: <20230328-topic-msgram_mpm-v7-0-6ee2bfeaac2c@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v7-0-6ee2bfeaac2c@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1701100347; l=3285; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UnAJ2EWA9JR18tWPDeobMem6WcpQTcTZkHcMBc8DA5o=; b=6hyNFuljkC0LUFiRqT23DUyz8Mhfre8bXxB7IXiD5VbX/ZqGXggcwRPETj6PbbKE0naEU5tQV pzzAeZ5fIZVC3JF8oeSLTD8o3hEgLRxtDLGu96oOQmgRNVbwiEa7YTR X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/interrupt-controller/qcom,mpm.yaml | 52 +++++++++++++++---= ---- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mp= m.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.ya= ml index 509d20c091af..4ce7912d8047 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM =20 interrupts: maxItems: 1 @@ -64,33 +70,45 @@ properties: =20 required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram =20 additionalProperties: false =20 examples: - | #include - mpm: interrupt-controller@45f01b8 { - compatible =3D "qcom,mpm"; - interrupts =3D ; - reg =3D <0x45f01b8 0x1000>; - mboxes =3D <&apcs_glb 1>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupt-parent =3D <&intc>; - qcom,mpm-pin-count =3D <96>; - qcom,mpm-pin-map =3D <2 275>, - <5 296>, - <12 422>, - <24 79>, - <86 183>, - <90 260>, - <91 260>; + + remoteproc-rpm { + compatible =3D "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible =3D "qcom,glink-rpm"; + + interrupts =3D ; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + mboxes =3D <&apcs_glb 0>; + }; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <96>; + qcom,mpm-pin-map =3D <2 275>, + <5 296>, + <12 422>, + <24 79>, + <86 183>, + <91 260>; + }; }; --=20 2.43.0