From nobody Wed Dec 17 13:54:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FDCBC4167B for ; Sat, 25 Nov 2023 14:27:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229569AbjKYO1P (ORCPT ); Sat, 25 Nov 2023 09:27:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232062AbjKYO1K (ORCPT ); Sat, 25 Nov 2023 09:27:10 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8688DB0 for ; Sat, 25 Nov 2023 06:27:16 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-a02d91ab199so387453066b.0 for ; Sat, 25 Nov 2023 06:27:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700922435; x=1701527235; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=47QyN1mARPQG0EF8lxrYb1VJmjeAmYEb6KvC/0GnTPA=; b=pBEkKGjiuwf9VEoHu490nlCZBjOBjDyL04flWWAhWC7bykcoeilUd28oOHCwAkaYKQ OgkSmg7UrsYe11h2n8e3Q6C2tVsOvlUEC+38tD51adMzAU27piFeWaoQZTo+wB1vAjxf JZnYk55hlsK8OQkuR5tKJRpTCWlqpJrb/Kpuy0GScjSn0szJJ93RG+634NuYRt3av1QW CS9KoRVE1n2mifXMB/O/A+T4cRkcGd0w3IlxVwIzi+R10l7I0hyOvF5G/d6Yu2E4XJKv O8quX7//8PmIp4qsDGcnhreANSdYYqZETX6yYN7fDM+vvHlydQoI7wjB46hOC88nE59D cg1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700922435; x=1701527235; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=47QyN1mARPQG0EF8lxrYb1VJmjeAmYEb6KvC/0GnTPA=; b=Sm46+1s51vx/YqIXQNfV+g1J3GABYhR3Wy+WayHHIsvyv11jkg2tnDPFec2dHhTkim 8cAHoj6EYCzulkS71ti1rp4JFWPr2GhLIpD42wcmXY8rpGPILCPkxYDktbWilzZlc2yH IdI0+4+8Q+NSdj2Yx99HTKaitrvuVARdeyOZjrMqnIaNlWQ557yERPesHWd6y4kI8G5F TPcyOGbUFxAUb5yt5C1gkbxpfH640cPBeK9PG19uZ6cV92DWespl5a5fvrJ3TcYCAfCL rDDyBnsrNz5x0a/YF0/P5K+PietBywz/N9uWBu4p4lh3v8vARizWDI3W4Mp+F3Wek2V7 4AjQ== X-Gm-Message-State: AOJu0YxPi70mlt7+LDrJTNZFzEhtoZA0+Q/wzNH8TzEofDmmj72WNbtB ZxcWtjQ6N1Kx/mvIwoSsuiUZjQ== X-Google-Smtp-Source: AGHT+IHXS1ts9rv22L6h9UkqSrfCjVQbW88nYZhMcmkD3NegVS+kQ/9FMcjMzB0/6/ofi/zH1Sa7HA== X-Received: by 2002:a17:906:5950:b0:9bf:60f9:9b7c with SMTP id g16-20020a170906595000b009bf60f99b7cmr4361155ejr.62.1700922435080; Sat, 25 Nov 2023 06:27:15 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id cb8-20020a170906a44800b009fd4583851esm3569253ejb.178.2023.11.25.06.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:27:14 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:27:03 +0100 Subject: [PATCH v6 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230328-topic-msgram_mpm-v6-1-682e4855b7e2@linaro.org> References: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700922431; l=3285; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=UnAJ2EWA9JR18tWPDeobMem6WcpQTcTZkHcMBc8DA5o=; b=2NrJMi4Wx+FGVOzYyLITnbX5suwHJ1qk4x1+EdNB/0gWA9Tu7x8Maq1745tzQFYNIqkSBMs8m vcFVDVq+keCDu6x+TGKskBrfJ3kSUJoxOxM+B7HB/BZ3m3sBIZRhsJC X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/interrupt-controller/qcom,mpm.yaml | 52 +++++++++++++++---= ---- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mp= m.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.ya= ml index 509d20c091af..4ce7912d8047 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM =20 interrupts: maxItems: 1 @@ -64,33 +70,45 @@ properties: =20 required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram =20 additionalProperties: false =20 examples: - | #include - mpm: interrupt-controller@45f01b8 { - compatible =3D "qcom,mpm"; - interrupts =3D ; - reg =3D <0x45f01b8 0x1000>; - mboxes =3D <&apcs_glb 1>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupt-parent =3D <&intc>; - qcom,mpm-pin-count =3D <96>; - qcom,mpm-pin-map =3D <2 275>, - <5 296>, - <12 422>, - <24 79>, - <86 183>, - <90 260>, - <91 260>; + + remoteproc-rpm { + compatible =3D "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible =3D "qcom,glink-rpm"; + + interrupts =3D ; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + mboxes =3D <&apcs_glb 0>; + }; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <96>; + qcom,mpm-pin-map =3D <2 275>, + <5 296>, + <12 422>, + <24 79>, + <86 183>, + <91 260>; + }; }; --=20 2.43.0 From nobody Wed Dec 17 13:54:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53B93C46CA0 for ; Sat, 25 Nov 2023 14:27:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232211AbjKYO1R (ORCPT ); Sat, 25 Nov 2023 09:27:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232017AbjKYO1M (ORCPT ); Sat, 25 Nov 2023 09:27:12 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8918BB0 for ; Sat, 25 Nov 2023 06:27:18 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2c87acba73bso36986171fa.1 for ; Sat, 25 Nov 2023 06:27:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700922437; x=1701527237; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IjrMx0Y9XqGbeFGv2v7KF3vpFk6Af7SmrHYjsceKUcc=; b=nMSIOCap7eRtNRKAftq68BVAYtwGVTsfBXmqPy9RDILKMmNIJY5fER2N9Crr61Cp8E oFvNPF6FaZjr97/MOuvNF8jTW0EGx4Diw2YbnbKOvoBkk1dI7HmuvXZuaDSIitO3SAHo 0SXhUDvMm/mvlYI37hGF1gj6sYvNrtX/8oD2bFwPcHotHNThHoO2mHY8n3gS4pdKGf63 2ejPYdv5+POuh+x/7jShwCyPDjG6wiC9ANdnT+Wx5bxZDXFaqTOKUvKNdoorK5CNHQfz ZeQURHlnqoYRUE8dODLxlvWtHVS4QBtdnv8Cs6r4f3gNr1LOEKr8yigwUCtntwq/14Az y6mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700922437; x=1701527237; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IjrMx0Y9XqGbeFGv2v7KF3vpFk6Af7SmrHYjsceKUcc=; b=OnkGyqTmkPHUuUbll2qPjTIWVbcXGVTM+lJ2P1v3/o1yvb/O2eOK3lcnKVJBvIT0of GXVykBv6HEjVGpF8ahO/ipDjZGb07KB2J50ArNFLu8M/h34b5ykBcUDXetwwaQq3GWRG T3kpKUSio2os5g+/0IfcqrWeKIXvoElWgdeQiBFoXktRlsq37XtZS9iBQfodooUdLTtU EacrsKbDoxMKgXx80S1EUO0cqSkjObcqXjZuUYmjcobgY2u6O5l+ciBFetLMpzyiwzo2 VDPB+dxZfwK8fQyMuQM7vHePsfIFn/S7H8cjKD5a9tWnWocpwBYRuNIIjbt95/08Ouja 1zIQ== X-Gm-Message-State: AOJu0YyBb8wiL/pExn8ezvuz0t3WwqelOOlTzLxF7AXNVUB7jb76bDow gMmRS3PxY+EwR1Fj39CgwEm9Hu84R+lqki5Vyls= X-Google-Smtp-Source: AGHT+IEAtacX1rpj46KJsE7MAgE0rYdmvPIBb99+gIuObi2T5Uo92sjkL5+CgdTJt5Nze6GB+GMY9Q== X-Received: by 2002:a2e:9d4e:0:b0:2b9:4b2e:5420 with SMTP id y14-20020a2e9d4e000000b002b94b2e5420mr4192424ljj.52.1700922436912; Sat, 25 Nov 2023 06:27:16 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id cb8-20020a170906a44800b009fd4583851esm3569253ejb.178.2023.11.25.06.27.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:27:16 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 15:27:04 +0100 Subject: [PATCH v6 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230328-topic-msgram_mpm-v6-2-682e4855b7e2@linaro.org> References: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v6-0-682e4855b7e2@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700922431; l=2753; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=C9jl/qWAOl6wjNdLIwtjlGydPzEtEemM1AEix/NRi+g=; b=QtoC2BFtU8WEQA3FaUGzzwenP8GqsgZoAjavep58j+7Xe7xYs8nBar2m2me6Rpy4DsIoa0wF3 Rm4t4mZXOxaC1SKmjd726QWQTfffqWQ1f0bR+GNiVeYGNpXTX11V9zK X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Acked-by: Shawn Guo Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue --- drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 7124565234a5..7115e3056aa5 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struc= t device_node *parent) struct device *dev =3D &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; =20 @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struc= t device_node *parent) =20 raw_spin_lock_init(&priv->lock); =20 - priv->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np =3D of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret =3D of_address_to_resource(msgram_np, 0, &res); + /* Don't use devm_ioremap_resource, as we're accessing a shared region. = */ + priv->base =3D devm_ioremap(dev, res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } =20 for (i =3D 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0); --=20 2.43.0