From nobody Wed Dec 17 05:47:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7E6CEE49B2 for ; Wed, 23 Aug 2023 11:15:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234385AbjHWLPo (ORCPT ); Wed, 23 Aug 2023 07:15:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232113AbjHWLPl (ORCPT ); Wed, 23 Aug 2023 07:15:41 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18EF8E52 for ; Wed, 23 Aug 2023 04:15:36 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2bbad32bc79so91942911fa.0 for ; Wed, 23 Aug 2023 04:15:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692789334; x=1693394134; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6jKJ9K8AESLKQZ+HE5HtynW9aPvpkrDN9h2vHMA4KaM=; b=TRF/DSn+3kfBHUd+H6144IL3A/Usj38y4AMqzr1lEHnlB6j4WAz2Slq6fQY63MkaB5 zaYVQGjsfPlgC0RmUXrhX38srlMt5mPWG6RypFk64MCxvB+P5nAYrfjlVv/eVYtBfGo8 iHs7mzYFAgtT/Y0Jva0pNwEHxBWdOo7GL3NZHX87/vr+0vFSmshV/dXJHPuqAgCvtK2z xfLhRgReYd2TfzWUeAQNfxQqdKITgta5+0NJ9ztTw5Yghqz2msCWH0+SrJUWWJdbYWC+ ikxWScIr8K5hUOcr0ksUGBNTrjFCU5P71d6xeJn6mLdezsUdEQavSGBwYMrtd/MipwRj USEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692789334; x=1693394134; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6jKJ9K8AESLKQZ+HE5HtynW9aPvpkrDN9h2vHMA4KaM=; b=d37VARgYIshbb04FAd3cXgrXPvfnrQa7NPYj7nAoCBfLI67IyF22YVAyJTnUj695wR tVPBL1GVwMoNN6AvtPC9Sk7T3fimu8rLPJ+OTYDn7pCiduNyNX0qA/+xemAlB5frECE9 6r9KJzaAOA/b4VefbITiNKYEPSWWXNHgK7Tj05LfAcwwI9HPeBGKb8knZ3yl3bs8hHmh mR1avB2xxF4vl4J1/O7ZXj8iXDHI/5hQI2oCXKYgfkyRuHuCpZQ5+1hh5JVJYZstGs0m MuiecYp/S43tTihcstGcVWar/ShYwJgsJyV2ZszmdEsg3/gLMu26J3lWfF8REJeZg3oK k66A== X-Gm-Message-State: AOJu0YzDiaAc66RUKCMQs4GFPV20wx0I6HTY6dI+x4xwuH5aD3t5B7OP iCkxv4u6vteoD35MYcpcFcre/w== X-Google-Smtp-Source: AGHT+IHvIgWzyNGDBNZE9SU75RNUPt3W4F5eihUdjUz0iWSRB7x2+YYoa9SCs9v50tbbSREroE9/ow== X-Received: by 2002:a2e:8957:0:b0:2b6:e2c1:6cdb with SMTP id b23-20020a2e8957000000b002b6e2c16cdbmr10018545ljk.51.1692789334347; Wed, 23 Aug 2023 04:15:34 -0700 (PDT) Received: from [192.168.1.101] (abyj76.neoplus.adsl.tpnet.pl. [83.9.29.76]) by smtp.gmail.com with ESMTPSA id r16-20020a2e80d0000000b002b6ffa50896sm3148981ljg.128.2023.08.23.04.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Aug 2023 04:15:34 -0700 (PDT) From: Konrad Dybcio Date: Wed, 23 Aug 2023 13:15:31 +0200 Subject: [PATCH v5 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230328-topic-msgram_mpm-v5-1-6e06278896b5@linaro.org> References: <20230328-topic-msgram_mpm-v5-0-6e06278896b5@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v5-0-6e06278896b5@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1692789331; l=3285; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=cKEWZHOdaJ0wddQhFxCKdERpAsyn+1yKkVogcTKhfXI=; b=iI2hCEU50BlnJX8oKl2wrCEysvxSGrPrns2J0qqmvRJn+hy7uq4TkYQL4Rl5Rz65AzFJ5nbWf Pzr/TYspFt2BPu1fZxzm8pibg2UEuwMMuo+cgxnmBE6Yd6QEy3MAAdS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Due to the wild nature of the Qualcomm RPM Message RAM, we can't really use 'reg' to point to the MPM's slice of Message RAM without cutting into an already-defined RPM MSG RAM node used for GLINK and SMEM. Document passing the register space as a slice of SRAM through the qcom,rpm-msg-ram property. This also makes 'reg' deprecated. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/interrupt-controller/qcom,mpm.yaml | 52 +++++++++++++++---= ---- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mp= m.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.ya= ml index 509d20c091af..4ce7912d8047 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -29,6 +29,12 @@ properties: maxItems: 1 description: Specifies the base address and size of vMPM registers in RPM MSG RAM. + deprecated: true + + qcom,rpm-msg-ram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the APSS MPM slice of the RPM Message RAM =20 interrupts: maxItems: 1 @@ -64,33 +70,45 @@ properties: =20 required: - compatible - - reg - interrupts - mboxes - interrupt-controller - '#interrupt-cells' - qcom,mpm-pin-count - qcom,mpm-pin-map + - qcom,rpm-msg-ram =20 additionalProperties: false =20 examples: - | #include - mpm: interrupt-controller@45f01b8 { - compatible =3D "qcom,mpm"; - interrupts =3D ; - reg =3D <0x45f01b8 0x1000>; - mboxes =3D <&apcs_glb 1>; - interrupt-controller; - #interrupt-cells =3D <2>; - interrupt-parent =3D <&intc>; - qcom,mpm-pin-count =3D <96>; - qcom,mpm-pin-map =3D <2 275>, - <5 296>, - <12 422>, - <24 79>, - <86 183>, - <90 260>, - <91 260>; + + remoteproc-rpm { + compatible =3D "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible =3D "qcom,glink-rpm"; + + interrupts =3D ; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + mboxes =3D <&apcs_glb 0>; + }; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <96>; + qcom,mpm-pin-map =3D <2 275>, + <5 296>, + <12 422>, + <24 79>, + <86 183>, + <91 260>; + }; }; --=20 2.42.0 From nobody Wed Dec 17 05:47:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3243EE4993 for ; Wed, 23 Aug 2023 11:15:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234401AbjHWLPs (ORCPT ); Wed, 23 Aug 2023 07:15:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234377AbjHWLPm (ORCPT ); Wed, 23 Aug 2023 07:15:42 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FB01E5E for ; Wed, 23 Aug 2023 04:15:37 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2bcc331f942so31035251fa.0 for ; Wed, 23 Aug 2023 04:15:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692789336; x=1693394136; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=JNv+5xba7bQvgA4+gEPjq5lTLo/u23dfY/H3jr3xdrI=; b=xUzJki82mPaUSdzILbTtZrc1drg0uKB2Bx0NRh4kQWyDhaCyv234ZLtxWntJhf9YSv ZJuNB/pht9eGn3JSq5tVspJEqlPoSgoDn3+hFNvqqtQ79o3vwz4leJqinbxhtaPi2L3U rRxy/X7FfbV+soEXiN1/wVI4u74I7SUrmQn0XtQZk+VEnuhpPgFjjpDi8WEjfkZHGqRM SdzflCv8H7wimEu2fxicM6EC+CDlpaVP0JHxzYrcuCd8X+neVTlBBabUimV+DKnMuP3r mYzAxX7UNO9VC2kBPKylDJdJQoUcQNFGfIjZM6rIuRQmOIlnZugvZZ08iL2iUrBLaj9Z oXAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692789336; x=1693394136; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JNv+5xba7bQvgA4+gEPjq5lTLo/u23dfY/H3jr3xdrI=; b=JpX2dLDL+C6CDKCQUdC6Gl9EDAM98yAqHP3PxyJrQU03bIH3wj/pmFYDbqs32sAZ9j FdYYRjWGJ1CRj1mIwolcRGToA3UGmIDBunIKh82igjTjYqhfuEvNICd7nsQ2AF4YL906 /SGrM//MFsRzL+ra98o/E+OALh1z5QD2PlQp1o+BZyMwv3zjtjOSaW2IMXdi0COv+pem OJqEkO9jRKq3PdXW2keIt9OmE63dPY2nUgaaHwE/O818edg7ke5s3l2QiJzy8CtYQwtw 7Z4RZxeoDKGaObcS6snwo8xhx06DoXBCR3ESoB405tTy4WJPTWF3YIBxc/Ucwv9xISLQ qQjQ== X-Gm-Message-State: AOJu0YyEkPB5kDe+lFAHMkqru6n2gwD8vVE/bf9j+wqGeHOKLY5ynyas wLcMdKY1CFmq/YzsyWcul4ElJg== X-Google-Smtp-Source: AGHT+IG8lAbMM5ohYZn6mk9W6ZRXhs/cpY9GnJH3geEZYdfhndratqyX1N8s03nbbvhNV5eoaHZcjw== X-Received: by 2002:a2e:888f:0:b0:2b6:b7c3:bb89 with SMTP id k15-20020a2e888f000000b002b6b7c3bb89mr4648791lji.18.1692789335879; Wed, 23 Aug 2023 04:15:35 -0700 (PDT) Received: from [192.168.1.101] (abyj76.neoplus.adsl.tpnet.pl. [83.9.29.76]) by smtp.gmail.com with ESMTPSA id r16-20020a2e80d0000000b002b6ffa50896sm3148981ljg.128.2023.08.23.04.15.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Aug 2023 04:15:35 -0700 (PDT) From: Konrad Dybcio Date: Wed, 23 Aug 2023 13:15:32 +0200 Subject: [PATCH v5 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230328-topic-msgram_mpm-v5-2-6e06278896b5@linaro.org> References: <20230328-topic-msgram_mpm-v5-0-6e06278896b5@linaro.org> In-Reply-To: <20230328-topic-msgram_mpm-v5-0-6e06278896b5@linaro.org> To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1692789331; l=2753; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=N8kAAyqrJhi9Gyt3LBw8oYypb/cOn3Xx6lhFuH23rnM=; b=wTjEsfdqz/9ijpfPCzPdt03nXz+NrBq8sKaqU2cL0jOzaAtjXdG6WzdyZTAMrXjDFpX4M1ZdD vCFLQ8nj+wlAMAc9L0KVOjxEoNZito1tYxLO+6Qr179t9gRIPlaK0vu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MPM hardware is accessible to us from the ARM CPUs through a shared memory region (RPM MSG RAM) that's also concurrently accessed by other kinds of cores on the system (like modem, ADSP etc.). Modeling this relation in a (somewhat) sane manner in the device tree basically requires us to either present the MPM as a child of said memory region (which makes little sense, as a mapped memory carveout is not a bus), define nodes which bleed their register spaces into one another, or passing their slice of the MSG RAM through some kind of a property. Go with the third option and add a way to map a region passed through the "qcom,rpm-msg-ram" property as our register space. The current way of using 'reg' is preserved for ABI reasons. Acked-by: Shawn Guo Signed-off-by: Konrad Dybcio --- drivers/irqchip/irq-qcom-mpm.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 7124565234a5..7115e3056aa5 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -322,8 +323,10 @@ static int qcom_mpm_init(struct device_node *np, struc= t device_node *parent) struct device *dev =3D &pdev->dev; struct irq_domain *parent_domain; struct generic_pm_domain *genpd; + struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; + struct resource res; int i, irq; int ret; =20 @@ -374,9 +377,21 @@ static int qcom_mpm_init(struct device_node *np, struc= t device_node *parent) =20 raw_spin_lock_init(&priv->lock); =20 - priv->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + /* If we have a handle to an RPM message ram partition, use it. */ + msgram_np =3D of_parse_phandle(np, "qcom,rpm-msg-ram", 0); + if (msgram_np) { + ret =3D of_address_to_resource(msgram_np, 0, &res); + /* Don't use devm_ioremap_resource, as we're accessing a shared region. = */ + priv->base =3D devm_ioremap(dev, res.start, resource_size(&res)); + of_node_put(msgram_np); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } else { + /* Otherwise, fall back to simple MMIO. */ + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + } =20 for (i =3D 0; i < priv->reg_stride; i++) { qcom_mpm_write(priv, MPM_REG_ENABLE, i, 0); --=20 2.42.0