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([172.25.112.68]) by orsmga008.jf.intel.com with ESMTP; 27 Mar 2023 01:24:31 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com, jiangshanlai@gmail.com, shan.kang@intel.com Subject: [PATCH v6 06/33] x86/cpufeature: add the cpu feature bit for FRED Date: Mon, 27 Mar 2023 00:58:11 -0700 Message-Id: <20230327075838.5403-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230327075838.5403-1-xin3.li@intel.com> References: <20230327075838.5403-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Add the CPU feature bit for FRED (Flexible Return and Event Delivery). The Intel flexible return and event delivery (FRED) architecture defines si= mple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the following goals: 1) Improve overall performance and response time by replacing event delivery through the interrupt descriptor table (IDT event delivery) and event retur= n by the IRET instruction with lower latency transitions. 2) Improve software robustness by ensuring that event delivery establishes = the full supervisor context and that event return establishes the full user con= text. The new transitions defined by the FRED architecture are FRED event deliver= y and, for returning from events, two FRED return instructions. FRED event deliver= y can effect a transition from ring 3 to ring 0, but it is used also to deliver e= vents incident to ring 0. One FRED instruction (ERETU) effects a return from ring= 0 to ring 3, while the other (ERETS) returns while remaining in ring 0. Search for the latest FRED spec in most search engines with this search pat= tern: site:intel.com FRED (flexible return and event delivery) specification Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 73c9672c123b..1fa444478d33 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -318,6 +318,7 @@ #define X86_FEATURE_FZRM (12*32+10) /* "" Fast zero-length REP MOVSB */ #define X86_FEATURE_FSRS (12*32+11) /* "" Fast short REP STOSB */ #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery= */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMAD= D52[H,L]UQ */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index b89005819cd5..e9064f4a011a 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instruc= tions */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery= */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMAD= D52[H,L]UQ */ --=20 2.34.1