From nobody Mon Feb 9 05:58:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B298C7619A for ; Mon, 27 Mar 2023 07:43:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232711AbjC0Hni (ORCPT ); Mon, 27 Mar 2023 03:43:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232715AbjC0Hn1 (ORCPT ); Mon, 27 Mar 2023 03:43:27 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 316F71B8 for ; Mon, 27 Mar 2023 00:42:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1679902934; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=9gEvGzO/t3GSZzHhYPQWJ5afaAW4baouQV1YxDz4Oxo=; b=fKi8SaBZ1tGJJpYdX68NkToFQeOLb7pYT98a7h91SIRBk76HcBy1ho5fm1ibcglkW0HCXH bJoIMkq63TUcYgIo0ldN6NSrlarXv3KqqLhc/Pq/xELHY3eIywIG8j+qorVr4Xsz/3AByi VluL+TNiFYOaIdckqCuX/4rUut7nxX4= Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-126-z1iCFoUcM1uT9cCe6nqrhw-1; Mon, 27 Mar 2023 03:42:09 -0400 X-MC-Unique: z1iCFoUcM1uT9cCe6nqrhw-1 Received: by mail-wm1-f69.google.com with SMTP id bd16-20020a05600c1f1000b003ee895f6201so5250378wmb.9 for ; Mon, 27 Mar 2023 00:42:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679902928; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9gEvGzO/t3GSZzHhYPQWJ5afaAW4baouQV1YxDz4Oxo=; b=Nf7Xg4l/1Y+2c9ocr/3DOPCo5bPIIgpaAdaip4M/OWjAZlZa7H7R66v19lJWjTqQun DeCdd68Tz53IV9GZVdojZaZZusZDYsqLn9E4BJ7PmVsgeZLfPgHAWKe2lxiAAeZs+gww vmfpSfBc5OUXagXqdgr2WltkkHC2aaJ5P0HWlGO48JAMPRLHbMhGKmhDDkR4NRLK2nfP Gph9CRGZYvTrRoZ/W5tk4ap2S77Lkrh3lpwCccdY8RebqueHnjTbjP7HCLbf/MVjKsy8 zhr/5xUZXax+S0VljUAo0vdtjzyt3IaVBQGHEaWbSEPSvd4wTPpe1cPrsduNsUOgwCED pO2Q== X-Gm-Message-State: AO0yUKX73Je4g0J3xyp7jiEq13El/7HM9knHhu3YaWxaljYMj4AJ22uo KcFiX3VxC30s2koLfFZ4eCfHwDckJWSpAYG6WQcwVFsmQohGmS0S/a3Y6scxX5lS5TY/91FuFj5 okS6KXXLfZQQyFPRmTdOExoZexdjmn0hY1o+iCPHOxuhwfLAD0AzBT7hz7+mgba9uv54TO+vA00 eBDqP1bCQ= X-Received: by 2002:a05:600c:b42:b0:3ee:6cdf:c357 with SMTP id k2-20020a05600c0b4200b003ee6cdfc357mr7727996wmr.20.1679902928518; Mon, 27 Mar 2023 00:42:08 -0700 (PDT) X-Google-Smtp-Source: AK7set9/tMR3AjsxF/BVjZ53UH5flNgkScCgYAEe7XzL7RWa18N1EYtYJbvZivLJq7GDux7Kr9leMA== X-Received: by 2002:a05:600c:b42:b0:3ee:6cdf:c357 with SMTP id k2-20020a05600c0b4200b003ee6cdfc357mr7727965wmr.20.1679902928101; Mon, 27 Mar 2023 00:42:08 -0700 (PDT) Received: from minerva.home (205.pool92-176-231.dynamic.orange.es. [92.176.231.205]) by smtp.gmail.com with ESMTPSA id z8-20020a05600c0a0800b003edc4788fa0sm7902247wmp.2.2023.03.27.00.42.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 00:42:07 -0700 (PDT) From: Javier Martinez Canillas To: linux-kernel@vger.kernel.org Cc: Robert Mader , Laurent Pinchart , Peter Robinson , Jacopo Mondi , Ondrej Jirman , Martijn Braam , =?UTF-8?q?Kamil=20Trzci=C5=84ski?= , Javier Martinez Canillas , Caleb Connolly , Heiko Stuebner , Jarrah Gosbell , Krzysztof Kozlowski , Rob Herring , Tom Fitzhenry , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2] arm64: dts: rk3399-pinephone-pro: Add internal display support Date: Mon, 27 Mar 2023 09:41:35 +0200 Message-Id: <20230327074136.1459212-1-javierm@redhat.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ondrej Jirman The phone's display is using a Hannstar LCD panel. Support it by adding a panel DT node and all needed nodes (backlight, MIPI DSI, regulators, etc). Signed-off-by: Ondrej Jirman Co-developed-by: Martijn Braam Co-developed-by: Kamil Trzci=C5=84ski Signed-off-by: Javier Martinez Canillas Tested-by: Ondrej Jirman --- Changes in v2: - Drop touchscreen node because used the wrong compatible (Ondrej Jirman). - Fix assigned-clock-parents in vopb node (Ondrej Jirman). - Add vopl and vopl nodes. .../dts/rockchip/rk3399-pinephone-pro.dts | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/a= rm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index a0795a2b1cb1..5116f156d548 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -29,6 +29,12 @@ chosen { stdout-path =3D "serial2:115200n8"; }; =20 + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm0 0 1000000 0>; + pwm-delay-us =3D <10000>; + }; + gpio-keys { compatible =3D "gpio-keys"; pinctrl-names =3D "default"; @@ -102,6 +108,32 @@ wifi_pwrseq: sdio-wifi-pwrseq { /* WL_REG_ON on module */ reset-gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + + /* MIPI DSI panel 1.8v supply */ + vcc1v8_lcd: vcc1v8-lcd { + compatible =3D "regulator-fixed"; + enable-active-high; + regulator-name =3D "vcc1v8_lcd"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc3v3_sys>; + gpio =3D <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&display_pwren1>; + }; + + /* MIPI DSI panel 2.8v supply */ + vcc2v8_lcd: vcc2v8-lcd { + compatible =3D "regulator-fixed"; + enable-active-high; + regulator-name =3D "vcc2v8_lcd"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc3v3_sys>; + gpio =3D <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&display_pwren>; + }; }; =20 &cpu_alert0 { @@ -139,6 +171,11 @@ &emmc_phy { status =3D "okay"; }; =20 +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + &i2c0 { clock-frequency =3D <400000>; i2c-scl-rising-time-ns =3D <168>; @@ -362,6 +399,40 @@ &io_domains { status =3D "okay"; }; =20 +&mipi_dsi { + status =3D "okay"; + clock-master; + + ports { + mipi_out: port@1 { + #address-cells =3D <0>; + #size-cells =3D <0>; + reg =3D <1>; + + mipi_out_panel: endpoint { + remote-endpoint =3D <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible =3D "hannstar,hsd060bhw4"; + reg =3D <0>; + backlight =3D <&backlight>; + reset-gpios =3D <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vcc2v8_lcd>; // 2v8 + iovcc-supply =3D <&vcc1v8_lcd>; // 1v8 + pinctrl-names =3D "default"; + pinctrl-0 =3D <&display_rst_l>; + + port { + mipi_in_panel: endpoint { + remote-endpoint =3D <&mipi_out_panel>; + }; + }; + }; +}; + &pmu_io_domains { pmu1830-supply =3D <&vcc_1v8>; status =3D "okay"; @@ -374,6 +445,20 @@ pwrbtn_pin: pwrbtn-pin { }; }; =20 + dsi { + display_rst_l: display-rst-l { + rockchip,pins =3D <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + display_pwren: display-pwren { + rockchip,pins =3D <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + display_pwren1: display-pwren1 { + rockchip,pins =3D <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins =3D <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; @@ -429,6 +514,10 @@ &sdio0 { status =3D "okay"; }; =20 +&pwm0 { + status =3D "okay"; +}; + &sdmmc { bus-width =3D <4>; cap-sd-highspeed; @@ -479,3 +568,25 @@ bluetooth { &uart2 { status =3D "okay"; }; + +&vopb { + status =3D "okay"; + assigned-clocks =3D <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, <&cru ACLK_VO= P0>, <&cru HCLK_VOP0>; + assigned-clock-rates =3D <0>, <0>, <400000000>, <100000000>; + assigned-clock-parents =3D <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>; +}; + +&vopb_mmu { + status =3D "okay"; +}; + +&vopl { + status =3D "okay"; + assigned-clocks =3D <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, <&cru ACLK_VO= P1>, <&cru HCLK_VOP1>; + assigned-clock-rates =3D <0>, <0>, <400000000>, <100000000>; + assigned-clock-parents =3D <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>; +}; + +&vopl_mmu { + status =3D "okay"; +}; base-commit: da8e7da11e4ba758caf4c149cc8d8cd555aefe5f --=20 2.39.2