From nobody Thu Nov 14 18:05:13 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E87DC77B74 for ; Mon, 27 Mar 2023 03:14:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232498AbjC0DOy (ORCPT ); Sun, 26 Mar 2023 23:14:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbjC0DOA (ORCPT ); Sun, 26 Mar 2023 23:14:00 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B9515249; Sun, 26 Mar 2023 20:13:47 -0700 (PDT) X-UUID: 5d9ad646cc4d11edb6b9f13eb10bd0fe-20230327 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WByBskY3OQfVkoYwoTQ6lsScT1N3NV3SSj3FxZ7ZqV8=; b=lI5EF5e5wyQb/6jshQlVsBacEelYgGo5iPygo6u6UkTSDQLDQ6Nef+x9yargOx5sxod+/90H9zrTdGTjyVLDbHMsrBP563ih7m2mvjvWFz1r+Kvkzj0ShFoExda8u2Ue05EX25LOH0wsxUHdTZolzcwq4sQUg+FAdUNt/VG4Z2E=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:6311defb-813f-495f-ba22-eae2e6493b14,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.22,REQID:6311defb-813f-495f-ba22-eae2e6493b14,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:120426c,CLOUDID:bcf870b4-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:230327111340F3DP9NF4,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 5d9ad646cc4d11edb6b9f13eb10bd0fe-20230327 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1861320625; Mon, 27 Mar 2023 11:13:37 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Mon, 27 Mar 2023 11:13:36 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Mon, 27 Mar 2023 11:13:36 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil , "Ping-Hsun Wu" CC: , , , , , Moudy Ho Subject: [PATCH v7 07/12] media: platform: mtk-mdp3: chip config split about pipe info Date: Mon, 27 Mar 2023 11:13:30 +0800 Message-ID: <20230327031335.9663-8-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230327031335.9663-1-moudy.ho@mediatek.com> References: <20230327031335.9663-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In MDP3, a pipe is used to represent a data path which consisting of different components and MUTEX, as shown in the following diagram: +----------------------------+ | MUTEX [*1] | +----------------------------+ S ^ S ^ S ^ S ^ S ^ | | | | | | | | | | | | | | | | | | | | +--------------+ | | | | | | | | +-------------+ | +--------------+ | | | | | | +-------------+ | | | +------+ | | | | +------+ | | | | | +------+ | | +------+ | | | | | | | | | | | | | | | | | | | | | | | v E v E v E v E v E +-------+ +-----+ +-------+ +-----+ +-------+ B>--->| RDMA0 |>-->| PQ |>-->| RSZ0 |>-->| PQ |>-->| WROT0 |>-->B +-------+ +-----+ +-------+ +-----+ +-------+ [*1] MUTEX is SOF/EOF signal controller [*2] S =3D Start of frame (SOF) [*3] E =3D End of frame (EOF) [*4] B =3D frame buffer More pipes will be introduced in future chips for applications such as higher frame rate frequency, which should integrate and reorder related information into specific chip config file. Signed-off-by: Moudy Ho --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 9 ++++++++ .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 23 ++++++++++++------- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 15 +++++++----- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 11 +++++++-- 4 files changed, 42 insertions(+), 16 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/= media/platform/mediatek/mdp3/mdp_cfg_data.c index 1769bce2871e..cf97ba70fddd 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -400,6 +400,13 @@ static const struct mdp_limit mt8183_mdp_def_limit =3D= { .v_scale_down_max =3D 128, }; =20 +static const struct mdp_pipe_info mt8183_pipe_info[] =3D { + [MDP_PIPE_WPEI] =3D {MDP_PIPE_WPEI, 0}, + [MDP_PIPE_WPEI2] =3D {MDP_PIPE_WPEI2, 1}, + [MDP_PIPE_IMGI] =3D {MDP_PIPE_IMGI, 2}, + [MDP_PIPE_RDMA0] =3D {MDP_PIPE_RDMA0, 3} +}; + const struct mtk_mdp_driver_data mt8183_mdp_driver_data =3D { .mdp_probe_infra =3D mt8183_mdp_probe_infra, .mdp_cfg =3D &mt8183_plat_cfg, @@ -410,6 +417,8 @@ const struct mtk_mdp_driver_data mt8183_mdp_driver_data= =3D { .format =3D mt8183_formats, .format_len =3D ARRAY_SIZE(mt8183_formats), .def_limit =3D &mt8183_mdp_def_limit, + .pipe_info =3D mt8183_pipe_info, + .pipe_info_len =3D ARRAY_SIZE(mt8183_pipe_info), }; =20 s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index dcd77f65b0e3..bff14e4944c5 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -50,21 +50,22 @@ static int mdp_path_subfrm_require(const struct mdp_pat= h *path, /* Decide which mutex to use based on the current pipeline */ switch (path->comps[0].comp->public_id) { case MDP_COMP_RDMA0: - *mutex_id =3D MDP_PIPE_RDMA0; + index =3D MDP_PIPE_RDMA0; break; case MDP_COMP_ISP_IMGI: - *mutex_id =3D MDP_PIPE_IMGI; + index =3D MDP_PIPE_IMGI; break; case MDP_COMP_WPEI: - *mutex_id =3D MDP_PIPE_WPEI; + index =3D MDP_PIPE_WPEI; break; case MDP_COMP_WPEI2: - *mutex_id =3D MDP_PIPE_WPEI2; + index =3D MDP_PIPE_WPEI2; break; default: dev_err(dev, "Unknown pipeline and no mutex is assigned"); return -EINVAL; } + *mutex_id =3D data->pipe_info[index].mutex_id; =20 /* Set mutex mod */ for (index =3D 0; index < config->num_components; index++) { @@ -286,11 +287,13 @@ static void mdp_auto_release_work(struct work_struct = *work) { struct mdp_cmdq_cmd *cmd; struct mdp_dev *mdp; + int id; =20 cmd =3D container_of(work, struct mdp_cmdq_cmd, auto_release_work); mdp =3D cmd->mdp; =20 - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + id =3D mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[id]); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); =20 @@ -310,6 +313,7 @@ static void mdp_handle_cmdq_callback(struct mbox_client= *cl, void *mssg) struct cmdq_cb_data *data; struct mdp_dev *mdp; struct device *dev; + int id; =20 if (!mssg) { pr_info("%s:no callback data\n", __func__); @@ -335,7 +339,8 @@ static void mdp_handle_cmdq_callback(struct mbox_client= *cl, void *mssg) INIT_WORK(&cmd->auto_release_work, mdp_auto_release_work); if (!queue_work(mdp->clock_wq, &cmd->auto_release_work)) { dev_err(dev, "%s:queue_work fail!\n", __func__); - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + id =3D mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[id]); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); =20 @@ -387,7 +392,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_= param *param) goto err_free_comps; } =20 - ret =3D mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i =3D mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + ret =3D mtk_mutex_prepare(mdp->mdp_mutex[i]); if (ret) { dev_err(dev, "Fail to enable mutex clk\n"); goto err_free_path; @@ -453,7 +459,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_= param *param) mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); err_free_path: - mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]); + i =3D mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; + mtk_mutex_unprepare(mdp->mdp_mutex[i]); kfree(path); err_free_comps: kfree(comps); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-core.c index 745cb06cc8bc..1c798da1df2c 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -153,7 +153,7 @@ static int mdp_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct mdp_dev *mdp; struct platform_device *mm_pdev; - int ret, i; + int ret, i, mutex_id; =20 mdp =3D kzalloc(sizeof(*mdp), GFP_KERNEL); if (!mdp) { @@ -176,10 +176,13 @@ static int mdp_probe(struct platform_device *pdev) ret =3D -ENODEV; goto err_destroy_device; } - for (i =3D 0; i < MDP_PIPE_MAX; i++) { - mdp->mdp_mutex[i] =3D mtk_mutex_get(&mm_pdev->dev); - if (IS_ERR(mdp->mdp_mutex[i])) { - ret =3D PTR_ERR(mdp->mdp_mutex[i]); + for (i =3D 0; i < mdp->mdp_data->pipe_info_len; i++) { + mutex_id =3D mdp->mdp_data->pipe_info[i].mutex_id; + if (!IS_ERR_OR_NULL(mdp->mdp_mutex[mutex_id])) + continue; + mdp->mdp_mutex[mutex_id] =3D mtk_mutex_get(&mm_pdev->dev); + if (IS_ERR(mdp->mdp_mutex[mutex_id])) { + ret =3D PTR_ERR(mdp->mdp_mutex[mutex_id]); goto err_free_mutex; } } @@ -259,7 +262,7 @@ static int mdp_probe(struct platform_device *pdev) err_deinit_comp: mdp_comp_destroy(mdp); err_free_mutex: - for (i =3D 0; i < MDP_PIPE_MAX; i++) + for (i =3D 0; i < mdp->mdp_data->pipe_info_len; i++) if (!IS_ERR_OR_NULL(mdp->mdp_mutex[i])) mtk_mutex_put(mdp->mdp_mutex[i]); err_destroy_device: diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers= /media/platform/mediatek/mdp3/mtk-mdp3-core.h index a312c1007e96..59a1c88d8184 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -43,10 +43,10 @@ struct mdp_platform_config { =20 /* indicate which mutex is used by each pipepline */ enum mdp_pipe_id { - MDP_PIPE_RDMA0, - MDP_PIPE_IMGI, MDP_PIPE_WPEI, MDP_PIPE_WPEI2, + MDP_PIPE_IMGI, + MDP_PIPE_RDMA0, MDP_PIPE_MAX }; =20 @@ -60,6 +60,8 @@ struct mtk_mdp_driver_data { const struct mdp_format *format; unsigned int format_len; const struct mdp_limit *def_limit; + const struct mdp_pipe_info *pipe_info; + unsigned int pipe_info_len; }; =20 struct mdp_dev { @@ -91,6 +93,11 @@ struct mdp_dev { atomic_t job_count; }; =20 +struct mdp_pipe_info { + enum mdp_pipe_id pipe_id; + u32 mutex_id; +}; + int mdp_vpu_get_locked(struct mdp_dev *mdp); void mdp_vpu_put_locked(struct mdp_dev *mdp); int mdp_vpu_register(struct mdp_dev *mdp); --=20 2.18.0