From nobody Mon Feb 9 02:11:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2714CC6FD1C for ; Sun, 26 Mar 2023 14:08:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231966AbjCZOIi (ORCPT ); Sun, 26 Mar 2023 10:08:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231771AbjCZOId (ORCPT ); Sun, 26 Mar 2023 10:08:33 -0400 Received: from mail-qv1-xf34.google.com (mail-qv1-xf34.google.com [IPv6:2607:f8b0:4864:20::f34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F99149F2; Sun, 26 Mar 2023 07:08:32 -0700 (PDT) Received: by mail-qv1-xf34.google.com with SMTP id 31so5165894qvc.1; Sun, 26 Mar 2023 07:08:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679839711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hlqMgsbtMdGDwnYgR2vesfxbv2C04RSOqe9u/KU4Ors=; b=KHOvRSfqQyWTy9ScGQJ8IWC0p7ihFilYWFRWGp1cuRjLBuNtSqMAa18k5ewbyq7Per F9Zk2ka0l6LdpkLmJi/Jpob3ws2xH4WfNayNory3VwV5s01MDbRtJD+d/ca8hTYcOUbk rYzAWbueY94VBEaN34s2DeUNNiWKowsy1r7nY0nG2FdjSAFre1PQjh9aTMXfw8NMxG6Y WGm/cKKdHhn0iG8Nsy8zyybIr/PS6FCBCq+fHQv87wIZFGhkjaqAjqoyqUUJcfFystzZ ADKkLHoTDOIc3nWfngO1AOjGoSQtIM/JOyjzymCi0bR4wnPBYnx+Y03BkBl4M1Ky0IE5 epbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679839711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hlqMgsbtMdGDwnYgR2vesfxbv2C04RSOqe9u/KU4Ors=; b=C7UwsxAHM2IDlgQMlLMXaw7tStheHWSenny3rVB6WCMXZXr3dqM/uHs9ItnfYr5Blg SMELBbPhkBXeMLanWVUF0dU/eTxvZjpsIBlIlRurk2asq0+n8fshZbpie8OIxD0J9hJH 5fojsM0CEkWBYWcQwvsTqRnchA/6AwhwRnPuORIMqVuZ8uo1xVWHaFnt2o7uOBrscu10 9XKD/KJu3sHMN8kX+qZUYU15nVEZQmpDxeD33MEWXhwoFGcasbU1w8zm0LHS6meiDqLs DYx0zcqGUmvr6hxQzRASkWRfiTh8Ss+/mT7AG5jcD6zQpqIH4jTLTDIY/cWlK0rrKH1m APxg== X-Gm-Message-State: AAQBX9dDB0pjR3pO/aXO83EJv42K1hIAerL4YCwPTlWqWlag1ifjsbDj qWEjVcAY1O/4NdTYCxZ0fWQ= X-Google-Smtp-Source: AKy350bQt+rT9tKjyp+jcmLOuyVtQ8y49KPu+aHAFnNI18NCKk4Cu4hKAl6gcnlq2J65UPddcNsBWw== X-Received: by 2002:a05:6214:258a:b0:56f:c138:2844 with SMTP id fq10-20020a056214258a00b0056fc1382844mr16074703qvb.37.1679839711363; Sun, 26 Mar 2023 07:08:31 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id j5-20020a0ce6a5000000b005dd8b93458esm2212220qvn.38.2023.03.26.07.08.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Mar 2023 07:08:31 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Russell King , Landen Chao , Ilya Lipnitskiy , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net 1/7] net: dsa: mt7530: fix comments regarding port 5 and 6 for both switches Date: Sun, 26 Mar 2023 17:08:12 +0300 Message-Id: <20230326140818.246575-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230326140818.246575-1-arinc.unal@arinc9.com> References: <20230326140818.246575-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There's no logic to numerically order the CPU ports. State the port number and its being a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for both the MT7530 and MT7531 switches but there's no phy muxing on MT7531. Fixes: ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") Fixes: 38f790a80560 ("net: dsa: mt7530: Add support for port 5") Fixes: 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding= a new hardware") Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 02410ac439b7..62a4b899a961 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2454,7 +2454,7 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, a CPU port, supports rgmii, mii, and gmii. */ phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2462,7 +2462,7 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 6: /* 1st cpu port */ + case 6: /* Port 6, a CPU port, supports rgmii and trgmii. */ __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2487,14 +2487,14 @@ static void mt7531_mac_port_get_caps(struct dsa_swi= tch *ds, int port, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + case 5: /* Port 5, a CPU port, supports rgmii and sgmii/802.3z. */ if (mt7531_is_rgmii_port(priv, port)) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; =20 - case 6: /* 1st cpu port supports sgmii/8023z only */ + case 6: /* Port 6, a CPU port, supports sgmii/802.3z only. */ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2772,7 +2772,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (state->interface !=3D PHY_INTERFACE_MODE_GMII) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, a CPU port. */ if (priv->p5_interface =3D=3D state->interface) break; =20 @@ -2782,7 +2782,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (priv->p5_intf_sel !=3D P5_DISABLED) priv->p5_interface =3D state->interface; break; - case 6: /* 1st cpu port */ + case 6: /* Port 6, a CPU port. */ if (priv->p6_interface =3D=3D state->interface) break; =20 --=20 2.37.2