From nobody Fri Dec 19 07:49:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 427F5C6FD1C for ; Sun, 26 Mar 2023 05:29:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231921AbjCZF3L (ORCPT ); Sun, 26 Mar 2023 01:29:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231330AbjCZF3J (ORCPT ); Sun, 26 Mar 2023 01:29:09 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DA8993CA; Sat, 25 Mar 2023 22:29:05 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id u38so3620908pfg.10; Sat, 25 Mar 2023 22:29:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679808544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YKhnMooh27ljfK1QnQ9/evwUgskAV4ZMTmZuvKU5mBY=; b=DPKd59Ctd/pEFdgcPXZjdaMzbrRkF3dNGVY2Nhb0Xmcs1Hwtfw1MJ+3GDzF8hB8xl5 Gl/QglRYLmo6POOBEXkLSnFX0fkuPe1Y85bUg+ZVi92qveYyTJGpRT4UmbhOLO4Vm8jj caJzhXnI7U1PmCAeQizsVX4htEMux7W7ihZm8G19qkxOenh6fhIEUML6dz97k6W4ojIs c7wm6mlqrGtJUYbOGRtb1SbZNJQqgzTGhpVECwReAGXb79kvHIdGlu008GsYBEVik94g zW4doY3FFOwpbC+LhOODY6OI5ECugkDunoGxMco5xgJw2qVGO6UeZRRjjNXjhX4t9kfH H8fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679808544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YKhnMooh27ljfK1QnQ9/evwUgskAV4ZMTmZuvKU5mBY=; b=zoftecA2KbseSwc3Jpqmm9FPuQoEDvxF1tYadtzjmFl7AFUp4w+C/jWP/KTOUCpVfN b0o21FZeXqdrkKDt/uK3vVDzqqFRKYd9zyfIbL3cMjo9/CmtK8NsuCCrx7VlEXqZ5pCF teH0PU6xhOVxDrRKKBxICKLlAAncKIdadawlYrM/2yzqfi31hdWPoqBuYXe4QoYj4Fmk mHqTcBtAbZvtmpzLVydvKw/qhgVyvMTDnqMwR+F+88h9kKhHMWDpRmNXmfrzk6XWA08G LqL83WSR9288MT6lwAybm0vIGPXpyOk7gUrFN+sbvExU12YdeJfcLrT5RYQOa1Cw3mir IF5g== X-Gm-Message-State: AO0yUKWqOFGwBGCWMiFjEGyJWhkvuRjKxRDRQFOXbKD8bsXDbNsDjnb6 vcZa/HR0UC8WoKT5qlf98nE+PniUB2dskuRYMAE= X-Google-Smtp-Source: AK7set/F4BQ9+srfoAOmQ0Gg2GTfqse507oBYtsMAsj+Jbl44BCUJ+e9rY6vB2iF/qS57xf+qDf5xQ== X-Received: by 2002:a05:6a00:2914:b0:627:de16:889c with SMTP id cg20-20020a056a00291400b00627de16889cmr13722391pfb.4.1679808543955; Sat, 25 Mar 2023 22:29:03 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.201]) by smtp.gmail.com with ESMTPSA id b14-20020a63eb4e000000b004fb5f4bf585sm15966915pgk.78.2023.03.25.22.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Mar 2023 22:29:03 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org Subject: [PATCH 3/4] clk: hisilicon: Convert to platform driver Date: Sun, 26 Mar 2023 13:27:49 +0800 Message-Id: <20230326052757.297551-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230326052757.297551-1-mmyangfl@gmail.com> References: <20230326052757.297551-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" And use common helper functions. This patch is part of devm APIs migration. Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3620.c | 195 ++++++++++++------------ drivers/clk/hisilicon/clk-hi6220.c | 225 +++++++++++++--------------- drivers/clk/hisilicon/clk-hip04.c | 41 +++-- drivers/clk/hisilicon/clk-hix5hd2.c | 83 ++++++---- 4 files changed, 281 insertions(+), 263 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk= -hi3620.c index a3d04c7c3da8..1eacf77b0d8c 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -22,48 +23,48 @@ #include "clk.h" =20 /* clock parent list */ -static const char *const timer0_mux_p[] __initconst =3D { "osc32k", "timer= clk01", }; -static const char *const timer1_mux_p[] __initconst =3D { "osc32k", "timer= clk01", }; -static const char *const timer2_mux_p[] __initconst =3D { "osc32k", "timer= clk23", }; -static const char *const timer3_mux_p[] __initconst =3D { "osc32k", "timer= clk23", }; -static const char *const timer4_mux_p[] __initconst =3D { "osc32k", "timer= clk45", }; -static const char *const timer5_mux_p[] __initconst =3D { "osc32k", "timer= clk45", }; -static const char *const timer6_mux_p[] __initconst =3D { "osc32k", "timer= clk67", }; -static const char *const timer7_mux_p[] __initconst =3D { "osc32k", "timer= clk67", }; -static const char *const timer8_mux_p[] __initconst =3D { "osc32k", "timer= clk89", }; -static const char *const timer9_mux_p[] __initconst =3D { "osc32k", "timer= clk89", }; -static const char *const uart0_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart1_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart2_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart3_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const uart4_mux_p[] __initconst =3D { "osc26m", "pclk",= }; -static const char *const spi0_mux_p[] __initconst =3D { "osc26m", "rclk_cf= gaxi", }; -static const char *const spi1_mux_p[] __initconst =3D { "osc26m", "rclk_cf= gaxi", }; -static const char *const spi2_mux_p[] __initconst =3D { "osc26m", "rclk_cf= gaxi", }; +static const char *const timer0_mux_p[] =3D { "osc32k", "timerclk01", }; +static const char *const timer1_mux_p[] =3D { "osc32k", "timerclk01", }; +static const char *const timer2_mux_p[] =3D { "osc32k", "timerclk23", }; +static const char *const timer3_mux_p[] =3D { "osc32k", "timerclk23", }; +static const char *const timer4_mux_p[] =3D { "osc32k", "timerclk45", }; +static const char *const timer5_mux_p[] =3D { "osc32k", "timerclk45", }; +static const char *const timer6_mux_p[] =3D { "osc32k", "timerclk67", }; +static const char *const timer7_mux_p[] =3D { "osc32k", "timerclk67", }; +static const char *const timer8_mux_p[] =3D { "osc32k", "timerclk89", }; +static const char *const timer9_mux_p[] =3D { "osc32k", "timerclk89", }; +static const char *const uart0_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart1_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart2_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart3_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const uart4_mux_p[] =3D { "osc26m", "pclk", }; +static const char *const spi0_mux_p[] =3D { "osc26m", "rclk_cfgaxi", }; +static const char *const spi1_mux_p[] =3D { "osc26m", "rclk_cfgaxi", }; +static const char *const spi2_mux_p[] =3D { "osc26m", "rclk_cfgaxi", }; /* share axi parent */ -static const char *const saxi_mux_p[] __initconst =3D { "armpll3", "armpll= 2", }; -static const char *const pwm0_mux_p[] __initconst =3D { "osc32k", "osc26m"= , }; -static const char *const pwm1_mux_p[] __initconst =3D { "osc32k", "osc26m"= , }; -static const char *const sd_mux_p[] __initconst =3D { "armpll2", "armpll3"= , }; -static const char *const mmc1_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const mmc1_mux2_p[] __initconst =3D { "osc26m", "mmc1_d= iv", }; -static const char *const g2d_mux_p[] __initconst =3D { "armpll2", "armpll3= ", }; -static const char *const venc_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const vdec_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const vpp_mux_p[] __initconst =3D { "armpll2", "armpll3= ", }; -static const char *const edc0_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const ldi0_mux_p[] __initconst =3D { "armpll2", "armpll= 4", +static const char *const saxi_mux_p[] =3D { "armpll3", "armpll2", }; +static const char *const pwm0_mux_p[] =3D { "osc32k", "osc26m", }; +static const char *const pwm1_mux_p[] =3D { "osc32k", "osc26m", }; +static const char *const sd_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const mmc1_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const mmc1_mux2_p[] =3D { "osc26m", "mmc1_div", }; +static const char *const g2d_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const venc_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const vdec_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const vpp_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const edc0_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const ldi0_mux_p[] =3D { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *const edc1_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const ldi1_mux_p[] __initconst =3D { "armpll2", "armpll= 4", +static const char *const edc1_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const ldi1_mux_p[] =3D { "armpll2", "armpll4", "armpll3", "armpll5", }; -static const char *const rclk_hsic_p[] __initconst =3D { "armpll3", "armpl= l2", }; -static const char *const mmc2_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; -static const char *const mmc3_mux_p[] __initconst =3D { "armpll2", "armpll= 3", }; +static const char *const rclk_hsic_p[] =3D { "armpll3", "armpll2", }; +static const char *const mmc2_mux_p[] =3D { "armpll2", "armpll3", }; +static const char *const mmc3_mux_p[] =3D { "armpll2", "armpll3", }; =20 =20 /* fixed rate clocks */ -static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] __initdata = =3D { +static struct hisi_fixed_rate_clock hi3620_fixed_rate_clks[] =3D { { HI3620_OSC32K, "osc32k", NULL, 0, 32768, }, { HI3620_OSC26M, "osc26m", NULL, 0, 26000000, }, { HI3620_PCLK, "pclk", NULL, 0, 26000000, }, @@ -76,13 +77,13 @@ static struct hisi_fixed_rate_clock hi3620_fixed_rate_c= lks[] __initdata =3D { }; =20 /* fixed factor clocks */ -static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] __initdat= a =3D { +static struct hisi_fixed_factor_clock hi3620_fixed_factor_clks[] =3D { { HI3620_RCLK_TCXO, "rclk_tcxo", "osc26m", 1, 4, 0, }, { HI3620_RCLK_CFGAXI, "rclk_cfgaxi", "armpll2", 1, 30, 0, }, { HI3620_RCLK_PICO, "rclk_pico", "hsic_div", 1, 40, 0, }, }; =20 -static struct hisi_mux_clock hi3620_mux_clks[] __initdata =3D { +static struct hisi_mux_clock hi3620_mux_clks[] =3D { { HI3620_TIMER0_MUX, "timer0_mux", timer0_mux_p, ARRAY_SIZE(timer0_mux_p)= , CLK_SET_RATE_PARENT, 0, 15, 2, 0, }, { HI3620_TIMER1_MUX, "timer1_mux", timer1_mux_p, ARRAY_SIZE(timer1_mux_p)= , CLK_SET_RATE_PARENT, 0, 17, 2, 0, }, { HI3620_TIMER2_MUX, "timer2_mux", timer2_mux_p, ARRAY_SIZE(timer2_mux_p)= , CLK_SET_RATE_PARENT, 0, 19, 2, 0, }, @@ -120,7 +121,7 @@ static struct hisi_mux_clock hi3620_mux_clks[] __initda= ta =3D { { HI3620_MMC3_MUX, "mmc3_mux", mmc3_mux_p, ARRAY_SIZE(mmc3_mux_p), = CLK_SET_RATE_PARENT, 0x140, 9, 1, CLK_MUX_HIWORD_MASK, }, }; =20 -static struct hisi_divider_clock hi3620_div_clks[] __initdata =3D { +static struct hisi_divider_clock hi3620_div_clks[] =3D { { HI3620_SHAREAXI_DIV, "saxi_div", "saxi_mux", 0, 0x100, 0, 5, CLK_DIV= IDER_HIWORD_MASK, NULL, }, { HI3620_CFGAXI_DIV, "cfgaxi_div", "saxi_div", 0, 0x100, 5, 2, CLK_DIV= IDER_HIWORD_MASK, NULL, }, { HI3620_SD_DIV, "sd_div", "sd_mux", 0, 0x108, 0, 4, CLK_DIVI= DER_HIWORD_MASK, NULL, }, @@ -130,7 +131,7 @@ static struct hisi_divider_clock hi3620_div_clks[] __in= itdata =3D { { HI3620_MMC3_DIV, "mmc3_div", "mmc3_mux", 0, 0x140, 5, 4, CLK_DIV= IDER_HIWORD_MASK, NULL, }, }; =20 -static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata =3D { +static struct hisi_gate_clock hi3620_separated_gate_clks[] =3D { { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PAREN= T, 0x20, 0, 0, }, { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PAREN= T, 0x20, 1, 0, }, { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PAREN= T, 0x20, 2, 0, }, @@ -192,29 +193,19 @@ static struct hisi_gate_clock hi3620_separated_gate_c= lks[] __initdata =3D { { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PAREN= T, 0x50, 24, 0, }, }; =20 -static void __init hi3620_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HI3620_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks, - ARRAY_SIZE(hi3620_fixed_rate_clks), - clk_data); - hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks, - ARRAY_SIZE(hi3620_fixed_factor_clks), - clk_data); - hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), - clk_data); - hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), - clk_data); - hisi_clk_register_gate_sep(hi3620_separated_gate_clks, - ARRAY_SIZE(hi3620_separated_gate_clks), - clk_data); -} -CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init); +static const struct hisi_clocks hi3620_clks =3D { + .nr =3D HI3620_NR_CLKS, + .fixed_rate_clks =3D hi3620_fixed_rate_clks, + .fixed_rate_clks_num =3D ARRAY_SIZE(hi3620_fixed_rate_clks), + .fixed_factor_clks =3D hi3620_fixed_factor_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hi3620_fixed_factor_clks), + .mux_clks =3D hi3620_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hi3620_mux_clks), + .divider_clks =3D hi3620_div_clks, + .divider_clks_num =3D ARRAY_SIZE(hi3620_div_clks), + .gate_sep_clks =3D hi3620_separated_gate_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi3620_separated_gate_clks), +}; =20 struct hisi_mmc_clock { unsigned int id; @@ -252,7 +243,7 @@ struct clk_mmc { =20 #define to_mmc(_hw) container_of(_hw, struct clk_mmc, hw) =20 -static struct hisi_mmc_clock hi3620_mmc_clks[] __initdata =3D { +static struct hisi_mmc_clock hi3620_mmc_clks[] =3D { { HI3620_SD_CIUCLK, "sd_bclk1", "sd_clk", CLK_SET_RATE_PARENT, 0x1f8, 0, = 0x1f8, 1, 3, 0x1f8, 4, 4, 0x1f8, 8, 4}, { HI3620_MMC_CIUCLK1, "mmc_bclk1", "mmc_clk1", CLK_SET_RATE_PARENT, 0x1= f8, 12, 0x1f8, 13, 3, 0x1f8, 16, 4, 0x1f8, 20, 4}, { HI3620_MMC_CIUCLK2, "mmc_bclk2", "mmc_clk2", CLK_SET_RATE_PARENT, 0x1= f8, 24, 0x1f8, 25, 3, 0x1f8, 28, 4, 0x1fc, 0, 4}, @@ -408,8 +399,9 @@ static const struct clk_ops clk_mmc_ops =3D { .recalc_rate =3D mmc_clk_recalc_rate, }; =20 -static struct clk *hisi_register_clk_mmc(struct hisi_mmc_clock *mmc_clk, - void __iomem *base, struct device_node *np) +static struct clk * +clk_register_hisi_mmc(struct device *dev, const struct hisi_mmc_clock *mmc= _clk, + void __iomem *base) { struct clk_mmc *mclk; struct clk *clk; @@ -445,39 +437,52 @@ static struct clk *hisi_register_clk_mmc(struct hisi_= mmc_clock *mmc_clk, return clk; } =20 -static void __init hi3620_mmc_clk_init(struct device_node *node) +static int hisi_register_clk_mmc(struct device *dev, const void *clocks, + int nums, struct hisi_clock_data *data) { - void __iomem *base; - int i, num =3D ARRAY_SIZE(hi3620_mmc_clks); - struct clk_onecell_data *clk_data; - - if (!node) { - pr_err("failed to find pctrl node in DTS\n"); - return; - } - - base =3D of_iomap(node, 0); - if (!base) { - pr_err("failed to map pctrl\n"); - return; + const struct hisi_mmc_clock *clks =3D clocks; + struct clk *clk; + int i; + + for (i =3D 0; i < nums; i++) { + clk =3D clk_register_hisi_mmc(dev, &clks[i], data->base); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + return PTR_ERR(clk); + } + data->clk_data.clks[clks[i].id] =3D clk; } =20 - clk_data =3D kzalloc(sizeof(*clk_data), GFP_KERNEL); - if (WARN_ON(!clk_data)) - return; + return 0; +} =20 - clk_data->clks =3D kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL); - if (!clk_data->clks) - return; +static const struct hisi_clocks hi3620_clks_mmc =3D { + .nr =3D ARRAY_SIZE(hi3620_mmc_clks), + .customized_clks =3D hi3620_mmc_clks, + .customized_clks_num =3D ARRAY_SIZE(hi3620_mmc_clks), + .clk_register_customized =3D hisi_register_clk_mmc, +}; =20 - for (i =3D 0; i < num; i++) { - struct hisi_mmc_clock *mmc_clk =3D &hi3620_mmc_clks[i]; - clk_data->clks[mmc_clk->id] =3D - hisi_register_clk_mmc(mmc_clk, base, node); - } +static const struct of_device_id hi3620_clk_match_table[] =3D { + { .compatible =3D "hisilicon,hi3620-clock", + .data =3D &hi3620_clks }, + { .compatible =3D "hisilicon,hi3620-mmc-clock", + .data =3D &hi3620_clks_mmc }, + { } +}; +MODULE_DEVICE_TABLE(of, hi3620_clk_match_table); + +static struct platform_driver hi3620_clk_driver =3D { + .probe =3D hisi_clk_probe, + .remove =3D hisi_clk_remove, + .driver =3D { + .name =3D "hi3620-clock", + .of_match_table =3D hi3620_clk_match_table, + }, +}; =20 - clk_data->clk_num =3D num; - of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); -} +module_platform_driver(hi3620_clk_driver); =20 -CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_cl= k_init); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("HiSilicon Hi3620 Clock Driver"); diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk= -hi6220.c index e7cdf72d4b06..cdc17f82ce2d 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -9,20 +9,15 @@ =20 #include #include -#include -#include -#include -#include +#include #include -#include =20 #include =20 #include "clk.h" =20 - /* clocks in AO (always on) controller */ -static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = =3D { +static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] =3D { { HI6220_REF32K, "ref32k", NULL, 0, 32764, }, { HI6220_CLK_TCXO, "clk_tcxo", NULL, 0, 19200000, }, { HI6220_MMC1_PAD, "mmc1_pad", NULL, 0, 100000000, }, @@ -38,7 +33,7 @@ static struct hisi_fixed_rate_clock hi6220_fixed_rate_clk= s[] __initdata =3D { { HI6220_PLL_DDR, "ddrpll0", NULL, 0, 1600000000,}, }; =20 -static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdat= a =3D { +static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] =3D { { HI6220_300M, "clk_300m", "syspll", 1, 4, 0, }, { HI6220_150M, "clk_150m", "clk_300m", 1, 2, 0, }, { HI6220_PICOPHY_SRC, "picophy_src", "clk_150m", 1, 4, 0, }, @@ -51,7 +46,7 @@ static struct hisi_fixed_factor_clock hi6220_fixed_factor= _clks[] __initdata =3D { { HI6220_MMC2_SMP, "mmc2_sample", "mmc2_sel", 1, 8, 0, }, }; =20 -static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = =3D { +static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] =3D { { HI6220_WDT0_PCLK, "wdt0_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_= IGNORE_UNUSED, 0x630, 12, 0, }, { HI6220_WDT1_PCLK, "wdt1_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_= IGNORE_UNUSED, 0x630, 13, 0, }, { HI6220_WDT2_PCLK, "wdt2_pclk", "ref32k", CLK_SET_RATE_PARENT|CLK_= IGNORE_UNUSED, 0x630, 14, 0, }, @@ -69,47 +64,43 @@ static struct hisi_gate_clock hi6220_separated_gate_clk= s_ao[] __initdata =3D { { HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_= IGNORE_UNUSED, 0x630, 26, 0, }, }; =20 -static void __init hi6220_clk_ao_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data_ao; - - clk_data_ao =3D hisi_clk_init(np, HI6220_AO_NR_CLKS); - if (!clk_data_ao) - return; - - hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks, - ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao); - - hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks, - ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao); +static const struct hisi_clocks hi6220_ao_clks =3D { + .nr =3D HI6220_AO_NR_CLKS, + .fixed_rate_clks =3D hi6220_fixed_rate_clks, + .fixed_rate_clks_num =3D ARRAY_SIZE(hi6220_fixed_rate_clks), + .fixed_factor_clks =3D hi6220_fixed_factor_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hi6220_fixed_factor_clks), + .gate_sep_clks =3D hi6220_separated_gate_clks_ao, + .gate_sep_clks_num =3D ARRAY_SIZE(hi6220_separated_gate_clks_ao), +}; =20 - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao, - ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao); +static void hi6220_clk_ao_early_init(struct device_node *np) +{ + hisi_clk_early_init(np, &hi6220_ao_clks); } /* Allow reset driver to probe as well */ -CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk= _ao_init); - +CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk= _ao_early_init); =20 /* clocks in sysctrl */ -static const char *mmc0_mux0_p[] __initdata =3D { "pll_ddr_gate", "syspll"= , }; -static const char *mmc0_mux1_p[] __initdata =3D { "mmc0_mux0", "pll_media_= gate", }; -static const char *mmc0_src_p[] __initdata =3D { "mmc0srcsel", "mmc0_div",= }; -static const char *mmc1_mux0_p[] __initdata =3D { "pll_ddr_gate", "syspll"= , }; -static const char *mmc1_mux1_p[] __initdata =3D { "mmc1_mux0", "pll_media_= gate", }; -static const char *mmc1_src_p[] __initdata =3D { "mmc1srcsel", "mmc1_div"= , }; -static const char *mmc2_mux0_p[] __initdata =3D { "pll_ddr_gate", "syspll"= , }; -static const char *mmc2_mux1_p[] __initdata =3D { "mmc2_mux0", "pll_media_= gate", }; -static const char *mmc2_src_p[] __initdata =3D { "mmc2srcsel", "mmc2_div"= , }; -static const char *mmc0_sample_in[] __initdata =3D { "mmc0_sample", "mmc0_= pad", }; -static const char *mmc1_sample_in[] __initdata =3D { "mmc1_sample", "mmc1_= pad", }; -static const char *mmc2_sample_in[] __initdata =3D { "mmc2_sample", "mmc2_= pad", }; -static const char *uart1_src[] __initdata =3D { "clk_tcxo", "clk_150m", }; -static const char *uart2_src[] __initdata =3D { "clk_tcxo", "clk_150m", }; -static const char *uart3_src[] __initdata =3D { "clk_tcxo", "clk_150m", }; -static const char *uart4_src[] __initdata =3D { "clk_tcxo", "clk_150m", }; -static const char *hifi_src[] __initdata =3D { "syspll", "pll_media_gate",= }; - -static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = =3D { +static const char * const mmc0_mux0_p[] =3D { "pll_ddr_gate", "syspll", }; +static const char * const mmc0_mux1_p[] =3D { "mmc0_mux0", "pll_media_gate= ", }; +static const char * const mmc0_src_p[] =3D { "mmc0srcsel", "mmc0_div", }; +static const char * const mmc1_mux0_p[] =3D { "pll_ddr_gate", "syspll", }; +static const char * const mmc1_mux1_p[] =3D { "mmc1_mux0", "pll_media_gate= ", }; +static const char * const mmc1_src_p[] =3D { "mmc1srcsel", "mmc1_div", }; +static const char * const mmc2_mux0_p[] =3D { "pll_ddr_gate", "syspll", }; +static const char * const mmc2_mux1_p[] =3D { "mmc2_mux0", "pll_media_gate= ", }; +static const char * const mmc2_src_p[] =3D { "mmc2srcsel", "mmc2_div", }; +static const char * const mmc0_sample_in[] =3D { "mmc0_sample", "mmc0_pad"= , }; +static const char * const mmc1_sample_in[] =3D { "mmc1_sample", "mmc1_pad"= , }; +static const char * const mmc2_sample_in[] =3D { "mmc2_sample", "mmc2_pad"= , }; +static const char * const uart1_src[] =3D { "clk_tcxo", "clk_150m", }; +static const char * const uart2_src[] =3D { "clk_tcxo", "clk_150m", }; +static const char * const uart3_src[] =3D { "clk_tcxo", "clk_150m", }; +static const char * const uart4_src[] =3D { "clk_tcxo", "clk_150m", }; +static const char * const hifi_src[] =3D { "syspll", "pll_media_gate", }; + +static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] =3D { { HI6220_MMC0_CLK, "mmc0_clk", "mmc0_src", CLK_SET_RATE_P= ARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, { HI6220_MMC0_CIUCLK, "mmc0_ciuclk", "mmc0_smp_in", CLK_SET_RATE_P= ARENT|CLK_IGNORE_UNUSED, 0x200, 0, 0, }, { HI6220_MMC1_CLK, "mmc1_clk", "mmc1_src", CLK_SET_RATE_P= ARENT|CLK_IGNORE_UNUSED, 0x200, 1, 0, }, @@ -146,7 +137,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clk= s_sys[] __initdata =3D { { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_P= ARENT|CLK_IS_CRITICAL, 0x270, 12, 0, }, }; =20 -static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata =3D { +static struct hisi_mux_clock hi6220_mux_clks_sys[] =3D { { HI6220_MMC0_SRC, "mmc0_src", mmc0_src_p, ARRAY_SIZE(mmc0_src_= p), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, }, { HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_samp= le_in), CLK_SET_RATE_PARENT, 0x4, 0, 1, 0, }, { HI6220_MMC1_SRC, "mmc1_src", mmc1_src_p, ARRAY_SIZE(mmc1_src_= p), CLK_SET_RATE_PARENT, 0x4, 2, 1, 0, }, @@ -166,7 +157,7 @@ static struct hisi_mux_clock hi6220_mux_clks_sys[] __in= itdata =3D { { HI6220_MMC2_MUX1, "mmc2_mux1", mmc2_mux1_p, ARRAY_SIZE(mmc2_mux1= _p), CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,}, }; =20 -static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata =3D { +static struct hi6220_divider_clock hi6220_div_clks_sys[] =3D { { HI6220_CLK_BUS, "clk_bus", "clk_300m", CLK_SET_RATE_PARENT= , 0x490, 0, 4, 7, }, { HI6220_MMC0_DIV, "mmc0_div", "mmc0_syspll", CLK_SET_RATE_PARENT= , 0x494, 0, 6, 7, }, { HI6220_MMC1_DIV, "mmc1_div", "mmc1_syspll", CLK_SET_RATE_PARENT= , 0x498, 0, 6, 7, }, @@ -177,32 +168,23 @@ static struct hi6220_divider_clock hi6220_div_clks_sy= s[] __initdata =3D { { HI6220_CS_ATB_DIV, "cs_atb_div", "cs_atb_syspll", CLK_SET_RATE_PARENT= , 0x4a4, 0, 4, 7, }, }; =20 -static void __init hi6220_clk_sys_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HI6220_SYS_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, - ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); - - hisi_clk_register_mux(hi6220_mux_clks_sys, - ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); - - hi6220_clk_register_divider(hi6220_div_clks_sys, - ARRAY_SIZE(hi6220_div_clks_sys), clk_data); -} -CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_c= lk_sys_init); - +static const struct hisi_clocks hi6220_sys_clks =3D { + .nr =3D HI6220_SYS_NR_CLKS, + .mux_clks =3D hi6220_mux_clks_sys, + .mux_clks_num =3D ARRAY_SIZE(hi6220_mux_clks_sys), + .gate_sep_clks =3D hi6220_separated_gate_clks_sys, + .gate_sep_clks_num =3D ARRAY_SIZE(hi6220_separated_gate_clks_sys), + .customized_clks =3D hi6220_div_clks_sys, + .customized_clks_num =3D ARRAY_SIZE(hi6220_div_clks_sys), + /* .clk_register_customized =3D hi6220_clk_register_divider, */ +}; =20 /* clocks in media controller */ -static const char *clk_1000_1200_src[] __initdata =3D { "pll_gpu_gate", "m= edia_syspll_src", }; -static const char *clk_1440_1200_src[] __initdata =3D { "media_syspll_src"= , "media_pll_src", }; -static const char *clk_1000_1440_src[] __initdata =3D { "pll_gpu_gate", "m= edia_pll_src", }; +static const char * const clk_1000_1200_src[] =3D { "pll_gpu_gate", "media= _syspll_src", }; +static const char * const clk_1440_1200_src[] =3D { "media_syspll_src", "m= edia_pll_src", }; +static const char * const clk_1000_1440_src[] =3D { "pll_gpu_gate", "media= _pll_src", }; =20 -static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdat= a =3D { +static struct hisi_gate_clock hi6220_separated_gate_clks_media[] =3D { { HI6220_DSI_PCLK, "dsi_pclk", "vpucodec", CLK_SET_RAT= E_PARENT|CLK_IGNORE_UNUSED, 0x520, 0, 0, }, { HI6220_G3D_PCLK, "g3d_pclk", "vpucodec", CLK_SET_RAT= E_PARENT|CLK_IGNORE_UNUSED, 0x520, 1, 0, }, { HI6220_ACLK_CODEC_VPU, "aclk_codec_vpu", "ade_core_src", CLK_SET_RAT= E_PARENT|CLK_IGNORE_UNUSED, 0x520, 3, 0, }, @@ -218,13 +200,13 @@ static struct hisi_gate_clock hi6220_separated_gate_c= lks_media[] __initdata =3D { { HI6220_MED_SYSPLL, "media_syspll_src", "media_syspll", CLK_SET_RAT= E_PARENT|CLK_IGNORE_UNUSED, 0x520, 17, 0, }, }; =20 -static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata =3D { +static struct hisi_mux_clock hi6220_mux_clks_media[] =3D { { HI6220_1440_1200, "clk_1440_1200", clk_1440_1200_src, ARRAY_SIZE(clk_14= 40_1200_src), CLK_SET_RATE_PARENT, 0x51c, 0, 1, 0, }, { HI6220_1000_1200, "clk_1000_1200", clk_1000_1200_src, ARRAY_SIZE(clk_10= 00_1200_src), CLK_SET_RATE_PARENT, 0x51c, 1, 1, 0, }, { HI6220_1000_1440, "clk_1000_1440", clk_1000_1440_src, ARRAY_SIZE(clk_10= 00_1440_src), CLK_SET_RATE_PARENT, 0x51c, 6, 1, 0, }, }; =20 -static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata =3D { +static struct hi6220_divider_clock hi6220_div_clks_media[] =3D { { HI6220_CODEC_JPEG, "codec_jpeg_aclk", "media_pll_src", CLK_SET_RATE= _PARENT, 0xcbc, 0, 4, 23, }, { HI6220_ISP_SCLK_SRC, "isp_sclk_src", "isp_sclk_gate", CLK_SET_RATE= _PARENT, 0xcbc, 8, 4, 15, }, { HI6220_ISP_SCLK1, "isp_sclk1", "isp_sclk_gate1", CLK_SET_RATE= _PARENT, 0xcbc, 24, 4, 31, }, @@ -234,28 +216,19 @@ static struct hi6220_divider_clock hi6220_div_clks_me= dia[] __initdata =3D { { HI6220_CODEC_VPU_SRC, "codec_vpu_src", "codec_vpu_gate", CLK_SET_RATE= _PARENT, 0xcc4, 24, 6, 31, }, }; =20 -static void __init hi6220_clk_media_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HI6220_MEDIA_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media, - ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data); - - hisi_clk_register_mux(hi6220_mux_clks_media, - ARRAY_SIZE(hi6220_mux_clks_media), clk_data); - - hi6220_clk_register_divider(hi6220_div_clks_media, - ARRAY_SIZE(hi6220_div_clks_media), clk_data); -} -CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi62= 20_clk_media_init); - +static const struct hisi_clocks hi6220_media_clks =3D { + .nr =3D HI6220_MEDIA_NR_CLKS, + .mux_clks =3D hi6220_mux_clks_media, + .mux_clks_num =3D ARRAY_SIZE(hi6220_mux_clks_media), + .gate_sep_clks =3D hi6220_separated_gate_clks_media, + .gate_sep_clks_num =3D ARRAY_SIZE(hi6220_separated_gate_clks_media), + .customized_clks =3D hi6220_div_clks_media, + .customized_clks_num =3D ARRAY_SIZE(hi6220_div_clks_media), + /* .clk_register_customized =3D hi6220_clk_register_divider, */ +}; =20 /* clocks in pmctrl */ -static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata =3D { +static struct hisi_gate_clock hi6220_gate_clks_power[] =3D { { HI6220_PLL_GPU_GATE, "pll_gpu_gate", "gpupll", CLK_SET_RATE_PARE= NT|CLK_IGNORE_UNUSED, 0x8, 0, 0, }, { HI6220_PLL1_DDR_GATE, "pll1_ddr_gate", "ddrpll1", CLK_SET_RATE_PARE= NT|CLK_IGNORE_UNUSED, 0x10, 0, 0, }, { HI6220_PLL_DDR_GATE, "pll_ddr_gate", "ddrpll0", CLK_SET_RATE_PARE= NT|CLK_IGNORE_UNUSED, 0x18, 0, 0, }, @@ -263,26 +236,19 @@ static struct hisi_gate_clock hi6220_gate_clks_power[= ] __initdata =3D { { HI6220_PLL0_BBP_GATE, "pll0_bbp_gate", "bbppll0", CLK_SET_RATE_PARE= NT|CLK_IGNORE_UNUSED, 0x48, 0, 0, }, }; =20 -static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata =3D { +static struct hi6220_divider_clock hi6220_div_clks_power[] =3D { { HI6220_DDRC_SRC, "ddrc_src", "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a= 8, 0, 4, 0, }, { HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src", CLK_SET_RATE_PARENT, 0x5a= 8, 8, 2, 0, }, }; =20 -static void __init hi6220_clk_power_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HI6220_POWER_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_gate(hi6220_gate_clks_power, - ARRAY_SIZE(hi6220_gate_clks_power), clk_data); - - hi6220_clk_register_divider(hi6220_div_clks_power, - ARRAY_SIZE(hi6220_div_clks_power), clk_data); -} -CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_pow= er_init); +static const struct hisi_clocks hi6220_power_clks =3D { + .nr =3D HI6220_POWER_NR_CLKS, + .gate_clks =3D hi6220_gate_clks_power, + .gate_clks_num =3D ARRAY_SIZE(hi6220_gate_clks_power), + .customized_clks =3D hi6220_div_clks_power, + .customized_clks_num =3D ARRAY_SIZE(hi6220_div_clks_power), + /* .clk_register_customized =3D hi6220_clk_register_divider, */ +}; =20 /* clocks in acpu */ static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] =3D { @@ -290,18 +256,37 @@ static const struct hisi_gate_clock hi6220_acpu_sc_ga= te_sep_clks[] =3D { CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, }, }; =20 -static void __init hi6220_clk_acpu_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - int nr =3D ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks); +static const struct hisi_clocks hi6220_acpu_clks =3D { + .nr =3D ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), + .gate_sep_clks =3D hi6220_acpu_sc_gate_sep_clks, + .gate_sep_clks_num =3D ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), +}; =20 - clk_data =3D hisi_clk_init(np, nr); - if (!clk_data) - return; +static const struct of_device_id hi6220_clk_match_table[] =3D { + { .compatible =3D "hisilicon,hi6220-aoctrl", + .data =3D &hi6220_ao_clks }, + { .compatible =3D "hisilicon,hi6220-sysctrl", + .data =3D &hi6220_sys_clks }, + { .compatible =3D "hisilicon,hi6220-mediactrl", + .data =3D &hi6220_media_clks }, + { .compatible =3D "hisilicon,hi6220-pmctrl", + .data =3D &hi6220_power_clks }, + { .compatible =3D "hisilicon,hi6220-acpu-sctrl", + .data =3D &hi6220_acpu_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hi6220_clk_match_table); + +static struct platform_driver hi6220_clk_driver =3D { + .probe =3D hisi_clk_probe, + .remove =3D hisi_clk_remove, + .driver =3D { + .name =3D "hi6220-clock", + .of_match_table =3D hi6220_clk_match_table, + }, +}; =20 - hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks, - ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), - clk_data); -} +module_platform_driver(hi6220_clk_driver); =20 -CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_= acpu_init); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hi6220 Clock Driver"); diff --git a/drivers/clk/hisilicon/clk-hip04.c b/drivers/clk/hisilicon/clk-= hip04.c index 785b9faf3ea5..e7d9582acc14 100644 --- a/drivers/clk/hisilicon/clk-hip04.c +++ b/drivers/clk/hisilicon/clk-hip04.c @@ -9,12 +9,8 @@ */ =20 #include -#include -#include -#include -#include +#include #include -#include =20 #include =20 @@ -27,16 +23,29 @@ static struct hisi_fixed_rate_clock hip04_fixed_rate_cl= ks[] __initdata =3D { { HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, }, }; =20 -static void __init hip04_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; +static const struct hisi_clocks hip04_clks =3D { + .nr =3D ARRAY_SIZE(hip04_fixed_rate_clks), + .fixed_rate_clks =3D hip04_fixed_rate_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hip04_fixed_rate_clks), +}; + +static const struct of_device_id hip04_clk_match_table[] =3D { + { .compatible =3D "hisilicon,hip04-clock", + .data =3D &hip04_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hip04_clk_match_table); + +static struct platform_driver hip04_clk_driver =3D { + .probe =3D hisi_clk_probe, + .remove =3D hisi_clk_remove, + .driver =3D { + .name =3D "hip04-clock", + .of_match_table =3D hip04_clk_match_table, + }, +}; =20 - clk_data =3D hisi_clk_init(np, HIP04_NR_CLKS); - if (!clk_data) - return; +module_platform_driver(hip04_clk_driver); =20 - hisi_clk_register_fixed_rate(hip04_fixed_rate_clks, - ARRAY_SIZE(hip04_fixed_rate_clks), - clk_data); -} -CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("HiSilicon HiP04 Clock Driver"); diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/cl= k-hix5hd2.c index 64bdd3f05725..f37a17649d26 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -4,13 +4,17 @@ * Copyright (c) 2014 Hisilicon Limited. */ =20 -#include #include + #include #include +#include +#include +#include + #include "clk.h" =20 -static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = =3D { +static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] =3D { { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, }, { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, }, @@ -43,19 +47,19 @@ static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_= clks[] __initdata =3D { { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, }, }; =20 -static const char *const sfc_mux_p[] __initconst =3D { +static const char *const sfc_mux_p[] =3D { "24m", "150m", "200m", "100m", "75m", }; static u32 sfc_mux_table[] =3D {0, 4, 5, 6, 7}; =20 -static const char *const sdio_mux_p[] __initconst =3D { +static const char *const sdio_mux_p[] =3D { "75m", "100m", "50m", "15m", }; static u32 sdio_mux_table[] =3D {0, 1, 2, 3}; =20 -static const char *const fephy_mux_p[] __initconst =3D { "25m", "125m"}; +static const char *const fephy_mux_p[] =3D { "25m", "125m"}; static u32 fephy_mux_table[] =3D {0, 1}; =20 =20 -static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata =3D { +static struct hisi_mux_clock hix5hd2_mux_clks[] =3D { { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p), CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, }, { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p), @@ -67,7 +71,7 @@ static struct hisi_mux_clock hix5hd2_mux_clks[] __initdat= a =3D { CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, }, }; =20 -static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata =3D { +static struct hisi_gate_clock hix5hd2_gate_clks[] =3D { /* sfc */ { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux", CLK_SET_RATE_PARENT, 0x5c, 0, 0, }, @@ -153,7 +157,7 @@ struct hix5hd2_clk_complex { u32 phy_rst_mask; }; =20 -static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata =3D { +static struct hix5hd2_complex_clock hix5hd2_complex_clks[] =3D { {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK, 0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER}, {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK, @@ -249,10 +253,11 @@ static const struct clk_ops clk_complex_ops =3D { .disable =3D clk_complex_disable, }; =20 -static void __init -hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, +static int +hix5hd2_clk_register_complex(struct device *dev, const void *clocks, int n= ums, struct hisi_clock_data *data) { + const struct hix5hd2_complex_clock *clks =3D clocks; void __iomem *base =3D data->base; int i; =20 @@ -263,7 +268,7 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_clo= ck *clks, int nums, =20 p_clk =3D kzalloc(sizeof(*p_clk), GFP_KERNEL); if (!p_clk) - return; + return -ENOMEM; =20 init.name =3D clks[i].name; if (clks[i].type =3D=3D TYPE_ETHER) @@ -289,31 +294,45 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_c= lock *clks, int nums, kfree(p_clk); pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(p_clk); } =20 data->clk_data.clks[clks[i].id] =3D clk; } -} =20 -static void __init hix5hd2_clk_init(struct device_node *np) -{ - struct hisi_clock_data *clk_data; - - clk_data =3D hisi_clk_init(np, HIX5HD2_NR_CLKS); - if (!clk_data) - return; - - hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks, - ARRAY_SIZE(hix5hd2_fixed_rate_clks), - clk_data); - hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), - clk_data); - hisi_clk_register_gate(hix5hd2_gate_clks, - ARRAY_SIZE(hix5hd2_gate_clks), clk_data); - hix5hd2_clk_register_complex(hix5hd2_complex_clks, - ARRAY_SIZE(hix5hd2_complex_clks), - clk_data); + return 0; } =20 -CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init); +static const struct hisi_clocks hix5hd2_clks =3D { + .nr =3D HIX5HD2_NR_CLKS, + .fixed_rate_clks =3D hix5hd2_fixed_rate_clks, + .fixed_factor_clks_num =3D ARRAY_SIZE(hix5hd2_fixed_rate_clks), + .mux_clks =3D hix5hd2_mux_clks, + .mux_clks_num =3D ARRAY_SIZE(hix5hd2_mux_clks), + .gate_clks =3D hix5hd2_gate_clks, + .gate_clks_num =3D ARRAY_SIZE(hix5hd2_gate_clks), + .customized_clks =3D hix5hd2_complex_clks, + .customized_clks_num =3D ARRAY_SIZE(hix5hd2_complex_clks), + .clk_register_customized =3D hix5hd2_clk_register_complex, +}; + +static const struct of_device_id hix5hd2_clk_match_table[] =3D { + { .compatible =3D "hisilicon,hix5hd2-clock", + .data =3D &hix5hd2_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, hix5hd2_clk_match_table); + +static struct platform_driver hix5hd2_clk_driver =3D { + .probe =3D hisi_clk_probe, + .remove =3D hisi_clk_remove, + .driver =3D { + .name =3D "hix5hd2-clock", + .of_match_table =3D hix5hd2_clk_match_table, + }, +}; + +module_platform_driver(hix5hd2_clk_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("HiSilicon Hix5hd2 Clock Driver"); --=20 2.39.2