From nobody Mon Apr 13 11:31:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21AFFC6FD20 for ; Fri, 24 Mar 2023 16:52:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231825AbjCXQwr (ORCPT ); Fri, 24 Mar 2023 12:52:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230471AbjCXQwn (ORCPT ); Fri, 24 Mar 2023 12:52:43 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D595A20A04 for ; Fri, 24 Mar 2023 09:52:42 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id dw14so1652285pfb.6 for ; Fri, 24 Mar 2023 09:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679676762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yryH7vC/nq+vPaNPZHPoVGq5Z2O/K90ppTi/YYO51JY=; b=kIIIpztVKyE5TXz0P71w7WJI5CmZz5r8zbxD43sBhuip0MZ7zB23xN35SkJY+xhzXO eyRs/LSQ6MknuWfh1pjW8hABr6NQjdoz3VZd0EDX5xJvzhaBFpK0cCFxbguwNKZmjTXa ju50zmTka9Y8mBIIS9sylBwGlI1aGTmctFZOPDoKg2Dq+/ZaiyRyRKR8MrkCbcmRry7L y/jjP9f2wRNbFoDD+JG+2avvTMjWpFKaoPi/1y6n/PqBsZcWNHoypqbySXVuMkh1iCbP 8RDdgVo9+yhglsNlqubZpyBJmvxMymK2kR2hhCb+eW9dGJt+IiSkoeHfV2MjA9Mc33Tn 6hKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679676762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yryH7vC/nq+vPaNPZHPoVGq5Z2O/K90ppTi/YYO51JY=; b=Zwmo2+DX7Ym979bb6Jioc94fkyivIoDPnrdAvK3MpOtlSrzbvCBuD3rvRwR6U6Fgbp fexRGTJDcNLhViT1D+XIAHUcG2PJCDIh3iEj6YnJ0Foy+nLgPFK+/sLdpVdmJUl4AXv8 Qw+8g+HWFlJaB8Q6UhQPKPyXVrNKgz/EEdDH8XCsTiMt7jiAmBhkL8d8m4dpPx2RB739 Eub3/r5R2IlkKN3OZWuLJX/APgrr45xU53M3ayj4UXoZYNVjAXcN5djyIJ7s4qm/xl8/ +VBWmQ2k+naM/GIBKGi+FUPPDX/8GtlsFv5r7KGr5U22gnewMv1Zy7zsPzWjq07kLkYG dh9g== X-Gm-Message-State: AAQBX9d+KsPzcZGCHoV7cXHx+WdyjGOOWrCTgBzgojxk1DsbQnDhvSQg rjKLzV6IavFu6gwEctP0lgWG4JGqBVY= X-Google-Smtp-Source: AKy350bdZI8qo/VNmxwZDUUT/YjFtDI61i5AdeQRwC50Zb+62VzNZq14Bqjo2Oh6M2OMpgyRifbKFA== X-Received: by 2002:a62:5254:0:b0:626:286d:b701 with SMTP id g81-20020a625254000000b00626286db701mr3768348pfb.20.1679676761902; Fri, 24 Mar 2023 09:52:41 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id a5-20020aa780c5000000b0062b5a55835dsm1420289pfn.213.2023.03.24.09.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 09:52:40 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Broadcom internal kernel review list , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 1/3] memory: brcmstb_memc: Cache configuration register value Date: Fri, 24 Mar 2023 09:52:29 -0700 Message-Id: <20230324165231.3468069-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230324165231.3468069-1-f.fainelli@gmail.com> References: <20230324165231.3468069-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The configuration register does not change once the DDR controller is configured, in preparation for providing more information about the DDR type/width in subsequent changes, store this value so we can retrieve it. Signed-off-by: Florian Fainelli --- drivers/memory/brcmstb_memc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c index 233a53f5bce1..67c75e21c95e 100644 --- a/drivers/memory/brcmstb_memc.c +++ b/drivers/memory/brcmstb_memc.c @@ -29,18 +29,15 @@ struct brcmstb_memc { struct device *dev; void __iomem *ddr_ctrl; unsigned int timeout_cycles; + u32 config_reg; u32 frequency; u32 srpd_offset; }; =20 static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc) { - void __iomem *config =3D memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG; - u32 reg; - - reg =3D readl_relaxed(config) & CNTRLR_CONFIG_MASK; - - return reg =3D=3D CNTRLR_CONFIG_LPDDR4_SHIFT; + return (memc->config_reg & CNTRLR_CONFIG_MASK) =3D=3D + CNTRLR_CONFIG_LPDDR4_SHIFT; } =20 static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc, @@ -148,6 +145,9 @@ static int brcmstb_memc_probe(struct platform_device *p= dev) of_property_read_u32(pdev->dev.of_node, "clock-frequency", &memc->frequency); =20 + memc->config_reg =3D readl_relaxed(memc->ddr_ctrl + + REG_MEMC_CNTRLR_CONFIG); + ret =3D sysfs_create_group(&dev->kobj, &dev_attr_group); if (ret) return ret; --=20 2.34.1 From nobody Mon Apr 13 11:31:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3868C6FD1C for ; Fri, 24 Mar 2023 16:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231840AbjCXQwu (ORCPT ); Fri, 24 Mar 2023 12:52:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231822AbjCXQwr (ORCPT ); Fri, 24 Mar 2023 12:52:47 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 381CC20A04 for ; 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Fri, 24 Mar 2023 09:52:42 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Broadcom internal kernel review list , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 2/3] Documentation: sysfs: brcmstb-memc: Document new attributes Date: Fri, 24 Mar 2023 09:52:30 -0700 Message-Id: <20230324165231.3468069-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230324165231.3468069-1-f.fainelli@gmail.com> References: <20230324165231.3468069-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the DDR rank, size, total size, width and type attributes. Signed-off-by: Florian Fainelli --- .../ABI/testing/sysfs-platform-brcmstb-memc | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-platform-brcmstb-memc b/Docume= ntation/ABI/testing/sysfs-platform-brcmstb-memc index 2f2b750ac2fd..bc969c02b85f 100644 --- a/Documentation/ABI/testing/sysfs-platform-brcmstb-memc +++ b/Documentation/ABI/testing/sysfs-platform-brcmstb-memc @@ -1,3 +1,42 @@ +What: /sys/bus/platform/devices/*/ddr_rank +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + Displays whether the device is single or dual rank. + +What: /sys/bus/platform/devices/*/ddr_size +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + This field specifies the size of each DRAM device in the first + (or only) rank + +What: /sys/bus/platform/devices/*/ddr_total_width +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + This field specifies the total data width of all DRAM devices + (in each rank) + +What: /sys/bus/platform/devices/*/ddr_type +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + This field specifies DRAM technology type. Possible values: + DDR2, DDR3, DDR4, GDDR5, GDDR5M, LPDDR4. + +What: /sys/bus/platform/devices/*/ddr_width +Date: March 2023 +KernelVersion: 6.3 +Contact: Florian Fainelli +Description: + This field specifies the data width of each DRAM device. + Possible values are: x8, x16, x32 + What: /sys/bus/platform/devices/*/srpd Date: July 2022 KernelVersion: 5.21 --=20 2.34.1 From nobody Mon Apr 13 11:31:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CBA3C6FD1C for ; Fri, 24 Mar 2023 16:52:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231866AbjCXQwy (ORCPT ); Fri, 24 Mar 2023 12:52:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231823AbjCXQwr (ORCPT ); Fri, 24 Mar 2023 12:52:47 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB3D3212A5 for ; Fri, 24 Mar 2023 09:52:45 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id i15so1646690pfo.8 for ; Fri, 24 Mar 2023 09:52:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679676765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8UmG7kTY7wjWcxkBXGijn5KqU6ZYb3Prx7pN3zRMZ2Q=; b=QVEqXaO0vwbg6qjXz3p/QiK0qIDvtFqAcZvJt3om0UyJ5+nosdtMGMbAVa/In6hj/w 0+ZwuC7B75j+g1KDkicEbZ7/Q/xWoHazfxg3v+uqOL3522+PaRj1VS0jSt3dF6L9rvM1 TXJipMfXePUNNeIEyhXzjjD19TU3PPhBTAl4uWKbrDj+i2eTgnmZZn4GDoa50RCZFmEB Tchet5lHEGcf+l4KoTxe8L9EdlqoYNgJ/SG7/OxNWuCPddbqZMXvNhuRW7Hrpl6NDO+D MH1DT7EVv/VXD+wlvHH0yJIA3OydtPXoDqcBGnZHYGbKt79L9kLk5DKAKycKKDn8wt4k iGBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679676765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8UmG7kTY7wjWcxkBXGijn5KqU6ZYb3Prx7pN3zRMZ2Q=; b=OvogoVifohIgRKXrdeaSNfanF+EXzpThJGu7PFTtBGoo/2O4GDrIuFN8GXE7zMFnhu qVSbP+JhSbQr3iNLBuZNvbTux2H22QrBzJZnsmVCZYQu8dpoA16AjG5B66HqxatPjIQn D1IhEzZu4bUN0lRIcBOabPE+XQNtT8XqcGq+PTmUgr+kZQwWCKwO1wHbOFx6zSf7OKLQ NxZyhHyzWoKT1y06xxfsb356NH9CyrBlfIfAA4jCTMG7IyrOF24GSSxdnkCUhLhsoXjD l6dCCHE0+4FCqFQNQbeVQs/rX2vuK5g/ZQH93IB2bQ3vKDOrBOfmSLmmcwbtCVqYANQY 4WbQ== X-Gm-Message-State: AAQBX9dI/24YCPJMA0a1MB2YtdKVgSCBSn9zXpAduRg2AaLzOnwSu15W XJSSgRkU0SSupN76rcDkyw2OOFrSBjQ= X-Google-Smtp-Source: AK7set+KBVxkxFHsXaMsVsIir/eox0dKYMv1EYMazIh/KAM89fItbtAbbbylsEN1+4M6KgzY6HlOlw== X-Received: by 2002:aa7:9629:0:b0:628:1274:4d60 with SMTP id r9-20020aa79629000000b0062812744d60mr3776739pfg.21.1679676764785; Fri, 24 Mar 2023 09:52:44 -0700 (PDT) Received: from fainelli-desktop.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id a5-20020aa780c5000000b0062b5a55835dsm1420289pfn.213.2023.03.24.09.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 09:52:44 -0700 (PDT) From: Florian Fainelli To: linux-kernel@vger.kernel.org Cc: Florian Fainelli , Broadcom internal kernel review list , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE) Subject: [PATCH 3/3] memory: brcmstb_memc: Add new DDR attributes Date: Fri, 24 Mar 2023 09:52:31 -0700 Message-Id: <20230324165231.3468069-4-f.fainelli@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230324165231.3468069-1-f.fainelli@gmail.com> References: <20230324165231.3468069-1-f.fainelli@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Provide information about the DDR size, type, width, total width, dual/single rank. This is useful for reporting purposes and inventory of the system(s). Signed-off-by: Florian Fainelli --- drivers/memory/brcmstb_memc.c | 80 ++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c index 67c75e21c95e..032567dfd6e2 100644 --- a/drivers/memory/brcmstb_memc.c +++ b/drivers/memory/brcmstb_memc.c @@ -13,7 +13,14 @@ =20 #define REG_MEMC_CNTRLR_CONFIG 0x00 #define CNTRLR_CONFIG_LPDDR4_SHIFT 5 -#define CNTRLR_CONFIG_MASK 0xf +#define CNTRLR_CONFIG_MASK GENMASK(3, 0) +#define CNTRLR_CONFIG_SIZE_SHIFT 4 +#define CNTRLR_CONFIG_SIZE_MASK GENMASK(7, 4) +#define CNTRLR_CONFIG_WIDTH_SHIFT 8 +#define CNTRLR_CONFIG_WIDTH_MASK GENMASK(9, 8) +#define CNTRLR_CONFIG_TOT_WIDTH_SHIFT 10 +#define CNTRLR_CONFIG_TOT_WIDTH_MASK GENMASK(11, 10) +#define CNTRLR_CONFIG_RANK_SHIFT 16 #define REG_MEMC_SRPD_CFG_21 0x20 #define REG_MEMC_SRPD_CFG_20 0x34 #define REG_MEMC_SRPD_CFG_1x 0x3c @@ -63,6 +70,67 @@ static int brcmstb_memc_srpd_config(struct brcmstb_memc = *memc, return 0; } =20 +static ssize_t ddr_rank_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc =3D dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", + memc->config_reg & CNTRLR_CONFIG_RANK_SHIFT ? + "dual" : "single"); +} + +static ssize_t ddr_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc =3D dev_get_drvdata(dev); + u32 val =3D (memc->config_reg & CNTRLR_CONFIG_SIZE_MASK) >> + CNTRLR_CONFIG_SIZE_SHIFT; + + return sprintf(buf, "%dMb\n", 256 << val); +} + +static ssize_t ddr_total_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc =3D dev_get_drvdata(dev); + u32 val =3D (memc->config_reg & CNTRLR_CONFIG_TOT_WIDTH_MASK) >> + CNTRLR_CONFIG_TOT_WIDTH_SHIFT; + + return sprintf(buf, "x%d\n", 8 << val); +} + +static ssize_t ddr_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc =3D dev_get_drvdata(dev); + const char *ddr_type_to_str[] =3D { + "DDR2", + "DDR3", + "DDR4", + "GDDR5M", + "GDDR5", + "LPDDR4", + }; + u32 val =3D memc->config_reg & CNTRLR_CONFIG_MASK; + const char *type =3D "unknown"; + + if (val < ARRAY_SIZE(ddr_type_to_str)) + type =3D ddr_type_to_str[val]; + + return sprintf(buf, "%s\n", type); +} + +static ssize_t ddr_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc =3D dev_get_drvdata(dev); + u32 val =3D (memc->config_reg & CNTRLR_CONFIG_WIDTH_MASK) >> + CNTRLR_CONFIG_WIDTH_SHIFT; + + return sprintf(buf, "x%d\n", 8 << val); +} + static ssize_t frequency_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -105,10 +173,20 @@ static ssize_t srpd_store(struct device *dev, struct = device_attribute *attr, return count; } =20 +static DEVICE_ATTR_RO(ddr_rank); +static DEVICE_ATTR_RO(ddr_size); +static DEVICE_ATTR_RO(ddr_total_width); +static DEVICE_ATTR_RO(ddr_type); +static DEVICE_ATTR_RO(ddr_width); static DEVICE_ATTR_RO(frequency); static DEVICE_ATTR_RW(srpd); =20 static struct attribute *dev_attrs[] =3D { + &dev_attr_ddr_rank.attr, + &dev_attr_ddr_size.attr, + &dev_attr_ddr_total_width.attr, + &dev_attr_ddr_type.attr, + &dev_attr_ddr_width.attr, &dev_attr_frequency.attr, &dev_attr_srpd.attr, NULL, --=20 2.34.1