From nobody Sun Sep 14 07:40:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13D1AC6FD1C for ; Fri, 24 Mar 2023 15:55:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232178AbjCXPzf (ORCPT ); Fri, 24 Mar 2023 11:55:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229945AbjCXPzc (ORCPT ); Fri, 24 Mar 2023 11:55:32 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAE8B1E5E1 for ; Fri, 24 Mar 2023 08:55:31 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id h17so2287376wrt.8 for ; Fri, 24 Mar 2023 08:55:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1679673330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tp3HoPN4Gc82+RijS+v6sxY9JgB+vr3DxCDQErkACNI=; b=ZWNhHoXsX43350iih+wD2VNFUpSmPZg3GoR5+pdNWLoUbl7wO5tfkt7YCB3poRYl8m QKSnyLjo+RRmDEJN3/k3T0mFwzkstsnUrvxIbT4zvwl2sHXeUOWBGBxGM6CCneBRAH8h hInUCCtT4YIpqv1pG3b1V7EMYdJI+JHKt+HkFcEiECEXJJ7Eac3jDBUEciRtu5JnJ9P2 3TQpRwkH2qpr9pW05hvbeHJLEoYl76Gd8emmbghk/tOJF2k3L8T45BKZZ36DMpuM/iRo hEy9lrCMYSMC1vVFvsPgI289oVnGc80AOZvfRdGJURQiohqSFW+zGiatqjGAAD8L8js3 Mv5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679673330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tp3HoPN4Gc82+RijS+v6sxY9JgB+vr3DxCDQErkACNI=; b=EzM85cNMkDTqWILfoPiZ9/qypkN3lnmV+gINqTbXtrFnVVyLE7YXxgRijJmU+HSoPp 3lT2jeN6AE0XPYo5jz6AJvyVToTy0l+wAjKkKyVPFx3bqVmPpyXMq/OBfDwtH//9N1FX gpMjZEFLJgpuVD8udENWt4+JC2x9oo5W2FScXX6ARc6aqAxki19tJyHoBK0Z1Ywel0M9 RVaw97HEvP0vbBHq8EMYQhU+D3f8Y0EglZy0716K2RyOreqINUnoUsujwiPDlZuhlCyh Ld/fUc59BMFNRuWoI+BFxgIOXWpHr5XSMDAuSKg0r4MOmnZtyRj24CerVJRjeMOLVrNf ebLQ== X-Gm-Message-State: AAQBX9fwUdkuke1yG5YM8nZNCx7qdVQ+6/hMRIuqB+z7+0YymXf0IXep 3PqBzHkCdFI3G1+GMSEkK5YL1g== X-Google-Smtp-Source: AKy350ak7ygxOxi4tYX8LpUVbV5mkgHWSgSVhi5JP6SXzo1OaZPV4mcFr7AfECSFJWF0WAqOGrpbnw== X-Received: by 2002:a5d:4809:0:b0:2ce:ae4c:c424 with SMTP id l9-20020a5d4809000000b002ceae4cc424mr3047287wrq.4.1679673330170; Fri, 24 Mar 2023 08:55:30 -0700 (PDT) Received: from alex-rivos.home (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id m8-20020a5d4a08000000b002c3f03d8851sm18571070wrq.16.2023.03.24.08.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 08:55:29 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Frank Rowand , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v9 1/3] riscv: Get rid of riscv_pfn_base variable Date: Fri, 24 Mar 2023 16:54:19 +0100 Message-Id: <20230324155421.271544-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230324155421.271544-1-alexghiti@rivosinc.com> References: <20230324155421.271544-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use directly phys_ram_base instead, riscv_pfn_base is just the pfn of the address contained in phys_ram_base. Even if there is no functional change intended in this patch, actually setting phys_ram_base that early changes the behaviour of kernel_mapping_pa_to_va during the early boot: phys_ram_base used to be zero before this patch and now it is set to the physical start address of the kernel. But it does not break the conversion of a kernel physical address into a virtual address since kernel_mapping_pa_to_va should only be used on kernel physical addresses, i.e. addresses greater than the physical start address of the kernel. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Tested-by: Anup Patel --- arch/riscv/include/asm/page.h | 3 +-- arch/riscv/mm/init.c | 6 +----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 7fed7c431928..8dc686f549b6 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -91,8 +91,7 @@ typedef struct page *pgtable_t; #endif =20 #ifdef CONFIG_MMU -extern unsigned long riscv_pfn_base; -#define ARCH_PFN_OFFSET (riscv_pfn_base) +#define ARCH_PFN_OFFSET (PFN_DOWN((unsigned long)phys_ram_base)) #else #define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) #endif /* CONFIG_MMU */ diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 87f6a5d475a6..cc558d94559a 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -271,9 +271,6 @@ static void __init setup_bootmem(void) #ifdef CONFIG_MMU struct pt_alloc_ops pt_ops __initdata; =20 -unsigned long riscv_pfn_base __ro_after_init; -EXPORT_SYMBOL(riscv_pfn_base); - pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss; pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss; static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss; @@ -285,7 +282,6 @@ static pmd_t __maybe_unused early_dtb_pmd[PTRS_PER_PMD]= __initdata __aligned(PAG =20 #ifdef CONFIG_XIP_KERNEL #define pt_ops (*(struct pt_alloc_ops *)XIP_FIXUP(&pt_ops)) -#define riscv_pfn_base (*(unsigned long *)XIP_FIXUP(&riscv_pfn_ba= se)) #define trampoline_pg_dir ((pgd_t *)XIP_FIXUP(trampoline_pg_dir)) #define fixmap_pte ((pte_t *)XIP_FIXUP(fixmap_pte)) #define early_pg_dir ((pgd_t *)XIP_FIXUP(early_pg_dir)) @@ -985,7 +981,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) kernel_map.va_pa_offset =3D PAGE_OFFSET - kernel_map.phys_addr; kernel_map.va_kernel_pa_offset =3D kernel_map.virt_addr - kernel_map.phys= _addr; =20 - riscv_pfn_base =3D PFN_DOWN(kernel_map.phys_addr); + phys_ram_base =3D kernel_map.phys_addr; =20 /* * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit --=20 2.37.2 From nobody Sun Sep 14 07:40:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04217C6FD1C for ; Fri, 24 Mar 2023 15:56:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231686AbjCXP4h (ORCPT ); Fri, 24 Mar 2023 11:56:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231614AbjCXP4e (ORCPT ); Fri, 24 Mar 2023 11:56:34 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E63A510A87 for ; Fri, 24 Mar 2023 08:56:32 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id h17so2290407wrt.8 for ; Fri, 24 Mar 2023 08:56:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1679673391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PR0MUUfacwAfsjInBPeABoZtOXtMYsQVXBaBrC8rWtM=; b=R3kCrQe6UqEb7GoCrQ19E+2HaE0y0+lHYsucNBd+vyoWzCdTuw80+N+fDn3B4o+dGG c3qMMwW7jNWTEIdDu0/u2KtnYi8Z4faTZC28TPwx77lPhfWdPjP83tGua6o+w7itsWnj mC3HDqQJuuf8k7AgnKbGbTX8y5ZXhA9Uh6RAgNkZxDP5De3aTBcrTXt7lCao9xGz/62i yRsIEErfZ8vqKRQmmBfipn3Wt25HXQtH2CQiOzoIT8RAc6LVYIvxgM6UkQ6h+FLqnKVY FeppzjVOse3GnyvmI1Qms9N0XKZuOPfDfWF4JwwjWlS/x8DIws6pR1+HOABy/Yzj8yLu jggg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679673391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PR0MUUfacwAfsjInBPeABoZtOXtMYsQVXBaBrC8rWtM=; b=eeZDf6AYM7OaNgdmAj8C2xc/IiDBMnmLAuiE917jvJFSu5UsQd5LooxYWX7W8B9MII qnX1KTm0npSDWt3atCcFQoPBeoqQgOx/f1HtCQZeDhobCtXj8sJaFEgSG8PWFC/+6Xd1 4QEtEMV+BpJf29aByEBufWd52edxmsusq51NbTaawVU8+AyprIgFWy/e75TtDE8nP7Yn THnKr/Ac48s8ExQa00eVZJheYjl5uaZBdB9AYkI6Y5aVo38DOwYLbE3hwzwSTMk32TyG GPavuupWql/QoWPCa0srcDxpwkIvYIIVAcN50avvGxBoH/HgC8mjuPXOX67LKbvtEBDi y/+w== X-Gm-Message-State: AAQBX9fDjXu1EWWTcs5oJ50SyUyF87dNeTWyisnVdGvGPn70qFqU3x7M mV81+ow8Aq2A0tTc2mKjzuQdGg== X-Google-Smtp-Source: AKy350ZbYATQfNEPjI55Pl0fHAqYJaEDna5Eve19pmNEhT+ETLFt3/hTIE34PKB7xqhm0hzFTkzAsw== X-Received: by 2002:adf:fe41:0:b0:2cf:e517:c138 with SMTP id m1-20020adffe41000000b002cfe517c138mr2687659wrs.66.1679673391487; Fri, 24 Mar 2023 08:56:31 -0700 (PDT) Received: from alex-rivos.home (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id d7-20020adffbc7000000b002d5a8d8442asm14382912wrs.37.2023.03.24.08.56.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 08:56:31 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Frank Rowand , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v9 2/3] riscv: Move the linear mapping creation in its own function Date: Fri, 24 Mar 2023 16:54:20 +0100 Message-Id: <20230324155421.271544-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230324155421.271544-1-alexghiti@rivosinc.com> References: <20230324155421.271544-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" No change intended, it just splits the linear mapping creation from setup_vm_final: this prepares for upcoming additions to the linear mapping creation. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Tested-by: Anup Patel --- arch/riscv/mm/init.c | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index cc558d94559a..3b37d8606920 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -1086,16 +1086,25 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) pt_ops_set_fixmap(); } =20 -static void __init setup_vm_final(void) +static void __init create_linear_mapping_range(phys_addr_t start, + phys_addr_t end) { + phys_addr_t pa; uintptr_t va, map_size; - phys_addr_t pa, start, end; - u64 i; =20 - /* Setup swapper PGD for fixmap */ - create_pgd_mapping(swapper_pg_dir, FIXADDR_START, - __pa_symbol(fixmap_pgd_next), - PGDIR_SIZE, PAGE_TABLE); + for (pa =3D start; pa < end; pa +=3D map_size) { + va =3D (uintptr_t)__va(pa); + map_size =3D best_map_size(pa, end - pa); + + create_pgd_mapping(swapper_pg_dir, va, pa, map_size, + pgprot_from_va(va)); + } +} + +static void __init create_linear_mapping_page_table(void) +{ + phys_addr_t start, end; + u64 i; =20 /* Map all memory banks in the linear mapping */ for_each_mem_range(i, &start, &end) { @@ -1107,14 +1116,19 @@ static void __init setup_vm_final(void) if (end >=3D __pa(PAGE_OFFSET) + memory_limit) end =3D __pa(PAGE_OFFSET) + memory_limit; =20 - for (pa =3D start; pa < end; pa +=3D map_size) { - va =3D (uintptr_t)__va(pa); - map_size =3D best_map_size(pa, end - pa); - - create_pgd_mapping(swapper_pg_dir, va, pa, map_size, - pgprot_from_va(va)); - } + create_linear_mapping_range(start, end); } +} + +static void __init setup_vm_final(void) +{ + /* Setup swapper PGD for fixmap */ + create_pgd_mapping(swapper_pg_dir, FIXADDR_START, + __pa_symbol(fixmap_pgd_next), + PGDIR_SIZE, PAGE_TABLE); + + /* Map the linear mapping */ + create_linear_mapping_page_table(); =20 /* Map the kernel */ if (IS_ENABLED(CONFIG_64BIT)) --=20 2.37.2 From nobody Sun Sep 14 07:40:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 789A6C6FD1C for ; Fri, 24 Mar 2023 15:57:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231461AbjCXP5k (ORCPT ); Fri, 24 Mar 2023 11:57:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232151AbjCXP5h (ORCPT ); Fri, 24 Mar 2023 11:57:37 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE57F1E5E1 for ; Fri, 24 Mar 2023 08:57:33 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id v1so2319367wrv.1 for ; Fri, 24 Mar 2023 08:57:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1679673452; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zhhEYFPCPVqM+bv/vdKyIuWfXi+AjGplPQmUGopcOcU=; b=m3WT+FNIduuiQuRRQK2gEavpehgueTGx9br5jILqJam7WzWuSCoSPo70Vaz7WrYBFt +HFMqSyA/nMVG4EKyFRyElCmY5Nie3HcgRSGEi3jmHn5KN7ohI6QKhZOaVmtHfUKgNud M5/SrhKd3BLN/ZcRChD/whjG8SIpO4w3gtuXl/PIMiGPSE7RrTVgHNXG4No7leGMQRSF 2cPN4OBEwwOYFmt7K0UVK/yopyZAaaq2DOxf6l/fzvVYIoL3GxNS1YqIfr1L7nSLsM0I p2xjtt2YI6AP5y+I55Pa7/ddwecKFUmQHaiXaUsXAofsELfar9qoEg/M3IrnW+6cg7tl R9EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679673452; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zhhEYFPCPVqM+bv/vdKyIuWfXi+AjGplPQmUGopcOcU=; b=r/faxCWycqQCaTWCuu2XI7zx7wON+UBYuApc09TkjqJVeNSIKC2Oo5hNi1/zgA5ziJ Gyn3PQqebWHvsz4Lrjt+Iq/SCyJ5n+EdzzVo/aRySACO/aivd0gD5b+iGYw+bn/TBK88 GwL/jYzMPs/tEGt0Z1rvi3QoLCxvolAyouo46WMAzWNPhl+fyKvKh9M8NxhnHhXtkseW 5ndub5dZiXdD6LiGUdpE9YTCUFdnsTfLOgNICkhiGMMHnvSXZB94LbuDUdSQj7pin1IZ GE+ne7Aqe4c+HQuDztJ9TMAjpbi5Q5Uqna5VnsRaE5lKZqhAjYZKrDGhdXha+8DHxcEQ SH9Q== X-Gm-Message-State: AAQBX9cxBetvSd7TmTOHs8o/3hlqliWenJfqR+1uAXhCV1ag3h3AGpKj pnXNxwMhGWl9Y3SPgb+qnqSLwQ== X-Google-Smtp-Source: AKy350ZKFS9Zknv3kJTbWN0OS/rVhFjsRCqh2HsrZErz2y8l5F7eehLZBdmucO6ButWIk1v8iCKvAA== X-Received: by 2002:adf:e64d:0:b0:2c5:4af3:3d26 with SMTP id b13-20020adfe64d000000b002c54af33d26mr2912903wrn.9.1679673452317; Fri, 24 Mar 2023 08:57:32 -0700 (PDT) Received: from alex-rivos.home (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id w2-20020a5d6082000000b002c6d0462163sm18580112wrt.100.2023.03.24.08.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Mar 2023 08:57:32 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Frank Rowand , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Alexandre Ghiti , Rob Herring Subject: [PATCH v9 3/3] riscv: Use PUD/P4D/PGD pages for the linear mapping Date: Fri, 24 Mar 2023 16:54:21 +0100 Message-Id: <20230324155421.271544-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230324155421.271544-1-alexghiti@rivosinc.com> References: <20230324155421.271544-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" During the early page table creation, we used to set the mapping for PAGE_OFFSET to the kernel load address: but the kernel load address is always offseted by PMD_SIZE which makes it impossible to use PUD/P4D/PGD pages as this physical address is not aligned on PUD/P4D/PGD size (whereas PAGE_OFFSET is). But actually we don't have to establish this mapping (ie set va_pa_offset) that early in the boot process because: - first, setup_vm installs a temporary kernel mapping and among other things, discovers the system memory, - then, setup_vm_final creates the final kernel mapping and takes advantage of the discovered system memory to create the linear mapping. During the first phase, we don't know the start of the system memory and then until the second phase is finished, we can't use the linear mapping at all and phys_to_virt/virt_to_phys translations must not be used because it would result in a different translation from the 'real' one once the final mapping is installed. So here we simply delay the initialization of va_pa_offset to after the system memory discovery. But to make sure noone uses the linear mapping before, we add some guard in the DEBUG_VIRTUAL config. Finally we can use PUD/P4D/PGD hugepages when possible, which will result in a better TLB utilization. Note that: - this does not apply to rv32 as the kernel mapping lies in the linear mapping. - we rely on the firmware to protect itself using PMP. Signed-off-by: Alexandre Ghiti Acked-by: Rob Herring # DT bits Reviewed-by: Andrew Jones Reviewed-by: Anup Patel Tested-by: Anup Patel --- arch/riscv/include/asm/page.h | 16 ++++++++++ arch/riscv/mm/init.c | 58 +++++++++++++++++++++++++++++++---- arch/riscv/mm/physaddr.c | 16 ++++++++++ drivers/of/fdt.c | 11 ++++--- 4 files changed, 90 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 8dc686f549b6..ea1a0e237211 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -90,6 +90,14 @@ typedef struct page *pgtable_t; #define PTE_FMT "%08lx" #endif =20 +#ifdef CONFIG_64BIT +/* + * We override this value as its generic definition uses __pa too early in + * the boot process (before kernel_map.va_pa_offset is set). + */ +#define MIN_MEMBLOCK_ADDR 0 +#endif + #ifdef CONFIG_MMU #define ARCH_PFN_OFFSET (PFN_DOWN((unsigned long)phys_ram_base)) #else @@ -121,7 +129,11 @@ extern phys_addr_t phys_ram_base; #define is_linear_mapping(x) \ ((x) >=3D PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < PAGE_OFFSET = + KERN_VIRT_SIZE)) =20 +#ifndef CONFIG_DEBUG_VIRTUAL #define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + kernel_m= ap.va_pa_offset)) +#else +void *linear_mapping_pa_to_va(unsigned long x); +#endif #define kernel_mapping_pa_to_va(y) ({ \ unsigned long _y =3D (unsigned long)(y); \ (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ? \ @@ -130,7 +142,11 @@ extern phys_addr_t phys_ram_base; }) #define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x) =20 +#ifndef CONFIG_DEBUG_VIRTUAL #define linear_mapping_va_to_pa(x) ((unsigned long)(x) - kernel_map.va_pa_= offset) +#else +phys_addr_t linear_mapping_va_to_pa(unsigned long x); +#endif #define kernel_mapping_va_to_pa(y) ({ \ unsigned long _y =3D (unsigned long)(y); \ (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET)= ? \ diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 3b37d8606920..f803671d18b2 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -213,6 +213,14 @@ static void __init setup_bootmem(void) phys_ram_end =3D memblock_end_of_DRAM(); if (!IS_ENABLED(CONFIG_XIP_KERNEL)) phys_ram_base =3D memblock_start_of_DRAM(); + + /* + * In 64-bit, any use of __va/__pa before this point is wrong as we + * did not know the start of DRAM before. + */ + if (IS_ENABLED(CONFIG_64BIT)) + kernel_map.va_pa_offset =3D PAGE_OFFSET - phys_ram_base; + /* * memblock allocator is not aware of the fact that last 4K bytes of * the addressable memory can not be mapped because of IS_ERR_VALUE @@ -667,9 +675,16 @@ void __init create_pgd_mapping(pgd_t *pgdp, =20 static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) { - /* Upgrade to PMD_SIZE mappings whenever possible */ - base &=3D PMD_SIZE - 1; - if (!base && size >=3D PMD_SIZE) + if (!(base & (PGDIR_SIZE - 1)) && size >=3D PGDIR_SIZE) + return PGDIR_SIZE; + + if (!(base & (P4D_SIZE - 1)) && size >=3D P4D_SIZE) + return P4D_SIZE; + + if (!(base & (PUD_SIZE - 1)) && size >=3D PUD_SIZE) + return PUD_SIZE; + + if (!(base & (PMD_SIZE - 1)) && size >=3D PMD_SIZE) return PMD_SIZE; =20 return PAGE_SIZE; @@ -978,11 +993,22 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) set_satp_mode(); #endif =20 - kernel_map.va_pa_offset =3D PAGE_OFFSET - kernel_map.phys_addr; + /* + * In 64-bit, we defer the setup of va_pa_offset to setup_bootmem, + * where we have the system memory layout: this allows us to align + * the physical and virtual mappings and then make use of PUD/P4D/PGD + * for the linear mapping. This is only possible because the kernel + * mapping lies outside the linear mapping. + * In 32-bit however, as the kernel resides in the linear mapping, + * setup_vm_final can not change the mapping established here, + * otherwise the same kernel addresses would get mapped to different + * physical addresses (if the start of dram is different from the + * kernel physical address start). + */ + kernel_map.va_pa_offset =3D IS_ENABLED(CONFIG_64BIT) ? + 0UL : PAGE_OFFSET - kernel_map.phys_addr; kernel_map.va_kernel_pa_offset =3D kernel_map.virt_addr - kernel_map.phys= _addr; =20 - phys_ram_base =3D kernel_map.phys_addr; - /* * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit * kernel, whereas for 64-bit kernel, the end of the virtual address @@ -1106,6 +1132,17 @@ static void __init create_linear_mapping_page_table(= void) phys_addr_t start, end; u64 i; =20 +#ifdef CONFIG_STRICT_KERNEL_RWX + phys_addr_t ktext_start =3D __pa_symbol(_start); + phys_addr_t ktext_size =3D __init_data_begin - _start; + phys_addr_t krodata_start =3D __pa_symbol(__start_rodata); + phys_addr_t krodata_size =3D _data - __start_rodata; + + /* Isolate kernel text and rodata so they don't get mapped with a PUD */ + memblock_mark_nomap(ktext_start, ktext_size); + memblock_mark_nomap(krodata_start, krodata_size); +#endif + /* Map all memory banks in the linear mapping */ for_each_mem_range(i, &start, &end) { if (start >=3D end) @@ -1118,6 +1155,15 @@ static void __init create_linear_mapping_page_table(= void) =20 create_linear_mapping_range(start, end); } + +#ifdef CONFIG_STRICT_KERNEL_RWX + create_linear_mapping_range(ktext_start, ktext_start + ktext_size); + create_linear_mapping_range(krodata_start, + krodata_start + krodata_size); + + memblock_clear_nomap(ktext_start, ktext_size); + memblock_clear_nomap(krodata_start, krodata_size); +#endif } =20 static void __init setup_vm_final(void) diff --git a/arch/riscv/mm/physaddr.c b/arch/riscv/mm/physaddr.c index 9b18bda74154..18706f457da7 100644 --- a/arch/riscv/mm/physaddr.c +++ b/arch/riscv/mm/physaddr.c @@ -33,3 +33,19 @@ phys_addr_t __phys_addr_symbol(unsigned long x) return __va_to_pa_nodebug(x); } EXPORT_SYMBOL(__phys_addr_symbol); + +phys_addr_t linear_mapping_va_to_pa(unsigned long x) +{ + BUG_ON(!kernel_map.va_pa_offset); + + return ((unsigned long)(x) - kernel_map.va_pa_offset); +} +EXPORT_SYMBOL(linear_mapping_va_to_pa); + +void *linear_mapping_pa_to_va(unsigned long x) +{ + BUG_ON(!kernel_map.va_pa_offset); + + return ((void *)((unsigned long)(x) + kernel_map.va_pa_offset)); +} +EXPORT_SYMBOL(linear_mapping_pa_to_va); diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index d1a68b6d03b3..d14735a81301 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -887,12 +887,13 @@ const void * __init of_flat_dt_match_machine(const vo= id *default_match, static void __early_init_dt_declare_initrd(unsigned long start, unsigned long end) { - /* ARM64 would cause a BUG to occur here when CONFIG_DEBUG_VM is - * enabled since __va() is called too early. ARM64 does make use - * of phys_initrd_start/phys_initrd_size so we can skip this - * conversion. + /* + * __va() is not yet available this early on some platforms. In that + * case, the platform uses phys_initrd_start/phys_initrd_size instead + * and does the VA conversion itself. */ - if (!IS_ENABLED(CONFIG_ARM64)) { + if (!IS_ENABLED(CONFIG_ARM64) && + !(IS_ENABLED(CONFIG_RISCV) && IS_ENABLED(CONFIG_64BIT))) { initrd_start =3D (unsigned long)__va(start); initrd_end =3D (unsigned long)__va(end); initrd_below_start_ok =3D 1; --=20 2.37.2