From nobody Sat Sep 21 00:01:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 102DBC77B60 for ; Fri, 24 Mar 2023 02:13:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231305AbjCXCNS (ORCPT ); Thu, 23 Mar 2023 22:13:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230016AbjCXCNO (ORCPT ); Thu, 23 Mar 2023 22:13:14 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 427A6298D5; Thu, 23 Mar 2023 19:13:08 -0700 (PDT) X-UUID: 6771e2cec9e911eda9a90f0bb45854f4-20230324 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Q9cstHFLJ+gx/qArsmu2CV4neaUdrgqVB6Ig+yYspwo=; b=DgwOjmGEgy0OKtKHAnX8bXAt+L8+6l4bekUd4lOSX1vSueyNE6SH+SodiYkLQYjqzFnZyZyGRFnzFrB0XgjyI0P1doF8GqudGNKVTp5YE+TUBhIWqG5JcLuBwdoGYhYlrtztq/vjiy+SPJ5GbGPn8a72GbRZB+2jqQXoB8c8ClY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:5c204a7e-d9f8-4a1b-aadf-270607f79de4,IP:0,U RL:0,TC:0,Content:0,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-30 X-CID-META: VersionHash:120426c,CLOUDID:8a4f34b4-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 6771e2cec9e911eda9a90f0bb45854f4-20230324 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1532918422; Fri, 24 Mar 2023 10:13:01 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 24 Mar 2023 10:13:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 24 Mar 2023 10:13:00 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v5 1/6] arm64: dts: mediatek: mt8186: Add MTU3 nodes Date: Fri, 24 Mar 2023 10:12:53 +0800 Message-ID: <20230324021258.15863-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> References: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MTU3 nodes for MT8186 SoC. Signed-off-by: Allen-KH Cheng Tested-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index a0d3e1f731bd..178421fd8380 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -981,6 +981,40 @@ status =3D "disabled"; }; =20 + ssusb0: usb@11201000 { + compatible =3D "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts =3D ; + phys =3D <&u2port0 PHY_TYPE_USB2>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_SSUSB>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host0: usb@11200000 { + compatible =3D "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11200000 0 0x1000>; + reg-names =3D "mac"; + clocks =3D <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts =3D ; + mediatek,syscon-wakeup =3D <&pericfg 0x420 2>; + wakeup-source; + status =3D "disabled"; + }; + }; + mmc0: mmc@11230000 { compatible =3D "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; @@ -1012,6 +1046,40 @@ status =3D "disabled"; }; =20 + ssusb1: usb@11281000 { + compatible =3D "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg =3D <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; + reg-names =3D "mac", "ippc"; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts =3D ; + phys =3D <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + usb_host1: usb@11280000 { + compatible =3D "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg =3D <0 0x11280000 0 0x1000>; + reg-names =3D "mac"; + clocks =3D <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names =3D "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; + interrupts =3D ; + mediatek,syscon-wakeup =3D <&pericfg 0x424 2>; + wakeup-source; + status =3D "disabled"; + }; + }; + u3phy0: t-phy@11c80000 { compatible =3D "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2"; --=20 2.18.0 From nobody Sat Sep 21 00:01:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05955C74A5B for ; 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Fri, 24 Mar 2023 10:13:02 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 24 Mar 2023 10:13:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 24 Mar 2023 10:13:01 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v5 2/6] dt-bindings: spmi: spmi-mtk-pmif: Document mediatek,mt8195-spmi as fallback of mediatek,mt8186-spmi Date: Fri, 24 Mar 2023 10:12:54 +0800 Message-ID: <20230324021258.15863-3-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> References: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mt8186-spmi is used as compatible with mt8195-spmi on the MT8186, document this situation. Signed-off-by: Allen-KH Cheng Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml = b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml index abcbbe13723f..e4f465abcfe9 100644 --- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -18,9 +18,14 @@ allOf: =20 properties: compatible: - enum: - - mediatek,mt6873-spmi - - mediatek,mt8195-spmi + oneOf: + - enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + - items: + - enum: + - mediatek,mt8186-spmi + - const: mediatek,mt8195-spmi =20 reg: maxItems: 2 --=20 2.18.0 From nobody Sat Sep 21 00:01:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6D55C761AF for ; Fri, 24 Mar 2023 02:13:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231317AbjCXCNU (ORCPT ); Thu, 23 Mar 2023 22:13:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231183AbjCXCNP (ORCPT ); Thu, 23 Mar 2023 22:13:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBA3011666; Thu, 23 Mar 2023 19:13:11 -0700 (PDT) X-UUID: 67c5a36ec9e911edb6b9f13eb10bd0fe-20230324 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=v4C/c+coZf632gYlNNtB8sYdI1ZF+6VwQghIMiH1Nmw=; b=DYibyXi4zKMHZz4rDfr/Ophzs1S4IImpkgpUzzDkKM3ZDos9JrzxXyW7l+ygBteobnpZlc8TlE0MqRgpB1alVrWVet4QH157OcVcpYGI5XLiYjbQuQtOGDPkX+LJs9KyAQG9hbNqbFhctzAR5p8u9k1FkS/t7vZa0RtgTo4CBWw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:949a303d-37a6-42a1-9580-e75c357d8e06,IP:0,U RL:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-35 X-CID-META: VersionHash:120426c,CLOUDID:ede0c1f6-ddba-41c3-91d9-10eeade8eac7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 67c5a36ec9e911edb6b9f13eb10bd0fe-20230324 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 610021462; Fri, 24 Mar 2023 10:13:02 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 24 Mar 2023 10:13:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 24 Mar 2023 10:13:01 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v5 3/6] arm64: dts: mediatek: mt8186: Add SPMI node Date: Fri, 24 Mar 2023 10:12:55 +0800 Message-ID: <20230324021258.15863-4-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> References: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add SPMI node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 178421fd8380..0e42bdbd2cb6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -602,6 +602,21 @@ clock-names =3D "spi", "wrap"; }; =20 + spmi: spmi@10015000 { + compatible =3D "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; + reg =3D <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; + reg-names =3D "pmif", "spmimst"; + clocks =3D <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST>; + clock-names =3D "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + assigned-clocks =3D <&topckgen CLK_TOP_SPMI_MST>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ULPOSC1_D10>; + interrupts =3D , + ; + status =3D "disabled"; + }; + systimer: timer@10017000 { compatible =3D "mediatek,mt8186-timer", "mediatek,mt6765-timer"; --=20 2.18.0 From nobody Sat Sep 21 00:01:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73A5BC74A5B for ; Fri, 24 Mar 2023 02:13:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231355AbjCXCNX (ORCPT ); Thu, 23 Mar 2023 22:13:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231278AbjCXCNQ (ORCPT ); Thu, 23 Mar 2023 22:13:16 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF20B298EF; Thu, 23 Mar 2023 19:13:13 -0700 (PDT) X-UUID: 6838d9b0c9e911edb6b9f13eb10bd0fe-20230324 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xcgV1aFJZyuT4duG4UGVRTSzUC7rIMfUP49ozcB4b38=; b=mTaDNjV7c3NTdok3f2G/Ma9hqRMUjDXu0d2Kce0GnNru3kqAFwxsqONdk4yklehMyPUqNN9Gv75hbZXVOGEAZFq3OMdJkxHCgM7hMiO819t+qTMO7h6tWMmUDxQ71uVc6vGQS2GF2dPSKXt1HV6TZrw2qYwzMoQ6ulOzwrMFyko=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.22,REQID:2484b0c1-81c4-4217-823f-cc9f7244f11d,IP:0,U RL:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-35 X-CID-META: VersionHash:120426c,CLOUDID:ca4f34b4-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 6838d9b0c9e911edb6b9f13eb10bd0fe-20230324 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 673169923; Fri, 24 Mar 2023 10:13:03 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 24 Mar 2023 10:13:01 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 24 Mar 2023 10:13:01 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v5 4/6] arm64: dts: mediatek: mt8186: Add ADSP node Date: Fri, 24 Mar 2023 10:12:56 +0800 Message-ID: <20230324021258.15863-5-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> References: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ADSP node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 0e42bdbd2cb6..337bcf3c1571 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -633,6 +633,22 @@ interrupts =3D ; }; =20 + adsp: adsp@10680000 { + compatible =3D "mediatek,mt8186-dsp"; + reg =3D <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, + <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; + reg-names =3D "cfg", "sram", "sec", "bus"; + clocks =3D <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; + clock-names =3D "audiodsp", "adsp_bus"; + assigned-clocks =3D <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + assigned-clock-parents =3D <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; + mbox-names =3D "rx", "tx"; + mboxes =3D <&adsp_mailbox0>, <&adsp_mailbox1>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; + status =3D "disabled"; + }; + adsp_mailbox0: mailbox@10686000 { compatible =3D "mediatek,mt8186-adsp-mbox"; #mbox-cells =3D <0>; --=20 2.18.0 From nobody Sat Sep 21 00:01:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87465C7619A for ; Fri, 24 Mar 2023 02:13:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229794AbjCXCNZ (ORCPT ); Thu, 23 Mar 2023 22:13:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231277AbjCXCNQ (ORCPT ); Thu, 23 Mar 2023 22:13:16 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C99A298CB; Thu, 23 Mar 2023 19:13:12 -0700 (PDT) X-UUID: 689815c4c9e911edb6b9f13eb10bd0fe-20230324 DKIM-Signature: v=1; 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charset="utf-8" Add the Global Command Engine (GCE) node for MT8186 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 337bcf3c1571..0d1ff5bb9526 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include +#include #include #include #include @@ -625,6 +626,15 @@ clocks =3D <&clk13m>; }; =20 + gce: mailbox@1022c000 { + compatible =3D "mediatek,mt8186-gce"; + reg =3D <0 0X1022c000 0 0x4000>; + clocks =3D <&infracfg_ao CLK_INFRA_AO_GCE>; + clock-names =3D "gce"; + interrupts =3D ; + #mbox-cells =3D <2>; + }; + scp: scp@10500000 { compatible =3D "mediatek,mt8186-scp"; reg =3D <0 0x10500000 0 0x40000>, --=20 2.18.0 From nobody Sat Sep 21 00:01:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00DE5C6FD1C for ; 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Fri, 24 Mar 2023 10:13:03 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 24 Mar 2023 10:13:03 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 24 Mar 2023 10:13:03 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v5 6/6] arm64: dts: mediatek: mt8186: Add display nodes Date: Fri, 24 Mar 2023 10:12:58 +0800 Message-ID: <20230324021258.15863-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> References: <20230324021258.15863-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add display nodes and the GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 116 +++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts= /mediatek/mt8186.dtsi index 0d1ff5bb9526..75667a26ec4e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -20,6 +20,13 @@ #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + ovl0 =3D &ovl0; + ovl_2l0 =3D &ovl_2l0; + rdma0 =3D &rdma0; + rdma1 =3D &rdma1; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -1189,6 +1196,20 @@ reg =3D <0 0x14000000 0 0x1000>; #clock-cells =3D <1>; #reset-cells =3D <1>; + mboxes =3D <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible =3D "mediatek,mt8186-disp-mutex"; + reg =3D <0 0x14001000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_MUTEX0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + mediatek,gce-events =3D , + ; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 smi_common: smi@14002000 { @@ -1222,6 +1243,45 @@ power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; }; =20 + ovl0: ovl@14005000 { + compatible =3D "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg =3D <0 0x14005000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + ovl_2l0: ovl@14006000 { + compatible =3D "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl= -2l"; + reg =3D <0 0x14006000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_OVL0_2L>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + rdma0: rdma@14007000 { + compatible =3D "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x14007000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA0>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + color: color@14009000 { + compatible =3D "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-colo= r"; + reg =3D <0 0x14009000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_COLOR0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dpi: dpi@1400a000 { compatible =3D "mediatek,mt8186-dpi"; reg =3D <0 0x1400a000 0 0x1000>; @@ -1239,6 +1299,52 @@ }; }; =20 + ccorr: ccorr@1400b000 { + compatible =3D "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccor= r"; + reg =3D <0 0x1400b000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_CCORR0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + aal: aal@1400c000 { + compatible =3D "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; + reg =3D <0 0x1400c000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_AAL0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + gamma: gamma@1400d000 { + compatible =3D "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamm= a"; + reg =3D <0 0x1400d000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_GAMMA0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + postmask: postmask@1400e000 { + compatible =3D "mediatek,mt8186-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg =3D <0 0x1400e000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_POSTMASK0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dither: dither@1400f000 { + compatible =3D "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dit= her"; + reg =3D <0 0x1400f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_DITHER0>; + interrupts =3D ; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dsi0: dsi@14013000 { compatible =3D "mediatek,mt8186-dsi"; reg =3D <0 0x14013000 0 0x1000>; @@ -1272,6 +1378,16 @@ #iommu-cells =3D <1>; }; =20 + rdma1: rdma@1401f000 { + compatible =3D "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg =3D <0 0x1401f000 0 0x1000>; + clocks =3D <&mmsys CLK_MM_DISP_RDMA1>; + interrupts =3D ; + iommus =3D <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0xf000 0x1000>; + power-domains =3D <&spm MT8186_POWER_DOMAIN_DIS>; + }; + wpesys: clock-controller@14020000 { compatible =3D "mediatek,mt8186-wpesys"; reg =3D <0 0x14020000 0 0x1000>; --=20 2.18.0