From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DA45C6FD1C for ; Thu, 23 Mar 2023 19:21:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231135AbjCWTVb (ORCPT ); Thu, 23 Mar 2023 15:21:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231245AbjCWTVW (ORCPT ); Thu, 23 Mar 2023 15:21:22 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57C161EBF6 for ; Thu, 23 Mar 2023 12:20:51 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 205-20020a2503d6000000b00b7411408308so4188253ybd.1 for ; Thu, 23 Mar 2023 12:20:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599248; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=nvDr5CEJpQ99Dan5HvL5Ea44JGN1C0/OsUkKnt1/keo=; b=jTbsgo4WPGZyi+bB/VZlE3DgqLdA83Oeu2ZjQ+xX867fB8LYjFadchlsy3a/X3LHvk 3+PFRq4eVZhg2HC0e0h2n3F/iXmF/oSxWd9F0M+VHgOZ3vSDlqnm3gjqcJfFHTSm5rfH 3+Oxusb6wpVe5CoPI4VWDl1Sq0NRoAB3GUXqdxpaE5OsyzHSWZke9kozGxX6AxvuB1tS NvfOKXAchtyVe64zeyrotajObP3jA9U9wzmb8NOiQmgY2gtnNJIok9UUzdtq/ffvfnpV CaJ/EL8mwxMLjkGZclRZ8+blfng7DMIeRLTB/jjrEJDEWNJcZyD3SAEUcLs9A2KNxQ4/ fBBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599248; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=nvDr5CEJpQ99Dan5HvL5Ea44JGN1C0/OsUkKnt1/keo=; b=xe6HrkwZB6Ij+EkYmE/+9LqB3MKznWDpYMG9mXryrF444VcM7tR+p6b9/J+y1JrjOx sxiGO+jhI4hGhWo5S4Eh7soZ9VbLC7HLoAjJaTC1oxyhoq1Bx7scKq16m5b2iZFS1AbP md8ftJPhYIAG3IIzIg1MrAhQ/zbqV0tvTUsY/qALKuOBeFNTPgmUpiVNIvIwdGzpSDM0 CZjm0wq3yd6HmXvudyPSsiNPZeNK+gAHlYCiyfH3EtAS++XCHE7L4CwEWAedaswUyF09 9drzbayQF2BaYyIqENy+VapCQIc8lqQK5TruXoRdkDFkiG/2qykxsWEo0BvkYv2J3Pm2 pcow== X-Gm-Message-State: AAQBX9eWGV0oMde87egoNskY3Mx5MWt02wkAFs3/haJxwmkFc1IS2wkp x451sT+zOuk40OW4tpuDgmyWSDunSwsu X-Google-Smtp-Source: AKy350bu5nOt+Qd0xzVVAKFvjOeUnVV87b6xCqXLTVk23tzBT89zBF+TD3yljYLmlarbvWI77A7a5BWxGusV X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a81:7647:0:b0:540:62be:42b with SMTP id j7-20020a817647000000b0054062be042bmr2198248ywk.6.1679599248271; Thu, 23 Mar 2023 12:20:48 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:20 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-2-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 1/9] perf vendor events: Broadwell v27 events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Description updates and formatting changes. Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/broadwell/cache.json | 296 +++++++++--------- .../arch/x86/broadwell/floating-point.json | 7 + .../arch/x86/broadwell/frontend.json | 18 +- .../pmu-events/arch/x86/broadwell/memory.json | 248 +++++++-------- .../arch/x86/broadwell/pipeline.json | 22 +- .../arch/x86/broadwell/uncore-other.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 7 files changed, 305 insertions(+), 290 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/pe= rf/pmu-events/arch/x86/broadwell/cache.json index 26199d3ebb25..f8ee5aefccea 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -16,7 +16,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", @@ -424,22 +424,22 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "This event counts load uops retired to the a= rchitected path with a filter on bits 0 and 1 applied.\nNote: This event co= unts AVX-256bit load/store double-pump memory uops as a single uop at retir= ement. This event also counts SW prefetches.", + "PublicDescription": "Counts all retired load uops. This event acc= ounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired store uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PublicDescription": "This event counts store uops retired to the = architected path with a filter on bits 0 and 1 applied.\nNote: This event c= ounts AVX-256bit load/store double-pump memory uops as a single uop at reti= rement.", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -511,10 +511,10 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests= ", + "BriefDescription": "Cacheable and non-cacheable code read request= s", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", + "PublicDescription": "This event counts both cacheable and non-cac= heable code read requests.", "SampleAfterValue": "100003", "UMask": "0x2" }, @@ -629,7 +629,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010091", + "MSRValue": "0x10091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -656,7 +656,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0091", + "MSRValue": "0x4003C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -665,7 +665,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0091", + "MSRValue": "0x2003C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -674,7 +674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0091", + "MSRValue": "0x803C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -683,7 +683,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0091", + "MSRValue": "0x1003C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -710,7 +710,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020091", + "MSRValue": "0x400020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -719,7 +719,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020091", + "MSRValue": "0x200020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020091", + "MSRValue": "0x80020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -737,7 +737,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT= _NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020091", + "MSRValue": "0x100020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -746,7 +746,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010240", + "MSRValue": "0x10240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -773,7 +773,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0240", + "MSRValue": "0x4003C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -782,7 +782,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0240", + "MSRValue": "0x2003C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -791,7 +791,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0240", + "MSRValue": "0x803C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -800,7 +800,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0240", + "MSRValue": "0x1003C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -827,7 +827,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020240", + "MSRValue": "0x400020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -836,7 +836,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020240", + "MSRValue": "0x200020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020240", + "MSRValue": "0x80020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -854,7 +854,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020240", + "MSRValue": "0x100020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -863,7 +863,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010090", + "MSRValue": "0x10090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -890,7 +890,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0090", + "MSRValue": "0x4003C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -899,7 +899,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0090", + "MSRValue": "0x2003C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -908,7 +908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0090", + "MSRValue": "0x803C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -917,7 +917,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0090", + "MSRValue": "0x1003C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -944,7 +944,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020090", + "MSRValue": "0x400020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -953,7 +953,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020090", + "MSRValue": "0x200020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020090", + "MSRValue": "0x80020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -971,7 +971,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020090", + "MSRValue": "0x100020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -980,7 +980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", + "MSRValue": "0x10120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1007,7 +1007,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", + "MSRValue": "0x4003C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1016,7 +1016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0120", + "MSRValue": "0x2003C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1025,7 +1025,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0120", + "MSRValue": "0x803C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1034,7 +1034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", + "MSRValue": "0x1003C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1061,7 +1061,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020120", + "MSRValue": "0x400020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1070,7 +1070,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020120", + "MSRValue": "0x200020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020120", + "MSRValue": "0x80020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1088,7 +1088,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020120", + "MSRValue": "0x100020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1097,7 +1097,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", + "MSRValue": "0x10122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1124,7 +1124,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1133,7 +1133,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0122", + "MSRValue": "0x2003C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1142,7 +1142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0122", + "MSRValue": "0x803C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1151,7 +1151,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", + "MSRValue": "0x1003C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1178,7 +1178,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020122", + "MSRValue": "0x400020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1187,7 +1187,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020122", + "MSRValue": "0x200020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020122", + "MSRValue": "0x80020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1205,7 +1205,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020122", + "MSRValue": "0x100020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1214,7 +1214,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010008", + "MSRValue": "0x10008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1241,7 +1241,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0008", + "MSRValue": "0x4003C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1250,7 +1250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0008", + "MSRValue": "0x2003C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1259,7 +1259,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0008", + "MSRValue": "0x803C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1268,7 +1268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0008", + "MSRValue": "0x1003C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1295,7 +1295,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020008", + "MSRValue": "0x400020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1304,7 +1304,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020008", + "MSRValue": "0x200020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1313,7 +1313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020008", + "MSRValue": "0x80020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1322,7 +1322,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020008", + "MSRValue": "0x100020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1331,7 +1331,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x10004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1358,7 +1358,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1367,7 +1367,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", + "MSRValue": "0x2003C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1376,7 +1376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0004", + "MSRValue": "0x803C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1385,7 +1385,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x1003C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1412,7 +1412,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", + "MSRValue": "0x400020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1421,7 +1421,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", + "MSRValue": "0x200020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1430,7 +1430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", + "MSRValue": "0x80020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1439,7 +1439,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", + "MSRValue": "0x100020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1448,7 +1448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x10001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1475,7 +1475,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1484,7 +1484,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", + "MSRValue": "0x2003C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1493,7 +1493,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0001", + "MSRValue": "0x803C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1502,7 +1502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x1003C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1529,7 +1529,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", + "MSRValue": "0x400020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1538,7 +1538,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", + "MSRValue": "0x200020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1547,7 +1547,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", + "MSRValue": "0x80020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1556,7 +1556,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", + "MSRValue": "0x100020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1565,7 +1565,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1592,7 +1592,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1601,7 +1601,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", + "MSRValue": "0x2003C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1610,7 +1610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0002", + "MSRValue": "0x803C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1619,7 +1619,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x1003C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1628,7 +1628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x18000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1655,7 +1655,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", + "MSRValue": "0x4003C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1664,7 +1664,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", + "MSRValue": "0x2003C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1673,7 +1673,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C8000", + "MSRValue": "0x803C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1682,7 +1682,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", + "MSRValue": "0x1003C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1709,7 +1709,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", + "MSRValue": "0x400028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1718,7 +1718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", + "MSRValue": "0x200028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1727,7 +1727,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", + "MSRValue": "0x80028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1736,7 +1736,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", + "MSRValue": "0x100028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1745,7 +1745,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010040", + "MSRValue": "0x10040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1772,7 +1772,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0040", + "MSRValue": "0x4003C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1781,7 +1781,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0040", + "MSRValue": "0x2003C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1790,7 +1790,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0040", + "MSRValue": "0x803C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1799,7 +1799,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0040", + "MSRValue": "0x1003C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1826,7 +1826,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020040", + "MSRValue": "0x400020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1835,7 +1835,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020040", + "MSRValue": "0x200020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1844,7 +1844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020040", + "MSRValue": "0x80020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1853,7 +1853,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020040", + "MSRValue": "0x100020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1862,7 +1862,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x10010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1889,7 +1889,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x4003C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1898,7 +1898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", + "MSRValue": "0x2003C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1907,7 +1907,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0010", + "MSRValue": "0x803C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1916,7 +1916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x1003C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1943,7 +1943,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020010", + "MSRValue": "0x400020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1952,7 +1952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020010", + "MSRValue": "0x200020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1961,7 +1961,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020010", + "MSRValue": "0x80020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1970,7 +1970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020010", + "MSRValue": "0x100020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1979,7 +1979,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x10020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2006,7 +2006,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x4003C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2015,7 +2015,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", + "MSRValue": "0x2003C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2024,7 +2024,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0020", + "MSRValue": "0x803C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2033,7 +2033,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1003C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2060,7 +2060,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020020", + "MSRValue": "0x400020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2069,7 +2069,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020020", + "MSRValue": "0x200020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2078,7 +2078,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020020", + "MSRValue": "0x80020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2087,7 +2087,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020020", + "MSRValue": "0x100020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2096,7 +2096,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010200", + "MSRValue": "0x10200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2123,7 +2123,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0200", + "MSRValue": "0x4003C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2132,7 +2132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0200", + "MSRValue": "0x2003C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2141,7 +2141,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0200", + "MSRValue": "0x803C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2150,7 +2150,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0200", + "MSRValue": "0x1003C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2177,7 +2177,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020200", + "MSRValue": "0x400020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2186,7 +2186,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020200", + "MSRValue": "0x200020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2195,7 +2195,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020200", + "MSRValue": "0x80020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2204,7 +2204,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020200", + "MSRValue": "0x100020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2213,7 +2213,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", + "MSRValue": "0x10080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2240,7 +2240,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", + "MSRValue": "0x4003C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2249,7 +2249,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0080", + "MSRValue": "0x2003C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2258,7 +2258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0080", + "MSRValue": "0x803C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2267,7 +2267,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", + "MSRValue": "0x1003C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2294,7 +2294,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020080", + "MSRValue": "0x400020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2303,7 +2303,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020080", + "MSRValue": "0x200020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2312,7 +2312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020080", + "MSRValue": "0x80020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2321,7 +2321,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020080", + "MSRValue": "0x100020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2330,7 +2330,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", + "MSRValue": "0x10100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2357,7 +2357,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", + "MSRValue": "0x4003C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2366,7 +2366,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0100", + "MSRValue": "0x2003C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2375,7 +2375,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0100", + "MSRValue": "0x803C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2384,7 +2384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", + "MSRValue": "0x1003C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2411,7 +2411,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020100", + "MSRValue": "0x400020100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2420,7 +2420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020100", + "MSRValue": "0x200020100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2429,7 +2429,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020100", + "MSRValue": "0x80020100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2438,7 +2438,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020100", + "MSRValue": "0x100020100", "SampleAfterValue": "100003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b= /tools/perf/pmu-events/arch/x86/broadwell/floating-point.json index 0de16d9a80da..e4826dc7f797 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json @@ -3,6 +3,7 @@ "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, @@ -10,6 +11,7 @@ "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 4 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, @@ -17,6 +19,7 @@ "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 c= alculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, @@ -24,6 +27,7 @@ "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 8 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -45,6 +49,7 @@ "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Each count represents 1 computation operation. Applies to SSE* and= AVX* scalar double and single precision floating-point instructions: ADD S= UB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions c= ount twice as they perform multiple calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", "SampleAfterValue": "2000003", "UMask": "0x3" }, @@ -52,6 +57,7 @@ "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform multiple calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -59,6 +65,7 @@ "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform multiple calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools= /perf/pmu-events/arch/x86/broadwell/frontend.json index d0f6678609ae..bd5da39564e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json @@ -125,16 +125,16 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -153,7 +153,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", @@ -161,10 +161,10 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", + "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.= ", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -178,10 +178,10 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/p= erf/pmu-events/arch/x86/broadwell/memory.json index 394ed602fcb1..ac7cdb831960 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -206,7 +206,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000091", + "MSRValue": "0x43C000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -215,7 +215,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000091", + "MSRValue": "0x23C000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -224,7 +224,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000091", + "MSRValue": "0xBC000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -233,7 +233,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000091", + "MSRValue": "0x13C000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -260,7 +260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000091", + "MSRValue": "0x404000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -269,7 +269,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000091", + "MSRValue": "0x204000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -278,7 +278,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000091", + "MSRValue": "0x84000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -296,7 +296,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000091", + "MSRValue": "0x104000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -323,7 +323,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000240", + "MSRValue": "0x43C000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -332,7 +332,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000240", + "MSRValue": "0x23C000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -341,7 +341,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000240", + "MSRValue": "0xBC000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -350,7 +350,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000240", + "MSRValue": "0x13C000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -377,7 +377,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000240", + "MSRValue": "0x404000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -386,7 +386,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000240", + "MSRValue": "0x204000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -395,7 +395,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000240", + "MSRValue": "0x84000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -413,7 +413,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000240", + "MSRValue": "0x104000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -440,7 +440,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000090", + "MSRValue": "0x43C000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -449,7 +449,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000090", + "MSRValue": "0x23C000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -458,7 +458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000090", + "MSRValue": "0xBC000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -467,7 +467,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000090", + "MSRValue": "0x13C000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -494,7 +494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000090", + "MSRValue": "0x404000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -503,7 +503,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000090", + "MSRValue": "0x204000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -512,7 +512,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000090", + "MSRValue": "0x84000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -530,7 +530,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000090", + "MSRValue": "0x104000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -557,7 +557,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000120", + "MSRValue": "0x43C000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -566,7 +566,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000120", + "MSRValue": "0x23C000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -575,7 +575,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000120", + "MSRValue": "0xBC000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -584,7 +584,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000120", + "MSRValue": "0x13C000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -611,7 +611,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000120", + "MSRValue": "0x404000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -620,7 +620,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000120", + "MSRValue": "0x204000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -629,7 +629,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000120", + "MSRValue": "0x84000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -647,7 +647,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000120", + "MSRValue": "0x104000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -674,7 +674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000122", + "MSRValue": "0x43C000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -683,7 +683,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000122", + "MSRValue": "0x23C000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -692,7 +692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000122", + "MSRValue": "0xBC000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -701,7 +701,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000122", + "MSRValue": "0x13C000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HI= T_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000122", + "MSRValue": "0x404000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -737,7 +737,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000122", + "MSRValue": "0x204000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -746,7 +746,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000122", + "MSRValue": "0x84000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -764,7 +764,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= T_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000122", + "MSRValue": "0x104000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -791,7 +791,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000008", + "MSRValue": "0x43C000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -800,7 +800,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000008", + "MSRValue": "0x23C000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -809,7 +809,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000008", + "MSRValue": "0xBC000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -818,7 +818,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000008", + "MSRValue": "0x13C000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000008", + "MSRValue": "0x404000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -854,7 +854,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000008", + "MSRValue": "0x204000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -863,7 +863,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000008", + "MSRValue": "0x84000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -881,7 +881,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT= _NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000008", + "MSRValue": "0x104000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -908,7 +908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000004", + "MSRValue": "0x43C000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -917,7 +917,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000004", + "MSRValue": "0x23C000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -926,7 +926,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000004", + "MSRValue": "0xBC000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -935,7 +935,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000004", + "MSRValue": "0x13C000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", + "MSRValue": "0x404000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -971,7 +971,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", + "MSRValue": "0x204000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -980,7 +980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", + "MSRValue": "0x84000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -998,7 +998,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", + "MSRValue": "0x104000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1025,7 +1025,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000001", + "MSRValue": "0x43C000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1034,7 +1034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000001", + "MSRValue": "0x23C000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1043,7 +1043,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000001", + "MSRValue": "0xBC000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1052,7 +1052,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000001", + "MSRValue": "0x13C000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", + "MSRValue": "0x404000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1088,7 +1088,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", + "MSRValue": "0x204000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1097,7 +1097,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", + "MSRValue": "0x84000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1115,7 +1115,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", + "MSRValue": "0x104000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1142,7 +1142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000002", + "MSRValue": "0x43C000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1151,7 +1151,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000002", + "MSRValue": "0x23C000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1160,7 +1160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000002", + "MSRValue": "0xBC000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1169,7 +1169,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000002", + "MSRValue": "0x13C000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C008000", + "MSRValue": "0x43C008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1205,7 +1205,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C008000", + "MSRValue": "0x23C008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1214,7 +1214,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC008000", + "MSRValue": "0xBC008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1223,7 +1223,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C008000", + "MSRValue": "0x13C008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1250,7 +1250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", + "MSRValue": "0x404008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1259,7 +1259,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", + "MSRValue": "0x204008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1268,7 +1268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", + "MSRValue": "0x84008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1286,7 +1286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", + "MSRValue": "0x104008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1313,7 +1313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000040", + "MSRValue": "0x43C000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1322,7 +1322,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000040", + "MSRValue": "0x23C000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1331,7 +1331,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000040", + "MSRValue": "0xBC000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1340,7 +1340,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000040", + "MSRValue": "0x13C000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1367,7 +1367,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000040", + "MSRValue": "0x404000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1376,7 +1376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000040", + "MSRValue": "0x204000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1385,7 +1385,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000040", + "MSRValue": "0x84000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1403,7 +1403,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000040", + "MSRValue": "0x104000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1430,7 +1430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000010", + "MSRValue": "0x43C000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1439,7 +1439,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000010", + "MSRValue": "0x23C000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1448,7 +1448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000010", + "MSRValue": "0xBC000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1457,7 +1457,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000010", + "MSRValue": "0x13C000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1484,7 +1484,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000010", + "MSRValue": "0x404000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1493,7 +1493,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000010", + "MSRValue": "0x204000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1502,7 +1502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000010", + "MSRValue": "0x84000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1520,7 +1520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000010", + "MSRValue": "0x104000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1547,7 +1547,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000020", + "MSRValue": "0x43C000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1556,7 +1556,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000020", + "MSRValue": "0x23C000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1565,7 +1565,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000020", + "MSRValue": "0xBC000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1574,7 +1574,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000020", + "MSRValue": "0x13C000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1601,7 +1601,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000020", + "MSRValue": "0x404000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1610,7 +1610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000020", + "MSRValue": "0x204000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1619,7 +1619,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000020", + "MSRValue": "0x84000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1637,7 +1637,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000020", + "MSRValue": "0x104000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1664,7 +1664,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000200", + "MSRValue": "0x43C000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1673,7 +1673,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000200", + "MSRValue": "0x23C000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1682,7 +1682,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000200", + "MSRValue": "0xBC000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1691,7 +1691,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000200", + "MSRValue": "0x13C000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1718,7 +1718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000200", + "MSRValue": "0x404000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1727,7 +1727,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000200", + "MSRValue": "0x204000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1736,7 +1736,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000200", + "MSRValue": "0x84000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1754,7 +1754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000200", + "MSRValue": "0x104000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1781,7 +1781,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000080", + "MSRValue": "0x43C000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1790,7 +1790,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000080", + "MSRValue": "0x23C000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1799,7 +1799,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000080", + "MSRValue": "0xBC000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1808,7 +1808,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000080", + "MSRValue": "0x13C000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1835,7 +1835,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000080", + "MSRValue": "0x404000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1844,7 +1844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000080", + "MSRValue": "0x204000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1853,7 +1853,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000080", + "MSRValue": "0x84000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1871,7 +1871,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000080", + "MSRValue": "0x104000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1898,7 +1898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000100", + "MSRValue": "0x43C000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1907,7 +1907,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000100", + "MSRValue": "0x23C000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1916,7 +1916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000100", + "MSRValue": "0xBC000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1925,7 +1925,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000100", + "MSRValue": "0x13C000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1952,7 +1952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000100", + "MSRValue": "0x404000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1961,7 +1961,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000100", + "MSRValue": "0x204000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1970,7 +1970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000100", + "MSRValue": "0x84000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1988,7 +1988,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000100", + "MSRValue": "0x104000100", "SampleAfterValue": "100003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools= /perf/pmu-events/arch/x86/broadwell/pipeline.json index 2f0fe6b35334..9a902d2160e6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json @@ -214,6 +214,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "EventCode": "0x89", @@ -500,7 +508,7 @@ "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to cha= nging prefix length (66, 67 or REX.W when they change the length of the dec= oded instruction). Occurrences counting is proportional to the number of pr= efixes in a 16B-line. This may result in the following penalties: three-cyc= le penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -909,7 +917,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", + "BriefDescription": "Cycles per core when uops are executed in por= t 0.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,7 +933,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", + "BriefDescription": "Cycles per core when uops are executed in por= t 1.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -973,7 +981,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", + "BriefDescription": "Cycles per core when uops are executed in por= t 4.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,7 +997,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", + "BriefDescription": "Cycles per core when uops are executed in por= t 5.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,7 +1013,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", + "BriefDescription": "Cycles per core when uops are executed in por= t 6.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -1097,7 +1105,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "CounterMask": "10", + "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", "Invert": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/broadwell/uncore-other.json index ddcf7faa9d10..368a958a18a0 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json @@ -8,7 +8,7 @@ "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of all Core outgoing = valid entries. Such entry is defined as valid from it's allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", + "BriefDescription": "Each cycle counts number of all Core outgoing= valid entries. Such entry is defined as valid from its allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 9abebe50ae0d..70be860bcb53 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -2,7 +2,7 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core -GenuineIntel-6-(3D|47),v26,broadwell,core +GenuineIntel-6-(3D|47),v27,broadwell,core GenuineIntel-6-56,v7,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4A8EC74A5B for ; Thu, 23 Mar 2023 19:21:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231461AbjCWTVe (ORCPT ); Thu, 23 Mar 2023 15:21:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230517AbjCWTVY (ORCPT ); Thu, 23 Mar 2023 15:21:24 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A0F3D515 for ; Thu, 23 Mar 2023 12:20:56 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-54196bfcd5fso225695447b3.4 for ; Thu, 23 Mar 2023 12:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599255; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=dpUbyagLHfyugt4xjgObF98IlMw5uCwm74nv9CwNkFI=; b=FJ6bwSpjlzvZD/StU/PddRnv/l2k/hnYLRQ6iItzf76rmzgIjohfVdObyOh1IXhp60 CuNIaphOhIyrLx6Nnsel8e5/RMRX6u0lCsqGxJDAqNfv1Y3kLu0dLQnCppcugL9fz9sm E6qwkcHJpcUHzcQijbslo+ejRrpcgUoU61oTo/fjV6CLA7anAF72Sb/k0vO3Pj/NICOx 8GrzJ0aK42GOVw+neIggAFCMRupdJ2s6625QwMHHirN8f8HyD2P318JkAWYcx5iksXde nim2WBAWHRQmzBtDLmmBH7BcgLX1SNImUsFNemM0qfK+BXgP2bAfZyEGRCtjsQ35P2f2 LlOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599255; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dpUbyagLHfyugt4xjgObF98IlMw5uCwm74nv9CwNkFI=; b=fhWIkOOsEEulFVkmJhfUNPeFhfOiH2AIDKZM0osi1+1wIZr6utkj66rBX2msPEApb1 RJbZQHZZDT257uLXnSrSgi9ivd395nT8Ch6lXtVyIivf4Lm9kP7AAp6XN1jvyeHSzEd4 gP5ZlF5WjTb1mghhc0jCqB3UI/IkGmvNuIZaCdiuwdXBhYjED5oFhlXozvjZI6TNsoTH vuKCmI4nafrQ205e2OSQMoO+B2eV7jnvDDJIsss8wkGa3/iezXv5WyTmIWfZvI7j+7RH I/h5ftM+HGKjSl7Pt0IwiDY1gj5vGxwSD+I9PV6jSZAPOi4sUHdamssIesjqpFXry9HI F/zA== X-Gm-Message-State: AAQBX9cOWeHVik72gNhflMwGzwlMdVAcw8GYMD1aooe1PxMRa7kbGiHe bdMTUq4/qjdzHYopcBtyNsEuPc7y5zPX X-Google-Smtp-Source: AKy350YBa8i/qR353DEb2eaMBwrV08XKVFCrwWg4R4Q0l2jXLRjJsUxHlw469MF+P8JG1CpGZn5q22bsfyeD X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a05:6902:1244:b0:b73:caa7:f05e with SMTP id t4-20020a056902124400b00b73caa7f05emr3090843ybu.2.1679599255478; Thu, 23 Mar 2023 12:20:55 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:21 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-3-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 2/9] perf vendor events: Broadwellde v9 events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Signed-off-by: Ian Rogers --- .../arch/x86/broadwellde/cache.json | 105 +++---- .../arch/x86/broadwellde/floating-point.json | 45 +-- .../arch/x86/broadwellde/frontend.json | 18 +- .../arch/x86/broadwellde/memory.json | 64 +++-- .../arch/x86/broadwellde/pipeline.json | 79 +++--- .../arch/x86/broadwellde/uncore-cache.json | 72 ++--- .../arch/x86/broadwellde/uncore-memory.json | 256 +++++++++++++++++- .../arch/x86/broadwellde/uncore-other.json | 27 +- .../arch/x86/broadwellde/uncore-power.json | 10 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 10 files changed, 495 insertions(+), 183 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/= perf/pmu-events/arch/x86/broadwellde/cache.json index fcc99fd22b0a..6784331ac1cb 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -16,7 +16,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", @@ -139,7 +139,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", - "UMask": "0x44" + "UMask": "0xc4" }, { "BriefDescription": "L2 cache misses when fetching instructions.", @@ -152,9 +152,9 @@ "BriefDescription": "Demand Data Read requests that hit L2 cache", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "This event counts the number of demand Data = Read requests that hit L2 cache. Only not rejected loads are counted.", + "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", "SampleAfterValue": "200003", - "UMask": "0x41" + "UMask": "0xc1" }, { "BriefDescription": "Demand Data Read miss L2, no rejects", @@ -170,7 +170,7 @@ "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", "SampleAfterValue": "200003", - "UMask": "0x50" + "UMask": "0xd0" }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", @@ -199,7 +199,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", - "UMask": "0x42" + "UMask": "0xc2" }, { "BriefDescription": "RFO requests that miss L2 cache.", @@ -297,61 +297,62 @@ "UMask": "0x4f" }, { - "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 hi= t and a cross-core snoop hit in the on-pkg core cache.", + "PublicDescription": "This event counts retired load uops which da= ta sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.= ", "SampleAfterValue": "20011", "UMask": "0x2" }, { - "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were HitM = responses from a core on same socket (shared L3).", + "PublicDescription": "This event counts retired load uops which da= ta sources were HitM responses from a core on same socket (shared L3).", "SampleAfterValue": "20011", "UMask": "0x4" }, { - "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS= )", + "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were L3 Hi= t and a cross-core snoop missed in the on-pkg core cache.", + "PublicDescription": "This event counts retired load uops which da= ta sources were L3 Hit and a cross-core snoop missed in the on-pkg core cac= he.", "SampleAfterValue": "20011", "UMask": "0x1" }, { - "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were hits = in the last-level (L3) cache without snoops required.", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the last-level (L3) cache without snoops required.", "SampleAfterValue": "100003", "UMask": "0x8" }, { + "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", "Data_LA": "1", "Errata": "BDE70, BDM100", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", - "PublicDescription": "This event counts retired load uops where th= e data came from local DRAM. This does not include hardware prefetches. Thi= s is a precise event.", + "PublicDescription": "Retired load uop whose Data Source was: loca= l DRAM either Snoop not needed or Snoop Miss (RspI).", "SampleAfterValue": "100007", "UMask": "0x1" }, { - "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", + "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -361,7 +362,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache (Precise Event)", + "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -371,7 +372,7 @@ "UMask": "0x20" }, { - "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM (Precise Event)", + "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -381,69 +382,69 @@ "UMask": "0x10" }, { - "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were load = uops missed L1 but hit a fill buffer due to a preceding miss to the same ca= che line with the data not ready.\nNote: Only two data-sources of L1/FB are= applicable for AVX-256bit even though the corresponding AVX load could be= serviced by a deeper level in the memory hierarchy. Data source is reporte= d for the Low-half load.", + "PublicDescription": "This event counts retired load uops which da= ta sources were load uops missed L1 but hit a fill buffer due to a precedin= g miss to the same cache line with the data not ready.\nNote: Only two data= -sources of L1/FB are applicable for AVX-256bit even though the correspond= ing AVX load could be serviced by a deeper level in the memory hierarchy. D= ata source is reported for the Low-half load.", "SampleAfterValue": "100003", "UMask": "0x40" }, { - "BriefDescription": "Retired load uops with L1 cache hits as data = sources. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data source were hits i= n the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are a= pplicable for AVX-256bit even though the corresponding AVX load could be s= erviced by a deeper level in the memory hierarchy. Data source is reported = for the Low-half load. This event also counts SW prefetches independent of = the actual data source.", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the nearest-level (L1) cache.\nNote: Only two data-= sources of L1/FB are applicable for AVX-256bit even though the correspondi= ng AVX load could be serviced by a deeper level in the memory hierarchy. Da= ta source is reported for the Low-half load. This event also counts SW pref= etches independent of the actual data source.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Retired load uops misses in L1 cache as data = sources. Uses PEBS.", + "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the nearest-level (L1) cache. Counting excludes unknown and UC data so= urce.", + "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the nearest-level (L1) cache. Counting excludes u= nknown and UC data source.", "SampleAfterValue": "100003", "UMask": "0x8" }, { - "BriefDescription": "Retired load uops with L2 cache hits as data = sources. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were hits = in the mid-level (L2) cache.", + "PublicDescription": "This event counts retired load uops which da= ta sources were hits in the mid-level (L2) cache.", "SampleAfterValue": "100003", "UMask": "0x2" }, { - "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources. Uses PEBS.", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were misse= s in the mid-level (L2) cache. Counting excludes unknown and UC data source= .", + "PublicDescription": "This event counts retired load uops which da= ta sources were misses in the mid-level (L2) cache. Counting excludes unkno= wn and UC data source.", "SampleAfterValue": "50021", "UMask": "0x10" }, { - "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknow= n data-source. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts retired load uops which data sources were data = hits in the last-level (L3) cache without snoops required.", + "PublicDescription": "This event counts retired load uops which da= ta sources were data hits in the last-level (L3) cache without snoops requi= red.", "SampleAfterValue": "50021", "UMask": "0x4" }, { - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source. (Precise Event - PEBS).", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", "Data_LA": "1", "Errata": "BDM100, BDE70", "EventCode": "0xD1", @@ -453,73 +454,73 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops. (Precise Event - PEBS)= ", + "BriefDescription": "Retired load uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops retired to the architected path with = a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/= store double-pump memory uops as a single uop at retirement. This event als= o counts SW prefetches.", + "PublicDescription": "Counts all retired load uops. This event acc= ounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", + "BriefDescription": "Retired store uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops retired to the architected path with= a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load= /store double-pump memory uops as a single uop at retirement.", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, { - "BriefDescription": "Retired load uops with locked access. (Precis= e Event - PEBS)", + "BriefDescription": "Retired load uops with locked access.", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with locked access retired to the arc= hitected path.", + "PublicDescription": "This event counts load uops with locked acce= ss retired to the architected path.", "SampleAfterValue": "100007", "UMask": "0x21" }, { - "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.(Precise Event - PEBS)", + "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted load uops retired to the architec= ted path. A line split is across 64B cache-line which includes a page split= (4K).", + "PublicDescription": "This event counts line-splitted load uops re= tired to the architected path. A line split is across 64B cache-line which = includes a page split (4K).", "SampleAfterValue": "100003", "UMask": "0x41" }, { - "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS)", + "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts line-splitted store uops retired to the archite= cted path. A line split is across 64B cache-line which includes a page spli= t (4K).", + "PublicDescription": "This event counts line-splitted store uops r= etired to the architected path. A line split is across 64B cache-line which= includes a page split (4K).", "SampleAfterValue": "100003", "UMask": "0x42" }, { - "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event - PEBS)", + "BriefDescription": "Retired load uops that miss the STLB.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts load uops with true STLB miss retired to the ar= chitected path. True STLB miss is an uop triggering page walk that gets com= pleted without blocks, and later gets retired. This page walk can end up wi= th or without a fault.", + "PublicDescription": "This event counts load uops with true STLB m= iss retired to the architected path. True STLB miss is an uop triggering pa= ge walk that gets completed without blocks, and later gets retired. This pa= ge walk can end up with or without a fault.", "SampleAfterValue": "100003", "UMask": "0x11" }, { - "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event - PEBS)", + "BriefDescription": "Retired store uops that miss the STLB.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts store uops true STLB miss retired to the archit= ected path. True STLB miss is an uop triggering page walk that gets complet= ed without blocks, and later gets retired. This page walk can end up with o= r without a fault.", + "PublicDescription": "This event counts store uops with true STLB = miss retired to the architected path. True STLB miss is an uop triggering p= age walk that gets completed without blocks, and later gets retired. This p= age walk can end up with or without a fault.", "SampleAfterValue": "100003", "UMask": "0x12" }, @@ -532,10 +533,18 @@ "UMask": "0x8" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests= ", + "BriefDescription": "Any memory transaction that reached the SQ.", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "This event counts memory transactions reache= d the super queue including requests initiated by the core, all L3 prefetch= es, page walks, and so on.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cacheable and non-cacheable code read request= s", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", + "PublicDescription": "This event counts both cacheable and non-cac= heable code read requests.", "SampleAfterValue": "100003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json= b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json index 0b3f026158e2..e4826dc7f797 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json @@ -1,70 +1,77 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired. Each count represe= nts 2 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP = and FM(N)ADD/SUB instructions count twice as they perform multiple calculat= ions per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/= SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multipl= e calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 4 calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired. Each count represe= nts 4 computations. Applies to SSE* and AVX* packed double precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP = and FM(N)ADD/SUB instructions count twice as they perform multiple calculat= ions per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 c= alculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired. Each count represe= nts 8 computations. Applies to SSE* and AVX* packed single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/= SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multipl= e calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 8 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, { - "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP = FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perfor= m multiple calculations per element. ?.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed double precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", "SampleAfterValue": "2000006", "UMask": "0x15" }, { - "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired. Applies to SSE* and AVX*, packed, double and= single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* packed double and single precision floating= -point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RC= P DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", "UMask": "0x3c" }, { - "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired. Applies to SSE* and AVX* scalar, double and = single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(= N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Each count represents 1 computation operation. Applies to SSE* and= AVX* scalar double and single precision floating-point instructions: ADD S= UB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions c= ount twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", "SampleAfterValue": "2000003", "UMask": "0x3" }, { - "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar double precision floating-point = instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB inst= ructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired. Each count represents 1 co= mputation. Applies to SSE* and AVX* scalar single precision floating-point = instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)AD= D/SUB instructions count twice as they perform multiple calculations per el= ement.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired. Applies to SSE* and AVX*scalar, do= uble and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT= SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as t= hey perform multiple calculations per element. ?.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed single precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", "UMask": "0x2a" diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/frontend.json index d0f6678609ae..bd5da39564e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json @@ -125,16 +125,16 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -153,7 +153,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", @@ -161,10 +161,10 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", + "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.= ", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -178,10 +178,10 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools= /perf/pmu-events/arch/x86/broadwellde/memory.json index 12cc384d7f18..041b6ff4062e 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -1,10 +1,10 @@ [ { - "BriefDescription": "Number of times HLE abort was triggered (PEBS= )", + "BriefDescription": "Number of times HLE abort was triggered", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", - "PublicDescription": "Number of times HLE abort was triggered (PEB= S).", + "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", "UMask": "0x4" }, @@ -73,98 +73,106 @@ "UMask": "0x2" }, { - "BriefDescription": "Loads with latency value being above 128", + "BriefDescription": "Randomly selected loads with latency value be= ing above 128", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", "MSRValue": "0x80", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above 128.", + "PublicDescription": "Counts randomly selected loads with latency = value being above 128.", "SampleAfterValue": "1009", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 16", + "BriefDescription": "Randomly selected loads with latency value be= ing above 16", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", "MSRValue": "0x10", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above 16.", + "PublicDescription": "Counts randomly selected loads with latency = value being above 16.", "SampleAfterValue": "20011", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 256", + "BriefDescription": "Randomly selected loads with latency value be= ing above 256", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", "MSRValue": "0x100", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above 256.", + "PublicDescription": "Counts randomly selected loads with latency = value being above 256.", "SampleAfterValue": "503", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 32", + "BriefDescription": "Randomly selected loads with latency value be= ing above 32", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", "MSRValue": "0x20", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above 32.", + "PublicDescription": "Counts randomly selected loads with latency = value being above 32.", "SampleAfterValue": "100007", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 4", + "BriefDescription": "Randomly selected loads with latency value be= ing above 4", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", "MSRValue": "0x4", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above four.", + "PublicDescription": "Counts randomly selected loads with latency = value being above four.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 512", + "BriefDescription": "Randomly selected loads with latency value be= ing above 512", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", "MSRValue": "0x200", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above 512.", + "PublicDescription": "Counts randomly selected loads with latency = value being above 512.", "SampleAfterValue": "101", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 64", + "BriefDescription": "Randomly selected loads with latency value be= ing above 64", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", "MSRValue": "0x40", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above 64.", + "PublicDescription": "Counts randomly selected loads with latency = value being above 64.", "SampleAfterValue": "2003", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 8", + "BriefDescription": "Randomly selected loads with latency value be= ing above 8", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", "MSRValue": "0x8", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value b= eing above eight.", + "PublicDescription": "Counts randomly selected loads with latency = value being above eight.", "SampleAfterValue": "50021", "UMask": "0x1" }, @@ -185,11 +193,11 @@ "UMask": "0x2" }, { - "BriefDescription": "Number of times RTM abort was triggered (PEBS= )", + "BriefDescription": "Number of times RTM abort was triggered", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", - "PublicDescription": "Number of times RTM abort was triggered (PEB= S).", + "PublicDescription": "Number of times RTM abort was triggered .", "SampleAfterValue": "2000003", "UMask": "0x4" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/pipeline.json index 9e7d66b07f01..9a902d2160e6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json @@ -129,11 +129,11 @@ "UMask": "0x4" }, { - "BriefDescription": "Conditional branch instructions retired. (Pre= cise Event - PEBS)", + "BriefDescription": "Conditional branch instructions retired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts conditional branch instructions retired.", + "PublicDescription": "This event counts conditional branch instruc= tions retired.", "SampleAfterValue": "400009", "UMask": "0x1" }, @@ -147,38 +147,38 @@ "UMask": "0x40" }, { - "BriefDescription": "Direct and indirect near call instructions re= tired. (Precise Event - PEBS)", + "BriefDescription": "Direct and indirect near call instructions re= tired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect near call instructions= retired.", + "PublicDescription": "This event counts both direct and indirect n= ear call instructions retired.", "SampleAfterValue": "100007", "UMask": "0x2" }, { - "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3). (Precise Event - PEBS)", + "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts both direct and indirect macro near call instru= ctions retired (captured in ring 3).", + "PublicDescription": "This event counts both direct and indirect m= acro near call instructions retired (captured in ring 3).", "SampleAfterValue": "100007", "UMask": "0x2" }, { - "BriefDescription": "Return instructions retired. (Precise Event -= PEBS)", + "BriefDescription": "Return instructions retired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts return instructions retired.", + "PublicDescription": "This event counts return instructions retire= d.", "SampleAfterValue": "100007", "UMask": "0x8" }, { - "BriefDescription": "Taken branch instructions retired. (Precise E= vent - PEBS)", + "BriefDescription": "Taken branch instructions retired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts taken branch instructions retired.", + "PublicDescription": "This event counts taken branch instructions = retired.", "SampleAfterValue": "400009", "UMask": "0x20" }, @@ -214,6 +214,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "EventCode": "0x89", @@ -270,29 +278,29 @@ "UMask": "0x4" }, { - "BriefDescription": "Mispredicted conditional branch instructions = retired. (Precise Event - PEBS)", + "BriefDescription": "Mispredicted conditional branch instructions = retired.", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted conditional branch instructions re= tired.", + "PublicDescription": "This event counts mispredicted conditional b= ranch instructions retired.", "SampleAfterValue": "400009", "UMask": "0x1" }, { - "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken. (Precise Event - PEBS).", + "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", - "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken. (Precise Event - PEBS).", + "PublicDescription": "Number of near branch instructions retired t= hat were mispredicted and taken.", "SampleAfterValue": "400009", "UMask": "0x20" }, { - "BriefDescription": "This event counts the number of mispredicted = ret instructions retired.(Precise Event)", + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts mispredicted return instructions retired.", + "PublicDescription": "This event counts mispredicted return instru= ctions retired.", "SampleAfterValue": "100007", "UMask": "0x8" }, @@ -300,7 +308,7 @@ "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "EventCode": "0x3c", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x2" }, { @@ -308,7 +316,7 @@ "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -316,14 +324,14 @@ "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x2" }, { @@ -338,7 +346,7 @@ "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -346,7 +354,7 @@ "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -500,7 +508,7 @@ "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to cha= nging prefix length (66, 67 or REX.W when they change the length of the dec= oded instruction). Occurrences counting is proportional to the number of pr= efixes in a 16B-line. This may result in the following penalties: three-cyc= le penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -681,9 +689,9 @@ }, { "BriefDescription": "Resource-related stall cycles", - "EventCode": "0xA2", + "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "This event counts resource-related stall cyc= les. Reasons for stalls can be as follows:\n - *any* u-arch structure got f= ull (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or P= hysical History Table (PHT) slots)\n - *any* u-arch structure got empty (li= ke INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This= counts cycles that the pipeline backend blocked uop delivery from the fron= t end.", + "PublicDescription": "This event counts resource-related stall cyc= les.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -909,7 +917,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", + "BriefDescription": "Cycles per core when uops are executed in por= t 0.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,7 +933,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", + "BriefDescription": "Cycles per core when uops are executed in por= t 1.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -973,7 +981,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", + "BriefDescription": "Cycles per core when uops are executed in por= t 4.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,7 +997,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", + "BriefDescription": "Cycles per core when uops are executed in por= t 5.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,7 +1013,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", + "BriefDescription": "Cycles per core when uops are executed in por= t 6.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -1068,21 +1076,20 @@ "UMask": "0x1" }, { - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)= ", - "Data_LA": "1", + "BriefDescription": "Actually retired uops.", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts all actually retired uops. Counting increments = by two for micro-fused uops, and by one for macro-fused and other uops. Max= imal increment value for one cycle is eight.", + "PublicDescription": "This event counts all actually retired uops.= Counting increments by two for micro-fused uops, and by one for macro-fuse= d and other uops. Maximal increment value for one cycle is eight.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)= ", + "BriefDescription": "Retirement slots used.", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEB= S) of the event that counts the number of retirement slots used.", + "PublicDescription": "This event counts the number of retirement s= lots used.", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -1098,7 +1105,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "CounterMask": "10", + "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", "Invert": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json index b8c9845308b2..2bf23ef7bfac 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json @@ -78,7 +78,7 @@ "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Writeback transactions from L2 to the= LLC This includes all write transactions -- both Cachable and UC.", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Writeback transactions from L2 to the= LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", "Unit": "CBO" }, @@ -968,7 +968,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR. This includes requests that reside in the TOR for a short= time, such as LLC Hits that do not need to snoop cores or requests that ge= t rejected and have to be retried through one of the ingress queues. The T= OR is more commonly a bottleneck in skews with smaller core counts, where t= he ratio of RTIDs to TOR entries is larger. Note that there are reserved T= OR entries for various request types, so it is possible that a given reques= t type be blocked with an occupancy that is less than 20. Also note that g= enerally requests will not be able to arbitrate into the TOR pipeline if th= ere are no available TOR slots.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserte= d into the TOR. This includes requests that reside in the TOR for a shor= t time, such as LLC Hits that do not need to snoop cores or requests that g= et rejected and have to be retried through one of the ingress queues. The = TOR is more commonly a bottleneck in skews with smaller core counts, where = the ratio of RTIDs to TOR entries is larger. Note that there are reserved = TOR entries for various request types, so it is possible that a given reque= st type be blocked with an occupancy that is less than 20. Also note that = generally requests will not be able to arbitrate into the TOR pipeline if t= here are no available TOR slots.", "UMask": "0x8", "Unit": "CBO" }, @@ -977,7 +977,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions ins= erted into the TOR. Evictions can be quick, such as when the line is in th= e F, S, or E states and no core valid bits are set. They can also be longe= r if either CV bits are set (so the cores need to be snooped) and/or if the= re is a HitM (in which case it is necessary to write the request out to mem= ory).", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions in= serted into the TOR. Evictions can be quick, such as when the line is in t= he F, S, or E states and no core valid bits are set. They can also be long= er if either CV bits are set (so the cores need to be snooped) and/or if th= ere is a HitM (in which case it is necessary to write the request out to me= mory).", "UMask": "0x4", "Unit": "CBO" }, @@ -986,7 +986,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserte= d into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", "Unit": "CBO" }, @@ -995,7 +995,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisf= ied by an opcode, inserted into the TOR that are satisfied by locally HOMe= d memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1004,7 +1004,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", "Unit": "CBO" }, @@ -1013,7 +1013,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satis= fied by an opcode, inserted into the TOR that are satisfied by locally HOMe= d memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1022,7 +1022,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "UMask": "0x3", "Unit": "CBO" }, @@ -1031,7 +1031,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", "Unit": "CBO" }, @@ -1040,7 +1040,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by remote cache= s or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satis= fied by an opcode, inserted into the TOR that are satisfied by remote cach= es or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1049,7 +1049,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches = an RTID destination) transactions inserted into the TOR. The NID is progra= mmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it is= possible to monitor misses to specific NIDs in the system.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches= an RTID destination) transactions inserted into the TOR. The NID is progr= ammed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it i= s possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", "Unit": "CBO" }, @@ -1058,7 +1058,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction tran= sactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction tra= nsactions inserted into the TOR.", "UMask": "0x44", "Unit": "CBO" }, @@ -1067,7 +1067,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requ= ests that were inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss req= uests that were inserted into the TOR.", "UMask": "0x4a", "Unit": "CBO" }, @@ -1076,7 +1076,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match a NID and an opcode.", "UMask": "0x43", "Unit": "CBO" }, @@ -1085,7 +1085,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match a NID and an opcode.", "UMask": "0x41", "Unit": "CBO" }, @@ -1094,7 +1094,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transac= tions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transa= ctions inserted into the TOR.", "UMask": "0x50", "Unit": "CBO" }, @@ -1103,7 +1103,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -1112,7 +1112,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserte= d into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", "Unit": "CBO" }, @@ -1121,7 +1121,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by remote caches= or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisf= ied by an opcode, inserted into the TOR that are satisfied by remote cache= s or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1130,7 +1130,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions insert= ed into the TOR. This does not include RFO, but actual operations that co= ntain data being sent from the core.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inser= ted into the TOR. This does not include RFO, but actual operations that c= ontain data being sent from the core.", "UMask": "0x10", "Unit": "CBO" }, @@ -1166,7 +1166,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisfied by an opcode, in the TOR that are satis= fied by locally HOMed memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1193,7 +1193,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisfied by an opcode, in the TOR that are sa= tisfied by locally HOMed memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1220,7 +1220,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisfied by an opcode, in the TOR that are sa= tisfied by remote caches or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1301,7 +1301,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisfied by an opcode, in the TOR that are satis= fied by remote caches or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1388,7 +1388,7 @@ "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the BL ring. This is commonly used for= transfering writeback data to the cache.", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the BL ring. This is commonly used for= transferring writeback data to the cache.", "UMask": "0x40", "Unit": "CBO" }, @@ -1535,7 +1535,7 @@ "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", - "PublicDescription": "Directory Latency Optimization Data Return P= ath Taken. When directory mode is enabled and the directory retuned for a r= ead is Dir=3DI, then data can be returned using a faster path if certain co= nditions are met (credits, free pipeline, etc).", + "PublicDescription": "Directory Latency Optimization Data Return P= ath Taken. When directory mode is enabled and the directory returned for a = read is Dir=3DI, then data can be returned using a faster path if certain c= onditions are met (credits, free pipeline, etc).", "Unit": "HA" }, { @@ -2647,7 +2647,7 @@ "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspSFwd. This is returned when a remote cach= ing agent forwards data but holds on to its currentl copy. This is common = for data and code reads that hit in a remote socket in E or F state.", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspSFwd. This is returned when a remote cach= ing agent forwards data but holds on to its current copy. This is common f= or data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", "Unit": "HA" }, @@ -2719,7 +2719,7 @@ "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd. This is returned whe= n a remote caching agent forwards data but holds on to its currentl copy. = This is common for data and code reads that hit in a remote socket in E or = F state.", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd. This is returned whe= n a remote caching agent forwards data but holds on to its current copy. T= his is common for data and code reads that hit in a remote socket in E or F= state.", "UMask": "0x8", "Unit": "HA" }, @@ -2931,7 +2931,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE R= equests", + "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE = Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -2940,7 +2940,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE = Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE= Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -2949,7 +2949,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requ= ests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Read Req= uests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -2958,7 +2958,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Req= uests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Re= quests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -2967,7 +2967,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Write Req= uests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Write Re= quests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -2976,7 +2976,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Re= quests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Write R= equests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -2985,7 +2985,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Local Requ= ests", + "BriefDescription": "Data Pending Occupancy Accumulator; Local Req= uests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -2994,7 +2994,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Remote Req= uests", + "BriefDescription": "Data Pending Occupancy Accumulator; Remote Re= quests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json = b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json index c3f2f6c2ac74..a764234a3584 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json @@ -166,7 +166,7 @@ "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit erros in lockstep mode.", + "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { @@ -302,6 +302,7 @@ "Unit": "iMC" }, { + "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", "PerPkg": "1", @@ -487,6 +488,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -495,6 +497,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -502,6 +505,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -510,6 +514,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -518,6 +523,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -526,6 +532,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -534,6 +541,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -542,6 +550,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -550,6 +559,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -558,6 +568,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -566,6 +577,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -574,6 +586,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -582,6 +595,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -590,6 +604,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -598,6 +613,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -606,6 +622,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -614,6 +631,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -622,6 +640,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -630,6 +649,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -638,6 +658,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -646,6 +667,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -654,6 +676,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -662,6 +685,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -669,6 +693,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -677,6 +702,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -685,6 +711,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -693,6 +720,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -701,6 +729,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -709,6 +738,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -717,6 +747,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -725,6 +756,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -733,6 +765,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -741,6 +774,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -749,6 +783,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -757,6 +792,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -765,6 +801,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -773,6 +810,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -781,6 +819,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -789,6 +828,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -797,6 +837,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -805,6 +846,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -813,6 +855,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -821,6 +864,7 @@ "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -828,6 +872,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -836,6 +881,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -843,6 +889,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -851,6 +898,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -859,6 +907,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -867,6 +916,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -875,6 +925,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -883,6 +934,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -891,6 +943,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -899,6 +952,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -907,6 +961,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -915,6 +970,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -923,6 +979,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -931,6 +988,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -939,6 +997,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -947,6 +1006,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -955,6 +1015,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -963,6 +1024,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -971,6 +1033,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -979,6 +1042,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -987,6 +1051,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -995,6 +1060,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1003,6 +1069,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1010,6 +1077,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1018,6 +1086,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1026,6 +1095,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1034,6 +1104,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1042,6 +1113,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1050,6 +1122,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1058,6 +1131,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1066,6 +1140,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1074,6 +1149,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1082,6 +1158,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1090,6 +1167,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1098,6 +1176,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1106,6 +1185,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1114,6 +1194,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1122,6 +1203,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1130,6 +1212,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1138,6 +1221,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1146,6 +1230,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1154,6 +1239,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1162,6 +1248,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1170,6 +1257,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1177,6 +1265,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1185,6 +1274,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1193,6 +1283,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1201,6 +1292,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1209,6 +1301,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1217,6 +1310,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1225,6 +1319,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1233,6 +1328,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1241,6 +1337,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1249,6 +1346,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1257,6 +1355,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1265,6 +1364,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1273,6 +1373,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1281,6 +1382,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1289,6 +1391,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1297,6 +1400,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1305,6 +1409,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1313,6 +1418,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1321,6 +1427,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1329,6 +1436,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1337,6 +1445,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1344,6 +1453,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1352,6 +1462,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1360,6 +1471,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1368,6 +1480,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1376,6 +1489,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1384,6 +1498,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1392,6 +1507,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1400,6 +1516,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1408,6 +1525,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1416,6 +1534,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1424,6 +1543,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1432,6 +1552,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1440,6 +1561,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1448,6 +1570,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1456,6 +1579,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1464,6 +1588,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1472,6 +1597,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1480,6 +1606,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1488,6 +1615,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1598,6 +1726,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1606,6 +1735,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1613,6 +1743,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1621,6 +1752,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1629,6 +1761,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1637,6 +1770,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1645,6 +1779,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1653,6 +1788,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1661,6 +1797,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1669,6 +1806,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1677,6 +1815,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1685,6 +1824,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1693,6 +1833,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1701,6 +1842,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1709,6 +1851,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1717,6 +1860,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1725,6 +1869,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1733,6 +1878,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1741,6 +1887,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1749,6 +1896,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1757,6 +1905,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1765,6 +1914,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1773,6 +1923,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1780,6 +1931,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1788,6 +1940,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1796,6 +1949,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1804,6 +1958,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1812,6 +1967,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1820,6 +1976,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1828,6 +1985,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1836,6 +1994,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1844,6 +2003,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1852,6 +2012,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1860,6 +2021,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1868,6 +2030,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1876,6 +2039,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1884,6 +2048,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1892,6 +2057,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1900,6 +2066,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1908,6 +2075,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1916,6 +2084,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1924,6 +2093,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1932,6 +2102,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1940,6 +2111,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1947,6 +2119,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1955,6 +2128,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1963,6 +2137,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1971,6 +2146,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1979,6 +2155,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1987,6 +2164,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1995,6 +2173,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2003,6 +2182,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2011,6 +2191,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2019,6 +2200,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2027,6 +2209,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2035,6 +2218,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2043,6 +2227,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2051,6 +2236,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2059,6 +2245,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2067,6 +2254,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2075,6 +2263,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2083,6 +2272,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2091,6 +2281,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2099,6 +2290,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2107,6 +2299,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2114,6 +2307,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2122,6 +2316,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2130,6 +2325,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2138,6 +2334,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2146,6 +2343,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2154,6 +2352,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2162,6 +2361,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2170,6 +2370,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2178,6 +2379,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2186,6 +2388,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2194,6 +2397,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2202,6 +2406,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2210,6 +2415,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2218,6 +2424,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2226,6 +2433,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2234,6 +2442,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2242,6 +2451,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2250,6 +2460,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2258,6 +2469,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2266,6 +2478,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2274,6 +2487,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2281,6 +2495,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2289,6 +2504,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2297,6 +2513,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2305,6 +2522,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2313,6 +2531,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2321,6 +2540,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2329,6 +2549,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2337,6 +2558,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2345,6 +2567,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2353,6 +2576,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2361,6 +2585,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2369,6 +2594,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2377,6 +2603,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2385,6 +2612,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2393,6 +2621,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2401,6 +2630,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2409,6 +2639,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2417,6 +2648,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2425,6 +2657,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2433,6 +2666,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2441,6 +2675,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2448,6 +2683,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2456,6 +2692,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2464,6 +2701,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2472,6 +2710,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2480,6 +2719,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2488,6 +2728,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2496,6 +2737,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2504,6 +2746,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2512,6 +2755,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2520,6 +2764,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2528,6 +2773,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2536,6 +2782,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2544,6 +2791,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2552,6 +2800,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2560,6 +2809,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2568,6 +2818,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2576,6 +2827,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2584,6 +2836,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2592,6 +2845,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" } diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json index 753b381b77fe..fea3dea67f38 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json @@ -101,6 +101,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of A= tomic Transactions as Secondary", "UMask": "0x10", "Unit": "IRP" }, @@ -109,6 +110,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of R= ead Transactions as Secondary", "UMask": "0x4", "Unit": "IRP" }, @@ -117,6 +119,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of W= rite Transactions as Secondary", "UMask": "0x8", "Unit": "IRP" }, @@ -125,6 +128,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", "UMask": "0x2", "Unit": "IRP" }, @@ -133,6 +137,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", "UMask": "0x1", "Unit": "IRP" }, @@ -141,6 +146,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers= From Primary to Secondary", "UMask": "0x20", "Unit": "IRP" }, @@ -149,6 +155,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints= From Primary to Secondary", "UMask": "0x40", "Unit": "IRP" }, @@ -175,6 +182,7 @@ "EventCode": "0x15", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop p= ulled away ownership before a write was committed", "UMask": "0x10", "Unit": "IRP" }, @@ -241,6 +249,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "EventCode": "0x4", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", @@ -256,6 +265,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", "EventCode": "0x7", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", @@ -263,6 +273,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "EventCode": "0x5", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", @@ -278,6 +289,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", "EventCode": "0x8", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", @@ -285,6 +297,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "EventCode": "0x6", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", @@ -300,6 +313,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", "EventCode": "0x9", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", @@ -311,6 +325,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit E or S", "UMask": "0x4", "Unit": "IRP" }, @@ -319,6 +334,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit I", "UMask": "0x2", "Unit": "IRP" }, @@ -327,6 +343,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit M", "UMask": "0x8", "Unit": "IRP" }, @@ -335,6 +352,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Miss", "UMask": "0x1", "Unit": "IRP" }, @@ -343,6 +361,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpCode", "UMask": "0x10", "Unit": "IRP" }, @@ -351,6 +370,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpData", "UMask": "0x20", "Unit": "IRP" }, @@ -359,6 +379,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpInv", "UMask": "0x40", "Unit": "IRP" }, @@ -453,7 +474,7 @@ "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outboun= d requests from the IRP to the switch (towards the devices). This can be u= sed in conjuection with the allocations event in order to calculate average= latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbou= nd requests from the IRP to the switch (towards the devices). This can be = used in conjunction with the allocations event in order to calculate averag= e latency of outbound requests.", "Unit": "IRP" }, { @@ -465,6 +486,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", "PerPkg": "1", @@ -472,6 +494,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", "PerPkg": "1", @@ -479,6 +502,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", "PerPkg": "1", @@ -486,6 +510,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json index 124b3fe2e0e1..83d20130c217 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json @@ -395,7 +395,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "Unit": "PCU" }, { @@ -403,7 +403,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "Unit": "PCU" }, { @@ -411,7 +411,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "Unit": "PCU" }, { @@ -427,7 +427,7 @@ "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that we are in I= nteral PROCHOT mode. This mode is triggered when a sensor on the die deter= mines that we are too hot and must throttle to avoid damaging the chip.", + "PublicDescription": "Counts the number of cycles that we are in I= nternal PROCHOT mode. This mode is triggered when a sensor on the die dete= rmines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { @@ -439,6 +439,7 @@ "Unit": "PCU" }, { + "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV", "EventCode": "0x79", "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", "PerPkg": "1", @@ -450,6 +451,7 @@ "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", + "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 70be860bcb53..4fa827c7f719 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -3,7 +3,7 @@ GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v27,broadwell,core -GenuineIntel-6-56,v7,broadwellde,core +GenuineIntel-6-56,v9,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4EEAC6FD1C for ; Thu, 23 Mar 2023 19:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231445AbjCWTVv (ORCPT ); Thu, 23 Mar 2023 15:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231225AbjCWTV3 (ORCPT ); Thu, 23 Mar 2023 15:21:29 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 54E4FAD31 for ; Thu, 23 Mar 2023 12:21:04 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-541a39df9f4so231863337b3.20 for ; Thu, 23 Mar 2023 12:21:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599263; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=htXY5sGJDItXY75tNu49iHBFf3vGbWbJLizWWx2z1Vo=; b=IdvLafgxSR99BNyomNND25dx5vbj+70jGDWExnU5DmF0WRDlfuEy12vBaXut75H5mc W0UfammjZuHhj/hshEr98A2e/SkKJ3LHjLJ7pEBzDnDQoGgA5jqdUFx9WUrMgtphcNGZ vmWIxeZMH1MyGX9U9NOlJUkm76JaS5kOxV9VziJ0pNS7i/VDGujmQYlBfWhQV2XiCwfD DlMYkLIlsrPV0cwvrA9a5C/WZan9AACmGJjHKqXBrTyMUNnPyF2d0sM/KprMjJYCDcfL ri3u0yCORVVT83lRIwIa6JAtQ3BKDq/ZlenRquJymVUj3dqI303NIArB9ZeRVEM8MToK zK/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599263; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=htXY5sGJDItXY75tNu49iHBFf3vGbWbJLizWWx2z1Vo=; b=nZEy0BezwCvf1sR0KmcQ8bB/FRAfTSXqP+q5w2rRRmNsBewLTT/2CONfq4z/mHAYAX uF7bIDA40ET2Jzn7WaG2jxtdY6h4RNozYkIT7L8n0SytOPHogpy7JUtfG5p5U1EPWO0u Miajs9Kw1W8i9Q7Q4o4nSU7Hy8c8DK7poDsO4XpV/u/CT6/3ogplJEkZrsrtC1rxszQ9 1FrWlGaBos34BAi0hoNmPejd0kvE4AHR24OkDgLd7DhIdamrXQCx4IsT1pKb364dChfV 0RI8+yIpPCUBY3A6cwF2UUyZ/Pz4gYLw/c8WeGl3mSGbFKW7/pxQ1hf7bAaKksOaVKhL xPmw== X-Gm-Message-State: AAQBX9d6K9HWpMzpX69DPkQliTA7EuNH3+FDaAxLWiQTAp/7V+/04wcf hfGJrJe+yOIq9ay9flCbFml+aK3lrNdH X-Google-Smtp-Source: AKy350aiGY+475mVxvHTvPWw0zIs+cV7xUb3Lxc9T+p9p4H6AUAgWYwq4ddlVinmSg2FfRtN8YOnq4vRTYzw X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a81:4423:0:b0:541:6aa7:f889 with SMTP id r35-20020a814423000000b005416aa7f889mr2353963ywa.5.1679599263596; Thu, 23 Mar 2023 12:21:03 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:22 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-4-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 3/9] perf vendor events: Broadwellx v20 events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/broadwellx/cache.json | 16 +- .../arch/x86/broadwellx/frontend.json | 18 +- .../arch/x86/broadwellx/pipeline.json | 20 +- .../arch/x86/broadwellx/uncore-cache.json | 156 ++---- .../x86/broadwellx/uncore-interconnect.json | 84 +-- .../arch/x86/broadwellx/uncore-memory.json | 522 +++++++++--------- .../arch/x86/broadwellx/uncore-other.json | 44 +- .../arch/x86/broadwellx/uncore-power.json | 10 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 9 files changed, 403 insertions(+), 469 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/p= erf/pmu-events/arch/x86/broadwellx/cache.json index 6a134928b3f0..781e7c64e71f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -16,7 +16,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", @@ -454,22 +454,22 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "This event counts load uops retired to the a= rchitected path with a filter on bits 0 and 1 applied.\nNote: This event co= unts AVX-256bit load/store double-pump memory uops as a single uop at retir= ement. This event also counts SW prefetches.", + "PublicDescription": "Counts all retired load uops. This event acc= ounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired store uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PublicDescription": "This event counts store uops retired to the = architected path with a filter on bits 0 and 1 applied.\nNote: This event c= ounts AVX-256bit load/store double-pump memory uops as a single uop at reti= rement.", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -541,10 +541,10 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests= ", + "BriefDescription": "Cacheable and non-cacheable code read request= s", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncach= aeble code read requests.", + "PublicDescription": "This event counts both cacheable and non-cac= heable code read requests.", "SampleAfterValue": "100003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tool= s/perf/pmu-events/arch/x86/broadwellx/frontend.json index d0f6678609ae..bd5da39564e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json @@ -125,16 +125,16 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts cycles during which uops a= re being delivered to Instruction Decode Queue (IDQ) while the Microcode Se= quencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops = maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is b= usy", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -153,7 +153,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", @@ -161,10 +161,10 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.= ", + "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.= ", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -178,10 +178,10 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tool= s/perf/pmu-events/arch/x86/broadwellx/pipeline.json index 75233316640b..9a902d2160e6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json @@ -214,6 +214,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", "EventCode": "0x89", @@ -500,7 +508,7 @@ "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to chan= ging prefix length (66, 67 or REX.W when they change the length of the deco= ded instruction). Occurrences counting is proportional to the number of pre= fixes in a 16B-line. This may result in the following penalties: three-cycl= e penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to cha= nging prefix length (66, 67 or REX.W when they change the length of the dec= oded instruction). Occurrences counting is proportional to the number of pr= efixes in a 16B-line. This may result in the following penalties: three-cyc= le penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -909,7 +917,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 0.", + "BriefDescription": "Cycles per core when uops are executed in por= t 0.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,7 +933,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 1.", + "BriefDescription": "Cycles per core when uops are executed in por= t 1.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -973,7 +981,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 4.", + "BriefDescription": "Cycles per core when uops are executed in por= t 4.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,7 +997,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 5.", + "BriefDescription": "Cycles per core when uops are executed in por= t 5.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,7 +1013,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in po= rt 6.", + "BriefDescription": "Cycles per core when uops are executed in por= t 6.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/= tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json index 746954775437..f794d2992323 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json @@ -5,7 +5,7 @@ "EventName": "LLC_MISSES.CODE_LLC_PREFETCH", "Filter": "filter_opc=3D0x191", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -16,7 +16,7 @@ "EventName": "LLC_MISSES.DATA_LLC_PREFETCH", "Filter": "filter_opc=3D0x192", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -27,7 +27,7 @@ "EventName": "LLC_MISSES.DATA_READ", "Filter": "filter_opc=3D0x182", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -38,7 +38,7 @@ "EventName": "LLC_MISSES.MMIO_READ", "Filter": "filter_opc=3D0x187,filter_nc=3D1", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -49,7 +49,7 @@ "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "filter_opc=3D0x18f,filter_nc=3D1", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -60,7 +60,7 @@ "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE", "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -71,7 +71,7 @@ "EventName": "LLC_MISSES.PCIE_READ", "Filter": "filter_opc=3D0x19e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -82,7 +82,7 @@ "EventName": "LLC_MISSES.PCIE_WRITE", "Filter": "filter_opc=3D0x1c8", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -93,7 +93,7 @@ "EventName": "LLC_MISSES.RFO_LLC_PREFETCH", "Filter": "filter_opc=3D0x190", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -104,7 +104,7 @@ "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "filter_opc=3D0x187", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -115,7 +115,7 @@ "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", "Filter": "filter_opc=3D0x181", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -126,7 +126,7 @@ "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", "Filter": "filter_opc=3D0x180,filter_tid=3D0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -136,7 +136,7 @@ "EventName": "LLC_REFERENCES.PCIE_READ", "Filter": "filter_opc=3D0x19e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -147,7 +147,7 @@ "EventName": "LLC_REFERENCES.PCIE_WRITE", "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -158,7 +158,7 @@ "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "filter_opc=3D0x18c", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -169,7 +169,7 @@ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "filter_opc=3D0x18d", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -179,14 +179,12 @@ "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", - "PublicDescription": "UNC_C_BOUNCE_CONTROL", "Unit": "CBO" }, { "BriefDescription": "Uncore Clocks", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "UNC_C_CLOCKTICKS", "Unit": "CBO" }, { @@ -257,7 +255,7 @@ "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Writeback transactions from L2 to the= LLC This includes all write transactions -- both Cachable and UC.", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:1= 8] bits correspond to [FMESI] state.; Writeback transactions from L2 to the= LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", "Unit": "CBO" }, @@ -618,7 +616,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.AD", "UMask": "0x1", "Unit": "CBO" }, @@ -627,7 +624,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.AK", "UMask": "0x2", "Unit": "CBO" }, @@ -636,7 +632,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.BL", "UMask": "0x4", "Unit": "CBO" }, @@ -645,7 +640,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.IV", "UMask": "0x10", "Unit": "CBO" }, @@ -690,7 +684,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.AD", "UMask": "0x1", "Unit": "CBO" }, @@ -699,7 +692,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.AK", "UMask": "0x2", "Unit": "CBO" }, @@ -708,7 +700,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.BL", "UMask": "0x4", "Unit": "CBO" }, @@ -717,7 +708,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.IV", "UMask": "0x8", "Unit": "CBO" }, @@ -726,7 +716,6 @@ "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SRC_THRTL", "Unit": "CBO" }, { @@ -1157,7 +1146,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR. This includes requests that reside in the TOR for a short= time, such as LLC Hits that do not need to snoop cores or requests that ge= t rejected and have to be retried through one of the ingress queues. The T= OR is more commonly a bottleneck in skews with smaller core counts, where t= he ratio of RTIDs to TOR entries is larger. Note that there are reserved T= OR entries for various request types, so it is possible that a given reques= t type be blocked with an occupancy that is less than 20. Also note that g= enerally requests will not be able to arbitrate into the TOR pipeline if th= ere are no available TOR slots.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserte= d into the TOR. This includes requests that reside in the TOR for a shor= t time, such as LLC Hits that do not need to snoop cores or requests that g= et rejected and have to be retried through one of the ingress queues. The = TOR is more commonly a bottleneck in skews with smaller core counts, where = the ratio of RTIDs to TOR entries is larger. Note that there are reserved = TOR entries for various request types, so it is possible that a given reque= st type be blocked with an occupancy that is less than 20. Also note that = generally requests will not be able to arbitrate into the TOR pipeline if t= here are no available TOR slots.", "UMask": "0x8", "Unit": "CBO" }, @@ -1166,7 +1155,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions ins= erted into the TOR. Evictions can be quick, such as when the line is in th= e F, S, or E states and no core valid bits are set. They can also be longe= r if either CV bits are set (so the cores need to be snooped) and/or if the= re is a HitM (in which case it is necessary to write the request out to mem= ory).", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions in= serted into the TOR. Evictions can be quick, such as when the line is in t= he F, S, or E states and no core valid bits are set. They can also be long= er if either CV bits are set (so the cores need to be snooped) and/or if th= ere is a HitM (in which case it is necessary to write the request out to me= mory).", "UMask": "0x4", "Unit": "CBO" }, @@ -1175,7 +1164,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserte= d into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", "Unit": "CBO" }, @@ -1184,7 +1173,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisf= ied by an opcode, inserted into the TOR that are satisfied by locally HOMe= d memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1193,7 +1182,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", "Unit": "CBO" }, @@ -1202,7 +1191,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by locally HOMed= memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satis= fied by an opcode, inserted into the TOR that are satisfied by locally HOMe= d memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1211,7 +1200,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match an opcode.", "UMask": "0x3", "Unit": "CBO" }, @@ -1220,7 +1209,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", "Unit": "CBO" }, @@ -1229,7 +1218,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisi= fed by an opcode, inserted into the TOR that are satisifed by remote cache= s or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satis= fied by an opcode, inserted into the TOR that are satisfied by remote cach= es or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1238,7 +1227,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches = an RTID destination) transactions inserted into the TOR. The NID is progra= mmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it is= possible to monitor misses to specific NIDs in the system.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches= an RTID destination) transactions inserted into the TOR. The NID is progr= ammed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE =3D I, it i= s possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", "Unit": "CBO" }, @@ -1247,7 +1236,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction tran= sactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction tra= nsactions inserted into the TOR.", "UMask": "0x44", "Unit": "CBO" }, @@ -1256,7 +1245,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requ= ests that were inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss req= uests that were inserted into the TOR.", "UMask": "0x4a", "Unit": "CBO" }, @@ -1265,7 +1254,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserte= d into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions insert= ed into the TOR that match a NID and an opcode.", "UMask": "0x43", "Unit": "CBO" }, @@ -1274,7 +1263,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match a NID and an opcode.", "UMask": "0x41", "Unit": "CBO" }, @@ -1283,7 +1272,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transac= tions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transa= ctions inserted into the TOR.", "UMask": "0x50", "Unit": "CBO" }, @@ -1292,7 +1281,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted int= o the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted in= to the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -1301,7 +1290,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted= into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserte= d into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", "Unit": "CBO" }, @@ -1310,7 +1299,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisif= ed by an opcode, inserted into the TOR that are satisifed by remote caches= or remote memory.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisf= ied by an opcode, inserted into the TOR that are satisfied by remote cache= s or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1319,7 +1308,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly ins= erted into the TOR that match qualifications specified by the subevent. T= here are a number of subevent 'filters' but only a subset of the subevent c= ombinations are valid. Subevents that require an opcode or NID match requi= re the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example,= one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and= set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions insert= ed into the TOR. This does not include RFO, but actual operations that co= ntain data being sent from the core.", + "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = There are a number of subevent 'filters' but only a subset of the subevent = combinations are valid. Subevents that require an opcode or NID match requ= ire the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example= , one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH an= d set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inser= ted into the TOR. This does not include RFO, but actual operations that c= ontain data being sent from the core.", "UMask": "0x10", "Unit": "CBO" }, @@ -1365,7 +1354,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisfied by an opcode, in the TOR that are satis= fied by locally HOMed memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1392,7 +1381,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisfied by an opcode, in the TOR that are sa= tisfied by locally HOMed memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1419,7 +1408,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisifed by an opcode, in the TOR that are sa= tisifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding Miss transactions, satisfied by an opcode, in the TOR that are sa= tisfied by remote caches or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1500,7 +1489,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisifed by an opcode, in the TOR that are satis= ifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of ou= tstanding transactions, satisfied by an opcode, in the TOR that are satis= fied by remote caches or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1518,7 +1507,6 @@ "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", - "PublicDescription": "UNC_C_TxR_ADS_USED.AD", "UMask": "0x1", "Unit": "CBO" }, @@ -1527,7 +1515,6 @@ "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", - "PublicDescription": "UNC_C_TxR_ADS_USED.AK", "UMask": "0x2", "Unit": "CBO" }, @@ -1536,7 +1523,6 @@ "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", - "PublicDescription": "UNC_C_TxR_ADS_USED.BL", "UMask": "0x4", "Unit": "CBO" }, @@ -1590,7 +1576,7 @@ "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the BL ring. This is commonly used for= transfering writeback data to the cache.", + "PublicDescription": "Number of allocations into the Cbo Egress. = The Egress is used to queue up requests destined for the ring.; Ring transa= ctions from the Corebo destined for the BL ring. This is commonly used for= transferring writeback data to the cache.", "UMask": "0x40", "Unit": "CBO" }, @@ -1737,7 +1723,7 @@ "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", - "PublicDescription": "Directory Latency Optimization Data Return P= ath Taken. When directory mode is enabled and the directory retuned for a r= ead is Dir=3DI, then data can be returned using a faster path if certain co= nditions are met (credits, free pipeline, etc).", + "PublicDescription": "Directory Latency Optimization Data Return P= ath Taken. When directory mode is enabled and the directory returned for a = read is Dir=3DI, then data can be returned using a faster path if certain c= onditions are met (credits, free pipeline, etc).", "Unit": "HA" }, { @@ -1790,7 +1776,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.ACKCNFLTWBI", "UMask": "0x4", "Unit": "HA" }, @@ -1799,7 +1784,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.ALL", "UMask": "0xff", "Unit": "HA" }, @@ -1808,7 +1792,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALLOCS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.ALLOCS", "UMask": "0x70", "Unit": "HA" }, @@ -1817,7 +1800,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.EVICTS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.EVICTS", "UMask": "0x42", "Unit": "HA" }, @@ -1826,7 +1808,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.HOM", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.HOM", "UMask": "0xf", "Unit": "HA" }, @@ -1835,7 +1816,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.INVALS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.INVALS", "UMask": "0x26", "Unit": "HA" }, @@ -1844,7 +1824,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.READ_OR_INVITOE", "UMask": "0x1", "Unit": "HA" }, @@ -1853,7 +1832,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSP", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSP", "UMask": "0x80", "Unit": "HA" }, @@ -1862,7 +1840,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", "UMask": "0x20", "Unit": "HA" }, @@ -1871,7 +1848,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", "UMask": "0x10", "Unit": "HA" }, @@ -1880,7 +1856,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSPFWDS", "UMask": "0x40", "Unit": "HA" }, @@ -1889,7 +1864,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.WBMTOE_OR_S", "UMask": "0x8", "Unit": "HA" }, @@ -1898,7 +1872,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.WBMTOI", "UMask": "0x2", "Unit": "HA" }, @@ -1907,7 +1880,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", "UMask": "0x4", "Unit": "HA" }, @@ -1916,7 +1888,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", "UMask": "0xff", "Unit": "HA" }, @@ -1925,7 +1896,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", "UMask": "0xf", "Unit": "HA" }, @@ -1934,7 +1904,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", "UMask": "0x1", "Unit": "HA" }, @@ -1943,7 +1912,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", "UMask": "0x80", "Unit": "HA" }, @@ -1952,7 +1920,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", "UMask": "0x20", "Unit": "HA" }, @@ -1961,7 +1928,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", "UMask": "0x10", "Unit": "HA" }, @@ -1970,7 +1936,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", "UMask": "0x40", "Unit": "HA" }, @@ -1979,7 +1944,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", "UMask": "0x8", "Unit": "HA" }, @@ -1988,7 +1952,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", "UMask": "0x2", "Unit": "HA" }, @@ -1997,7 +1960,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", "UMask": "0x4", "Unit": "HA" }, @@ -2006,7 +1968,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.ALL", "UMask": "0xff", "Unit": "HA" }, @@ -2015,7 +1976,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALLOCS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.ALLOCS", "UMask": "0x70", "Unit": "HA" }, @@ -2024,7 +1984,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.HOM", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.HOM", "UMask": "0xf", "Unit": "HA" }, @@ -2033,7 +1992,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.INVALS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.INVALS", "UMask": "0x26", "Unit": "HA" }, @@ -2042,7 +2000,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", "UMask": "0x1", "Unit": "HA" }, @@ -2051,7 +2008,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSP", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSP", "UMask": "0x80", "Unit": "HA" }, @@ -2060,7 +2016,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", "UMask": "0x20", "Unit": "HA" }, @@ -2069,7 +2024,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", "UMask": "0x10", "Unit": "HA" }, @@ -2078,7 +2032,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDS", "UMask": "0x40", "Unit": "HA" }, @@ -2087,7 +2040,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", "UMask": "0x8", "Unit": "HA" }, @@ -2096,7 +2048,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOI", "UMask": "0x2", "Unit": "HA" }, @@ -2168,7 +2119,6 @@ "EventCode": "0x1E", "EventName": "UNC_H_IMC_RETRY", "PerPkg": "1", - "PublicDescription": "UNC_H_IMC_RETRY", "Unit": "HA" }, { @@ -2221,7 +2171,6 @@ "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.HUB", "PerPkg": "1", - "PublicDescription": "UNC_H_IOT_BACKPRESSURE.HUB", "UMask": "0x2", "Unit": "HA" }, @@ -2230,7 +2179,6 @@ "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.SAT", "PerPkg": "1", - "PublicDescription": "UNC_H_IOT_BACKPRESSURE.SAT", "UMask": "0x1", "Unit": "HA" }, @@ -2889,7 +2837,7 @@ "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspSFwd. This is returned when a remote cach= ing agent forwards data but holds on to its currentl copy. This is common = for data and code reads that hit in a remote socket in E or F state.", + "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspSFwd. This is returned when a remote cach= ing agent forwards data but holds on to its current copy. This is common f= or data and code reads that hit in a remote socket in E or F state.", "ScaleUnit": "64Bytes", "UMask": "0x8", "Unit": "HA" @@ -2963,7 +2911,7 @@ "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd. This is returned whe= n a remote caching agent forwards data but holds on to its currentl copy. = This is common for data and code reads that hit in a remote socket in E or = F state.", + "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd. This is returned whe= n a remote caching agent forwards data but holds on to its current copy. T= his is common for data and code reads that hit in a remote socket in E or F= state.", "UMask": "0x8", "Unit": "HA" }, @@ -3175,7 +3123,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE R= equests", + "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE = Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -3184,7 +3132,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE = Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE= Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -3193,7 +3141,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requ= ests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Read Req= uests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -3202,7 +3150,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Req= uests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Re= quests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -3211,7 +3159,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Write Req= uests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Write Re= quests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -3220,7 +3168,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Re= quests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Write R= equests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -3229,7 +3177,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Local Requ= ests", + "BriefDescription": "Data Pending Occupancy Accumulator; Local Req= uests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -3238,7 +3186,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Remote Req= uests", + "BriefDescription": "Data Pending Occupancy Accumulator; Remote Re= quests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json index 489a3673323d..2819c6621089 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json @@ -3,7 +3,7 @@ "BriefDescription": "Number of non data (control) flits transmitte= d . Derived from unc_q_txl_flits_g0.non_data", "EventName": "QPI_CTL_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transfering a 64B= cacheline across QPI, we will break it into 9 flits -- 1 with header infor= mation and 8 with 64 bits of actual data and an additional 16 bits of other= information. To calculate data bandwidth, one should therefore do: data f= lits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL = non-data flits transmitted across QPI. This basically tracks the protocol = overhead on the QPI link. One can get a good picture of the QPI-link chara= cteristics by evaluating the protocol flits, data flits, and idle/null flit= s. This includes the header flits for data packets.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL= non-data flits transmitted across QPI. This basically tracks the protocol= overhead on the QPI link. One can get a good picture of the QPI-link char= acteristics by evaluating the protocol flits, data flits, and idle/null fli= ts. This includes the header flits for data packets.", "ScaleUnit": "8Bytes", "UMask": "0x4", "Unit": "QPI LL" @@ -12,7 +12,7 @@ "BriefDescription": "Number of data flits transmitted . Derived fr= om unc_q_txl_flits_g0.data", "EventName": "QPI_DATA_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transfering a 64B= cacheline across QPI, we will break it into 9 flits -- 1 with header infor= mation and 8 with 64 bits of actual data and an additional 16 bits of other= information. To calculate data bandwidth, one should therefore do: data f= lits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flit= s transmitted over QPI. Each flit contains 64b of data. This includes bot= h DRS and NCB data flits (coherent and non-coherent). This can be used to = calculate the data bandwidth of the QPI link. One can get a good picture o= f the QPI-link characteristics by evaluating the protocol flits, data flits= , and idle/null flits. This does not include the header flits that go in d= ata packets.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data fli= ts transmitted over QPI. Each flit contains 64b of data. This includes bo= th DRS and NCB data flits (coherent and non-coherent). This can be used to= calculate the data bandwidth of the QPI link. One can get a good picture = of the QPI-link characteristics by evaluating the protocol flits, data flit= s, and idle/null flits. This does not include the header flits that go in = data packets.", "ScaleUnit": "8Bytes", "UMask": "0x2", "Unit": "QPI LL" @@ -38,7 +38,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because there were not enough Egress = credits. Had there been enough credits, the spawn would have worked as the= RBT bit was set and the RBT tag matched.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn failed because there were not enough Egress= credits. Had there been enough credits, the spawn would have worked as th= e RBT bit was set and the RBT tag matched.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -47,7 +47,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match and= there weren't enough Egress credits. The valid bit was set.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn failed because the RBT tag did not match an= d there weren't enough Egress credits. The valid bit was set.", "UMask": "0x20", "Unit": "QPI LL" }, @@ -56,7 +56,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because there were not enough Egress = credits AND the RBT bit was not set, but the RBT tag matched.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn failed because there were not enough Egress= credits AND the RBT bit was not set, but the RBT tag matched.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -65,7 +65,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match, th= e valid bit was not set and there weren't enough Egress credits.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn failed because the RBT tag did not match, t= he valid bit was not set and there weren't enough Egress credits.", "UMask": "0x80", "Unit": "QPI LL" }, @@ -74,7 +74,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match alt= hough the valid bit was set and there were enough Egress credits.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn failed because the RBT tag did not match al= though the valid bit was set and there were enough Egress credits.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -83,7 +83,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the route-back table (RBT) sp= ecified that the transaction should not trigger a direct2core tranaction. = This is common for IO transactions. There were enough Egress credits and t= he RBT tag matched but the valid bit was not set.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn failed because the route-back table (RBT) s= pecified that the transaction should not trigger a direct2core transaction.= This is common for IO transactions. There were enough Egress credits and= the RBT tag matched but the valid bit was not set.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -92,7 +92,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn failed because the RBT tag did not match and= the valid bit was not set although there were enough Egress credits.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn failed because the RBT tag did not match an= d the valid bit was not set although there were enough Egress credits.", "UMask": "0x40", "Unit": "QPI LL" }, @@ -101,7 +101,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exlusive filters. Filte= r [0] can be used to get successful spawns, while [1:3] provide the differe= nt failure cases. Note that this does not count packets that are not candi= dates for Direct2Core. The only candidates for Direct2Core are DRS packets= destined for Cbos.; The spawn was successful. There were sufficient credi= ts, the RBT valid bit was set and there was an RBT tag match. The message = was marked to spawn direct2core.", + "PublicDescription": "Counts the number of DRS packets that we att= empted to do direct2core on. There are 4 mutually exclusive filters. Filt= er [0] can be used to get successful spawns, while [1:3] provide the differ= ent failure cases. Note that this does not count packets that are not cand= idates for Direct2Core. The only candidates for Direct2Core are DRS packet= s destined for Cbos.; The spawn was successful. There were sufficient cred= its, the RBT valid bit was set and there was an RBT tag match. The message= was marked to spawn direct2core.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -134,7 +134,7 @@ "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming = flit was able to bypass the flit buffer and pass directly across the BGF an= d into the Egress. This is a latency optimization, and should generally be= the common case. If this value is less than the number of flits transfere= d, it implies that there was queueing getting onto the ring, and thus the t= ransactions saw higher latency.", + "PublicDescription": "Counts the number of times that an incoming = flit was able to bypass the flit buffer and pass directly across the BGF an= d into the Egress. This is a latency optimization, and should generally be= the common case. If this value is less than the number of flits transferr= ed, it implies that there was queueing getting onto the ring, and thus the = transactions saw higher latency.", "Unit": "QPI LL" }, { @@ -391,7 +391,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each f= lit is made up of 80 bits of information (in addition to some ECC data). I= n full-width (L0) mode, flits are made up of four fits, each of which conta= ins 20 bits of data (along with some additional ECC data). In half-width = (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many= fits to transmit a flit. When one talks about QPI speed (for example, 8.0= GT/s), the transfers here refer to fits. Therefore, in L0, the system wil= l transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate th= e bandwidth of the link by taking: flits*80b/time. Note that this is not t= he same as data bandwidth. For example, when we are transfering a 64B cach= eline across QPI, we will break it into 9 flits -- 1 with header informatio= n and 8 with 64 bits of actual data and an additional 16 bits of other info= rmation. To calculate data bandwidth, one should therefore do: data flits = * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received= over QPI that do not hold protocol payload. When QPI is not in a power sa= ving state, it continuously transmits flits across the link. When there ar= e no protocol flits to send, it will send IDLE and NULL flits across. The= se flits sometimes do carry a payload, such as credit returns, but are gene= rall not considered part of the QPI bandwidth.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. It includes filters for Idle, protocol, and Data Flits. Each f= lit is made up of 80 bits of information (in addition to some ECC data). I= n full-width (L0) mode, flits are made up of four fits, each of which conta= ins 20 bits of data (along with some additional ECC data). In half-width = (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many= fits to transmit a flit. When one talks about QPI speed (for example, 8.0= GT/s), the transfers here refer to fits. Therefore, in L0, the system wil= l transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate th= e bandwidth of the link by taking: flits*80b/time. Note that this is not t= he same as data bandwidth. For example, when we are transferring a 64B cac= heline across QPI, we will break it into 9 flits -- 1 with header informati= on and 8 with 64 bits of actual data and an additional 16 bits of other inf= ormation. To calculate data bandwidth, one should therefore do: data flits= * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits receive= d over QPI that do not hold protocol payload. When QPI is not in a power s= aving state, it continuously transmits flits across the link. When there a= re no protocol flits to send, it will send IDLE and NULL flits across. Th= ese flits sometimes do carry a payload, such as credit returns, but are gen= erally not considered part of the QPI bandwidth.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -400,7 +400,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of flits received over QPI on the DRS (Data Respon= se) channel. DRS flits are used to transmit data with coherency. This doe= s not count data flits received over the NCB channel which transmits non-co= herent data.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the total number of flits received over QPI on the DRS (Data Respo= nse) channel. DRS flits are used to transmit data with coherency. This do= es not count data flits received over the NCB channel which transmits non-c= oherent data.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -409,7 +409,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of data flits received over QPI on the DRS (Data R= esponse) channel. DRS flits are used to transmit data with coherency. Thi= s does not count data flits received over the NCB channel which transmits n= on-coherent data. This includes only the data flits (not the header).", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the total number of data flits received over QPI on the DRS (Data = Response) channel. DRS flits are used to transmit data with coherency. Th= is does not count data flits received over the NCB channel which transmits = non-coherent data. This includes only the data flits (not the header).", "UMask": "0x8", "Unit": "QPI LL" }, @@ -418,7 +418,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of protocol flits received over QPI on the DRS (Da= ta Response) channel. DRS flits are used to transmit data with coherency. = This does not count data flits received over the NCB channel which transmi= ts non-coherent data. This includes only the header flits (not the data). = This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the total number of protocol flits received over QPI on the DRS (D= ata Response) channel. DRS flits are used to transmit data with coherency.= This does not count data flits received over the NCB channel which transm= its non-coherent data. This includes only the header flits (not the data).= This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -427,7 +427,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of flits received over QPI on the home channel.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the number of flits received over QPI on the home channel.", "UMask": "0x6", "Unit": "QPI LL" }, @@ -436,7 +436,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of non-request flits received over QPI on the home chann= el. These are most commonly snoop responses, and this event can be used as= a proxy for that.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the number of non-request flits received over QPI on the home chan= nel. These are most commonly snoop responses, and this event can be used a= s a proxy for that.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -445,7 +445,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of data request received over QPI on the home channel. = This basically counts the number of remote memory requests received over QP= I. In conjunction with the local read count in the Home Agent, one can cal= culate the number of LLC Misses.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the number of data request received over QPI on the home channel. = This basically counts the number of remote memory requests received over Q= PI. In conjunction with the local read count in the Home Agent, one can ca= lculate the number of LLC Misses.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -454,7 +454,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the number of snoop request flits received over QPI. These request= s are contained in the snoop channel. This does not include snoop response= s, which are received on the home channel.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for SNP, HOM, and DRS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the number of snoop request flits received over QPI. These reques= ts are contained in the snoop channel. This does not include snoop respons= es, which are received on the home channel.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -463,7 +463,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of Non-Coherent Bypass flits. These packets are generally used to = transmit non-coherent data across QPI.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Number of Non-Coherent Bypass flits. These packets are generally used to= transmit non-coherent data across QPI.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -472,7 +472,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of Non-Coherent Bypass data flits. These flits are generally used = to transmit non-coherent data across QPI. This does not include a count of= the DRS (coherent) data flits. This only counts the data flits, not the N= CB headers.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Number of Non-Coherent Bypass data flits. These flits are generally used= to transmit non-coherent data across QPI. This does not include a count o= f the DRS (coherent) data flits. This only counts the data flits, not the = NCB headers.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -481,7 +481,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of Non-Coherent Bypass non-data flits. These packets are generally= used to transmit non-coherent data across QPI, and the flits counted here = are for headers and other non-data flits. This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Number of Non-Coherent Bypass non-data flits. These packets are generall= y used to transmit non-coherent data across QPI, and the flits counted here= are for headers and other non-data flits. This includes extended headers.= ", "UMask": "0x8", "Unit": "QPI LL" }, @@ -490,7 +490,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Number of NCS (non-coherent standard) flits received over QPI. This inc= ludes extended headers.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Number of NCS (non-coherent standard) flits received over QPI. This in= cludes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -499,7 +499,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of flits received over the NDR (Non-Data Response)= channel. This channel is used to send a variety of protocol flits includi= ng grants and completions. This is only for NDR packets to the local socke= t which use the AK ring.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the total number of flits received over the NDR (Non-Data Response= ) channel. This channel is used to send a variety of protocol flits includ= ing grants and completions. This is only for NDR packets to the local sock= et which use the AK ring.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -508,7 +508,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transfering a 64B cacheline across = QPI, we will break it into 9 flits -- 1 with header information and 8 with = 64 bits of actual data and an additional 16 bits of other information. To = calculate data bandwidth, one should therefore do: data flits * 8B / time.;= Counts the total number of flits received over the NDR (Non-Data Response)= channel. This channel is used to send a variety of protocol flits includi= ng grants and completions. This is only for NDR packets destined for Route= -thru to a remote socket.", + "PublicDescription": "Counts the number of flits received from the= QPI Link. This is one of three groups that allow us to track flits. It i= ncludes filters for NDR, NCB, and NCS message classes. Each flit is made u= p of 80 bits of information (in addition to some ECC data). In full-width = (L0) mode, flits are made up of four fits, each of which contains 20 bits o= f data (along with some additional ECC data). In half-width (L0p) mode, t= he fits are only 10 bits, and therefore it takes twice as many fits to tran= smit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the t= ransfers here refer to fits. Therefore, in L0, the system will transfer 1 = flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth o= f the link by taking: flits*80b/time. Note that this is not the same as da= ta bandwidth. For example, when we are transferring a 64B cacheline across= QPI, we will break it into 9 flits -- 1 with header information and 8 with= 64 bits of actual data and an additional 16 bits of other information. To= calculate data bandwidth, one should therefore do: data flits * 8B / time.= ; Counts the total number of flits received over the NDR (Non-Data Response= ) channel. This channel is used to send a variety of protocol flits includ= ing grants and completions. This is only for NDR packets destined for Rout= e-thru to a remote socket.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -924,7 +924,7 @@ "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transfering a 64B= cacheline across QPI, we will break it into 9 flits -- 1 with header infor= mation and 8 with 64 bits of actual data and an additional 16 bits of other= information. To calculate data bandwidth, one should therefore do: data f= lits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flit= s transmitted over QPI. Each flit contains 64b of data. This includes bot= h DRS and NCB data flits (coherent and non-coherent). This can be used to = calculate the data bandwidth of the QPI link. One can get a good picture o= f the QPI-link characteristics by evaluating the protocol flits, data flits= , and idle/null flits. This does not include the header flits that go in d= ata packets.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data fli= ts transmitted over QPI. Each flit contains 64b of data. This includes bo= th DRS and NCB data flits (coherent and non-coherent). This can be used to= calculate the data bandwidth of the QPI link. One can get a good picture = of the QPI-link characteristics by evaluating the protocol flits, data flit= s, and idle/null flits. This does not include the header flits that go in = data packets.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -932,7 +932,7 @@ "BriefDescription": "Flits Transferred - Group 0; Non-Data protoco= l Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transfering a 64B= cacheline across QPI, we will break it into 9 flits -- 1 with header infor= mation and 8 with 64 bits of actual data and an additional 16 bits of other= information. To calculate data bandwidth, one should therefore do: data f= lits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL = non-data flits transmitted across QPI. This basically tracks the protocol = overhead on the QPI link. One can get a good picture of the QPI-link chara= cteristics by evaluating the protocol flits, data flits, and idle/null flit= s. This includes the header flits for data packets.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL= non-data flits transmitted across QPI. This basically tracks the protocol= overhead on the QPI link. One can get a good picture of the QPI-link char= acteristics by evaluating the protocol flits, data flits, and idle/null fli= ts. This includes the header flits for data packets.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -940,7 +940,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both = Header and Data)", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of flits transmitted over QPI on the DRS (Data= Response) channel. DRS flits are used to transmit data with coherency.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of flits transmitted over QPI on the DRS (Da= ta Response) channel. DRS flits are used to transmit data with coherency.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -948,7 +948,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of data flits transmitted over QPI on the DRS = (Data Response) channel. DRS flits are used to transmit data with coherenc= y. This does not count data flits transmitted over the NCB channel which t= ransmits non-coherent data. This includes only the data flits (not the hea= der).", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of data flits transmitted over QPI on the DR= S (Data Response) channel. DRS flits are used to transmit data with cohere= ncy. This does not count data flits transmitted over the NCB channel which= transmits non-coherent data. This includes only the data flits (not the h= eader).", "UMask": "0x8", "Unit": "QPI LL" }, @@ -956,7 +956,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits= ", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of protocol flits transmitted over QPI on the = DRS (Data Response) channel. DRS flits are used to transmit data with cohe= rency. This does not count data flits transmitted over the NCB channel whi= ch transmits non-coherent data. This includes only the header flits (not t= he data). This includes extended headers.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of protocol flits transmitted over QPI on th= e DRS (Data Response) channel. DRS flits are used to transmit data with co= herency. This does not count data flits transmitted over the NCB channel w= hich transmits non-coherent data. This includes only the header flits (not= the data). This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -964,7 +964,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of flits transmitted over QPI on the home channel.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of flits transmitted over QPI on the home channel.= ", "UMask": "0x6", "Unit": "QPI LL" }, @@ -972,7 +972,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request = Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of non-request flits transmitted over QPI on the hom= e channel. These are most commonly snoop responses, and this event can be = used as a proxy for that.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of non-request flits transmitted over QPI on the h= ome channel. These are most commonly snoop responses, and this event can b= e used as a proxy for that.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -980,7 +980,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Request Flit= s", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of data request transmitted over QPI on the home cha= nnel. This basically counts the number of remote memory requests transmitt= ed over QPI. In conjunction with the local read count in the Home Agent, o= ne can calculate the number of LLC Misses.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of data request transmitted over QPI on the home c= hannel. This basically counts the number of remote memory requests transmi= tted over QPI. In conjunction with the local read count in the Home Agent,= one can calculate the number of LLC Misses.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -988,7 +988,7 @@ "BriefDescription": "Flits Transferred - Group 1; SNP Flits", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the number of snoop request flits transmitted over QPI. These = requests are contained in the snoop channel. This does not include snoop r= esponses, which are transmitted on the home channel.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of snoop request flits transmitted over QPI. Thes= e requests are contained in the snoop channel. This does not include snoop= responses, which are transmitted on the home channel.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -997,7 +997,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of Non-Coherent Bypass flits. These packets are generally used= to transmit non-coherent data across QPI.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Number of Non-Coherent Bypass flits. These packets are generally us= ed to transmit non-coherent data across QPI.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -1006,7 +1006,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of Non-Coherent Bypass data flits. These flits are generally u= sed to transmit non-coherent data across QPI. This does not include a coun= t of the DRS (coherent) data flits. This only counts the data flits, not t= e NCB headers.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Number of Non-Coherent Bypass data flits. These flits are generally= used to transmit non-coherent data across QPI. This does not include a co= unt of the DRS (coherent) data flits. This only counts the data flits, not= the NCB headers.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -1015,7 +1015,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of Non-Coherent Bypass non-data flits. These packets are gener= ally used to transmit non-coherent data across QPI, and the flits counted h= ere are for headers and other non-data flits. This includes extended heade= rs.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Number of Non-Coherent Bypass non-data flits. These packets are gen= erally used to transmit non-coherent data across QPI, and the flits counted= here are for headers and other non-data flits. This includes extended hea= ders.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -1024,7 +1024,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Number of NCS (non-coherent standard) flits transmitted over QPI. T= his includes extended headers.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Number of NCS (non-coherent standard) flits transmitted over QPI. = This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -1033,7 +1033,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of flits transmitted over the NDR (Non-Data Re= sponse) channel. This channel is used to send a variety of protocol flits = including grants and completions. This is only for NDR packets to the loca= l socket which use the AK ring.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of flits transmitted over the NDR (Non-Data = Response) channel. This channel is used to send a variety of protocol flit= s including grants and completions. This is only for NDR packets to the lo= cal socket which use the AK ring.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -1042,7 +1042,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across= the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is ma= de up of 80 bits of information (in addition to some ECC data). In full-wi= dth (L0) mode, flits are made up of four fits, each of which contains 20 bi= ts of data (along with some additional ECC data). In half-width (L0p) mod= e, the fits are only 10 bits, and therefore it takes twice as many fits to = transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), t= he transfers here refer to fits. Therefore, in L0, the system will transfe= r 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwid= th of the link by taking: flits*80b/time. Note that this is not the same a= s data bandwidth. For example, when we are transfering a 64B cacheline acr= oss QPI, we will break it into 9 flits -- 1 with header information and 8 w= ith 64 bits of actual data and an additional 16 bits of other information. = To calculate data bandwidth, one should therefore do: data flits * 8B / ti= me.; Counts the total number of flits transmitted over the NDR (Non-Data Re= sponse) channel. This channel is used to send a variety of protocol flits = including grants and completions. This is only for NDR packets destined fo= r Route-thru to a remote socket.", + "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for NDR, NCB, and NCS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of flits transmitted over the NDR (Non-Data = Response) channel. This channel is used to send a variety of protocol flit= s including grants and completions. This is only for NDR packets destined = for Route-thru to a remote socket.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -1157,7 +1157,7 @@ "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO fro Snoop messages on AD.", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -1166,7 +1166,7 @@ "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO fro Snoop messages on AD.", + "PublicDescription": "Occupancy event that tracks the number of li= nk layer credits into the R3 (for transactions across the BGF) available in= each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x2", "Unit": "QPI LL" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json index 34dfc3cf22ef..b5a33e7a68c6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json @@ -51,7 +51,6 @@ "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", - "PublicDescription": "UNC_M_BYP_CMDS.ACT", "UMask": "0x1", "Unit": "iMC" }, @@ -60,7 +59,6 @@ "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", - "PublicDescription": "UNC_M_BYP_CMDS.CAS", "UMask": "0x2", "Unit": "iMC" }, @@ -69,7 +67,6 @@ "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", - "PublicDescription": "UNC_M_BYP_CMDS.PRE", "UMask": "0x4", "Unit": "iMC" }, @@ -202,7 +199,7 @@ "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit erros in lockstep mode.", + "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { @@ -492,7 +489,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.HIGH", "UMask": "0x4", "Unit": "iMC" }, @@ -501,7 +497,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.LOW", "UMask": "0x1", "Unit": "iMC" }, @@ -510,7 +505,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.MED", "UMask": "0x2", "Unit": "iMC" }, @@ -519,7 +513,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.PANIC", "UMask": "0x8", "Unit": "iMC" }, @@ -528,7 +521,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -537,7 +530,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -545,7 +538,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -554,7 +547,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -563,7 +556,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -572,7 +565,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -581,7 +574,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -590,7 +583,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -599,7 +592,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -608,7 +601,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -617,7 +610,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -626,7 +619,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -635,7 +628,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -644,7 +637,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -653,7 +646,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -662,7 +655,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -671,7 +664,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -680,7 +673,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -689,7 +682,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -698,7 +691,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -707,7 +700,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -716,7 +709,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -725,7 +718,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -733,7 +726,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -742,7 +735,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -751,7 +744,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -760,7 +753,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -769,7 +762,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -778,7 +771,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -787,7 +780,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -796,7 +789,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -805,7 +798,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -814,7 +807,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -823,7 +816,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -832,7 +825,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -841,7 +834,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -850,7 +843,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -859,7 +852,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -868,7 +861,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -877,7 +870,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -886,7 +879,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -895,7 +888,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -904,7 +897,7 @@ "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK2.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -912,7 +905,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -921,7 +914,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -929,7 +922,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -938,7 +931,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -947,7 +940,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -956,7 +949,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -965,7 +958,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -974,7 +967,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -983,7 +976,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -992,7 +985,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1001,7 +994,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1010,7 +1003,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1019,7 +1012,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1028,7 +1021,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1037,7 +1030,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1046,7 +1039,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1055,7 +1048,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1064,7 +1057,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1073,7 +1066,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1082,7 +1075,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1091,7 +1084,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1100,7 +1093,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1109,7 +1102,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1117,7 +1110,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1126,7 +1119,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1135,7 +1128,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1144,7 +1137,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1153,7 +1146,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1162,7 +1155,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1171,7 +1164,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1180,7 +1173,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1189,7 +1182,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1198,7 +1191,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1207,7 +1200,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1216,7 +1209,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1225,7 +1218,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1234,7 +1227,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1243,7 +1236,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1252,7 +1245,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1261,7 +1254,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1270,7 +1263,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1279,7 +1272,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1288,7 +1281,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1297,7 +1290,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1305,7 +1298,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1314,7 +1307,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1323,7 +1316,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1332,7 +1325,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1341,7 +1334,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1350,7 +1343,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1359,7 +1352,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1368,7 +1361,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1377,7 +1370,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1386,7 +1379,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1395,7 +1388,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1404,7 +1397,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1413,7 +1406,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1422,7 +1415,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1431,7 +1424,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1440,7 +1433,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1449,7 +1442,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1458,7 +1451,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1467,7 +1460,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1476,7 +1469,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1485,7 +1478,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1493,7 +1486,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1502,7 +1495,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1511,7 +1504,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1520,7 +1513,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1529,7 +1522,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1538,7 +1531,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1547,7 +1540,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1556,7 +1549,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1565,7 +1558,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1574,7 +1567,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1583,7 +1576,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1592,7 +1585,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1601,7 +1594,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1610,7 +1603,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1619,7 +1612,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1628,7 +1621,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1637,7 +1630,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1646,7 +1639,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1655,7 +1648,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1680,7 +1673,6 @@ "EventCode": "0x91", "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "Unit": "iMC" }, { @@ -1688,7 +1680,6 @@ "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.RMM", "PerPkg": "1", - "PublicDescription": "UNC_M_VMSE_WR_PUSH.RMM", "UMask": "0x2", "Unit": "iMC" }, @@ -1697,7 +1688,6 @@ "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.WMM", "PerPkg": "1", - "PublicDescription": "UNC_M_VMSE_WR_PUSH.WMM", "UMask": "0x1", "Unit": "iMC" }, @@ -1706,7 +1696,6 @@ "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", "PerPkg": "1", - "PublicDescription": "UNC_M_WMM_TO_RMM.LOW_THRESH", "UMask": "0x1", "Unit": "iMC" }, @@ -1715,7 +1704,6 @@ "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", "PerPkg": "1", - "PublicDescription": "UNC_M_WMM_TO_RMM.STARVE", "UMask": "0x2", "Unit": "iMC" }, @@ -1724,7 +1712,6 @@ "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "PerPkg": "1", - "PublicDescription": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "UMask": "0x4", "Unit": "iMC" }, @@ -1765,7 +1752,6 @@ "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", "PerPkg": "1", - "PublicDescription": "UNC_M_WRONG_MM", "Unit": "iMC" }, { @@ -1773,7 +1759,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1782,7 +1768,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1790,7 +1776,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1799,7 +1785,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1808,7 +1794,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1817,7 +1803,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1826,7 +1812,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1835,7 +1821,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1844,7 +1830,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1853,7 +1839,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1862,7 +1848,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1871,7 +1857,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1880,7 +1866,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1889,7 +1875,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1898,7 +1884,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1907,7 +1893,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1916,7 +1902,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1925,7 +1911,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1934,7 +1920,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1943,7 +1929,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1952,7 +1938,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1961,7 +1947,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1970,7 +1956,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1978,7 +1964,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1987,7 +1973,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1996,7 +1982,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2005,7 +1991,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2014,7 +2000,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2023,7 +2009,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2032,7 +2018,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2041,7 +2027,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2050,7 +2036,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2059,7 +2045,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2068,7 +2054,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2077,7 +2063,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2086,7 +2072,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2095,7 +2081,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2104,7 +2090,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2113,7 +2099,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2122,7 +2108,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2131,7 +2117,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2140,7 +2126,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2149,7 +2135,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2158,7 +2144,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2166,7 +2152,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2175,7 +2161,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2184,7 +2170,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2193,7 +2179,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2202,7 +2188,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2211,7 +2197,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2220,7 +2206,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2229,7 +2215,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2238,7 +2224,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2247,7 +2233,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2256,7 +2242,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2265,7 +2251,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2274,7 +2260,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2283,7 +2269,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2292,7 +2278,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2301,7 +2287,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2310,7 +2296,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2319,7 +2305,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2328,7 +2314,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2337,7 +2323,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2346,7 +2332,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2354,7 +2340,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2363,7 +2349,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2372,7 +2358,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2381,7 +2367,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2390,7 +2376,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2399,7 +2385,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2408,7 +2394,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2417,7 +2403,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2426,7 +2412,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2435,7 +2421,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2444,7 +2430,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2453,7 +2439,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2462,7 +2448,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2471,7 +2457,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2480,7 +2466,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2489,7 +2475,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2498,7 +2484,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2507,7 +2493,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2516,7 +2502,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2525,7 +2511,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2534,7 +2520,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2542,7 +2528,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2551,7 +2537,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2560,7 +2546,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2569,7 +2555,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2578,7 +2564,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2587,7 +2573,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2596,7 +2582,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2605,7 +2591,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2614,7 +2600,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2623,7 +2609,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2632,7 +2618,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2641,7 +2627,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2650,7 +2636,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2659,7 +2645,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2668,7 +2654,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2677,7 +2663,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2686,7 +2672,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2695,7 +2681,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2704,7 +2690,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2713,7 +2699,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2722,7 +2708,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2730,7 +2716,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2739,7 +2725,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2748,7 +2734,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2757,7 +2743,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2766,7 +2752,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2775,7 +2761,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2784,7 +2770,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2793,7 +2779,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2802,7 +2788,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2811,7 +2797,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2820,7 +2806,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2829,7 +2815,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2838,7 +2824,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2847,7 +2833,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2856,7 +2842,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2865,7 +2851,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Bank= s 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2874,7 +2860,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Bank= s 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2883,7 +2869,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Bank= s 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2892,7 +2878,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Bank= s 12-15)", "UMask": "0x14", "Unit": "iMC" } diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json b/= tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json index a80d931dc3d5..43def2582617 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json @@ -101,7 +101,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of A= tomic Transactions as Secondary", "UMask": "0x10", "Unit": "IRP" }, @@ -110,7 +110,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.2ND_RD_INSERT", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of R= ead Transactions as Secondary", "UMask": "0x4", "Unit": "IRP" }, @@ -119,7 +119,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.2ND_WR_INSERT", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of W= rite Transactions as Secondary", "UMask": "0x8", "Unit": "IRP" }, @@ -128,7 +128,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.FAST_REJ", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", "UMask": "0x2", "Unit": "IRP" }, @@ -137,7 +137,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.FAST_REQ", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", "UMask": "0x1", "Unit": "IRP" }, @@ -146,7 +146,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.FAST_XFER", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers= From Primary to Secondary", "UMask": "0x20", "Unit": "IRP" }, @@ -155,7 +155,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.PF_ACK_HINT", + "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints= From Primary to Secondary", "UMask": "0x40", "Unit": "IRP" }, @@ -182,7 +182,7 @@ "EventCode": "0x15", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC1.LOST_FWD", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop p= ulled away ownership before a write was committed", "UMask": "0x10", "Unit": "IRP" }, @@ -325,7 +325,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.HIT_ES", + "PublicDescription": "Snoop Responses : Hit E or S", "UMask": "0x4", "Unit": "IRP" }, @@ -334,7 +334,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.HIT_I", + "PublicDescription": "Snoop Responses : Hit I", "UMask": "0x2", "Unit": "IRP" }, @@ -343,7 +343,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.HIT_M", + "PublicDescription": "Snoop Responses : Hit M", "UMask": "0x8", "Unit": "IRP" }, @@ -352,7 +352,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.MISS", + "PublicDescription": "Snoop Responses : Miss", "UMask": "0x1", "Unit": "IRP" }, @@ -361,7 +361,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.SNPCODE", + "PublicDescription": "Snoop Responses : SnpCode", "UMask": "0x10", "Unit": "IRP" }, @@ -370,7 +370,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.SNPDATA", + "PublicDescription": "Snoop Responses : SnpData", "UMask": "0x20", "Unit": "IRP" }, @@ -379,7 +379,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.SNPINV", + "PublicDescription": "Snoop Responses : SnpInv", "UMask": "0x40", "Unit": "IRP" }, @@ -474,7 +474,7 @@ "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outboun= d requests from the IRP to the switch (towards the devices). This can be u= sed in conjuection with the allocations event in order to calculate average= latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbou= nd requests from the IRP to the switch (towards the devices). This can be = used in conjunction with the allocations event in order to calculate averag= e latency of outbound requests.", "Unit": "IRP" }, { @@ -1223,7 +1223,6 @@ "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", "PerPkg": "1", - "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.HUB", "UMask": "0x2", "Unit": "R3QPI" }, @@ -1232,7 +1231,6 @@ "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", "PerPkg": "1", - "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.SAT", "UMask": "0x1", "Unit": "R3QPI" }, @@ -2312,7 +2310,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transfered). Therefore, this event will increment by the number o= f credits acquired in each cycle. Filtering based on message class is not = provided. One can count the number of packets transfered in a given messag= e class using an qfclk event.; Filter for the Home (HOM) message class. HO= M is generally used to send requests, request responses, and snoop response= s.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credits from the VN0 pool. = Note that a single packet may require multiple flit buffers (i.e. when data= is being transferred). Therefore, this event will increment by the number= of credits acquired in each cycle. Filtering based on message class is no= t provided. One can count the number of packets transferred in a given mes= sage class using an qfclk event.; Filter for the Home (HOM) message class. = HOM is generally used to send requests, request responses, and snoop respo= nses.", "UMask": "0x1", "Unit": "R3QPI" }, @@ -2321,7 +2319,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transfered). Therefore, this event will increment by the number o= f credits acquired in each cycle. Filtering based on message class is not = provided. One can count the number of packets transfered in a given messag= e class using an qfclk event.; Filter for the Home (HOM) message class. HO= M is generally used to send requests, request responses, and snoop response= s.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credits from the VN0 pool. = Note that a single packet may require multiple flit buffers (i.e. when data= is being transferred). Therefore, this event will increment by the number= of credits acquired in each cycle. Filtering based on message class is no= t provided. One can count the number of packets transferred in a given mes= sage class using an qfclk event.; Filter for the Home (HOM) message class. = HOM is generally used to send requests, request responses, and snoop respo= nses.", "UMask": "0x4", "Unit": "R3QPI" }, @@ -2384,14 +2382,12 @@ "EventCode": "0xA", "EventName": "UNC_S_BOUNCE_CONTROL", "PerPkg": "1", - "PublicDescription": "UNC_S_BOUNCE_CONTROL", "Unit": "SBO" }, { "BriefDescription": "Uncore Clocks", "EventName": "UNC_S_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "UNC_S_CLOCKTICKS", "Unit": "SBO" }, { @@ -2596,7 +2592,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.AD_CACHE", "UMask": "0x1", "Unit": "SBO" }, @@ -2605,7 +2600,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AK_CORE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.AK_CORE", "UMask": "0x2", "Unit": "SBO" }, @@ -2614,7 +2608,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.BL_CORE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.BL_CORE", "UMask": "0x4", "Unit": "SBO" }, @@ -2623,7 +2616,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.IV_CORE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.IV_CORE", "UMask": "0x8", "Unit": "SBO" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json b/= tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json index e682eedf644a..83d20130c217 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json @@ -395,7 +395,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "Unit": "PCU" }, { @@ -403,7 +403,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "Unit": "PCU" }, { @@ -411,7 +411,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with threshholding to gene= rate histograms, or with other PCU events and occupancy triggering to captu= re other details.", + "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "Unit": "PCU" }, { @@ -427,7 +427,7 @@ "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that we are in I= nteral PROCHOT mode. This mode is triggered when a sensor on the die deter= mines that we are too hot and must throttle to avoid damaging the chip.", + "PublicDescription": "Counts the number of cycles that we are in I= nternal PROCHOT mode. This mode is triggered when a sensor on the die dete= rmines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { @@ -451,7 +451,7 @@ "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", - "PublicDescription": "UNC_P_VR_HOT_CYCLES", + "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 4fa827c7f719..dfed265c95ab 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -4,7 +4,7 @@ GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v27,broadwell,core GenuineIntel-6-56,v9,broadwellde,core -GenuineIntel-6-4F,v19,broadwellx,core +GenuineIntel-6-4F,v20,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98DBFC74A5B for ; Thu, 23 Mar 2023 19:21:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231620AbjCWTVr (ORCPT ); Thu, 23 Mar 2023 15:21:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbjCWTV3 (ORCPT ); Thu, 23 Mar 2023 15:21:29 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FD671024E for ; Thu, 23 Mar 2023 12:21:12 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-54352648c1eso227427717b3.9 for ; Thu, 23 Mar 2023 12:21:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599271; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=rVcqhyYrDTRhmMXr68BgAEpfijkgy4ZxPrTLjnvUojY=; b=XFOhAfS9VOOJ/P1Hmyz1Q9lOX5xIy57eEfr8i+67ELdkZaIh/2T8tftEVxeqQO1jP+ Nc4RLtFkMDym0w1BJdSmTr9/MukfuUDiMnbxU+4XtDVvK39a4mKE5q3bBh2qrQWb5+B7 4YzBpLRUSAa6q9J5p+GC6HxJ10szy4/y5DcBJOJ6LnoEEB+gkGIAVKtnOtpPyDwlPtFk 1I/sYoidgAlkk5iVL2J2NRrzSREB7aMwsIAH5GqA8RFdu32O9e3Ql3xo8CZzNg2+mSek q49YtHt2qp1jP9pIMdWwKKRYuS2wjWgBkRw/KZTzPVqC9zLuOhrDE/b/ITKkQ22REjSw /gmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599271; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rVcqhyYrDTRhmMXr68BgAEpfijkgy4ZxPrTLjnvUojY=; b=CBuLbcUiRvYEtUSFiH874rHce5Hr3vvyz3o4IrCZr7xrVASemfsJLWNG770BMyAKBj rCAo38WQjPcXvOoJy+hUvtpKND49JuqKZB8w36tHIyK9AC2nCXZheyLthkLomA7sFi3o ZfhGvgnrl+uMT/xNtxNEUSdVyojgSZFo1vbXNgXUozefL4THOsKgZWkA/vnCM9k0xtzX xie5wWVbTMKdx+NAWvYsd+/JnzTDHhFzy7txxmysiN/Ce5+8sygN8qz2xR3FbjLdOOAD AbOKKtIeSPzbsbbNcaWhE+9CvftlG+PkJdK56w8BDTmoQsR7NtedH3x3md4M2/RSfM8g +spw== X-Gm-Message-State: AAQBX9e44hHfB3D9a2DmF6Yr+WTXzcP16jT640k80zcUlq2vsQBhTbf6 aLql83/+4bGkdUcg/fuCrg2zpxHnCq/t X-Google-Smtp-Source: AKy350aeXPQzzGJfov0xmHXf/Y5BBHa1U7E2qa6Lo55RT6fWG6uJJtyUFxau35DdmjW9K2pauBDg0TdakFqs X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a05:6902:1008:b0:b1d:5061:98e3 with SMTP id w8-20020a056902100800b00b1d506198e3mr2923171ybt.6.1679599271741; Thu, 23 Mar 2023 12:21:11 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:23 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-5-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 4/9] perf vendor events: Haswell v33 events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/haswell/cache.json | 38 +++++++++---------- .../pmu-events/arch/x86/haswell/memory.json | 38 +++++++++---------- .../pmu-events/arch/x86/haswell/pipeline.json | 8 ++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 47 insertions(+), 39 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf= /pmu-events/arch/x86/haswell/cache.json index 5a1489e79859..0831f14b3cc6 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -643,7 +643,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch code readshit in= the L3 and the snoops to sibling cores hit in either E/S state and the lin= e is not forwarded", + "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -652,7 +652,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readshit in= the L3 and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -661,7 +661,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readshit in= the L3 and the snoops to sibling cores hit in either E/S state and the lin= e is not forwarded", + "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -688,7 +688,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all requestshit in the L3", + "BriefDescription": "Counts all requests hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -697,7 +697,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOshit in the L= 3 and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -706,7 +706,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOshit in the L= 3 and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -715,7 +715,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readshit in the L3 and= the snoop to one of the sibling cores hits the line in M state and the lin= e is forwarded", + "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -724,7 +724,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readshit in the L3 and= the snoops to sibling cores hit in either E/S state and the line is not fo= rwarded", + "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -733,7 +733,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readshit in the L3 and the= snoop to one of the sibling cores hits the line in M state and the line is= forwarded", + "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -742,7 +742,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readshit in the L3 and the= snoops to sibling cores hit in either E/S state and the line is not forwar= ded", + "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -751,7 +751,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)hit in th= e L3 and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -760,7 +760,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)hit in th= e L3 and the snoops to sibling cores hit in either E/S state and the line i= s not forwarded", + "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -769,7 +769,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code readshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -778,7 +778,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to L2) data = readshit in the L3", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -787,7 +787,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -796,7 +796,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code readshit in the L3", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -805,7 +805,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data readshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -814,7 +814,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/per= f/pmu-events/arch/x86/haswell/memory.json index 9fb63e1dab08..2fc25e22a42a 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json @@ -179,7 +179,7 @@ "UMask": "0x2" }, { - "BriefDescription": "Counts all demand & prefetch code readsmiss i= n the L3", + "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -188,7 +188,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch code readsmiss t= he L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -197,7 +197,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readsmiss i= n the L3", + "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -206,7 +206,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readsmiss t= he L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -233,7 +233,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all requestsmiss in the L3", + "BriefDescription": "Counts all requests miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -242,7 +242,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOsmiss in the = L3", + "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -251,7 +251,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOsmiss the L3 = and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -260,7 +260,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readsmiss in the L3", + "BriefDescription": "Counts all demand code reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -269,7 +269,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readsmiss the L3 and t= he data is returned from local dram", + "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -278,7 +278,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readsmiss in the L3", + "BriefDescription": "Counts demand data reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -287,7 +287,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readsmiss the L3 and the d= ata is returned from local dram", + "BriefDescription": "Counts demand data reads miss the L3 and the = data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -296,7 +296,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)miss in t= he L3", + "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -305,7 +305,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)miss the = L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -314,7 +314,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code readsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -323,7 +323,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to L2) data = readsmiss in the L3", + "BriefDescription": "Counts prefetch (that bring data to L2) data = reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -332,7 +332,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -341,7 +341,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to LLC only)= code readsmiss in the L3", + "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -350,7 +350,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data readsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -359,7 +359,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/p= erf/pmu-events/arch/x86/haswell/pipeline.json index 9ac36c1c24b6..540f4372623c 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -194,6 +194,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index dfed265c95ab..927e60f3417d 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -10,7 +10,7 @@ GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-A[DE],v1.01,graniterapids,core -GenuineIntel-6-(3C|45|46),v32,haswell,core +GenuineIntel-6-(3C|45|46),v33,haswell,core GenuineIntel-6-3F,v26,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.19,icelakex,core --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B91BC76196 for ; Thu, 23 Mar 2023 19:22:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231150AbjCWTWA (ORCPT ); Thu, 23 Mar 2023 15:22:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231490AbjCWTVg (ORCPT ); Thu, 23 Mar 2023 15:21:36 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CABB12CDE for ; Thu, 23 Mar 2023 12:21:20 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id j11-20020a25230b000000b00b6871c296bdso16182344ybj.5 for ; Thu, 23 Mar 2023 12:21:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599279; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=Uih42a7geLUhVXca3hZ+/zz/xw+NyUuKTbPaxBF4q7k=; b=Ynh6jCGoKZT+li3+u1mwZXjGs3n91CPqS38oeRIQG+blW16kmzIMtWjqNP8iZvtDL8 PZfz2rKxnO4ihjzGmiLR/VQnItZ8FD+vbfKepA3NpSkOG9f5xCdiepLsTIi+JpwJ2PoH oQRDLvCiHq/F0YNRcJcX57GKs8kK0Tl8uI7elCnV2scPglreyj7N5eSWdfmdfbHeLvsj tK0Qy33mmngCDRcJ0lNX9fiFGY9sOK6+X19yTMk9m59G3pDL/EBQVlYm9QbGYgPnqX3a lg1F3c9xBAVoGTBW30Z42xtQcZ+mVvdn6JH5yA05+uSYhyPEBBnd+J0QPN5z9h8oohD+ HHrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599279; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Uih42a7geLUhVXca3hZ+/zz/xw+NyUuKTbPaxBF4q7k=; b=aNXmv59MNET0i99oI50dVrWNoktdwF2H2i8ATm6dR2agDKT4E+ccJ6FHxdpgHM+Y4o rmVagyYfc74pWDHGo9qPWjFAMkNH0s4v0CXbtz7rPp0sHkF4XzelBi8rsDo5K0hVsjGr an0vXkLXFFkmEbqP0472z5aW1fCz3Ta1oLCZqcOgw1FXNw8UZts6sPLSgLrDTTFcMb7l ZYz7rbmM8y/CTQRG9xTZOndBWQ7zC+QIybZBCMUSQh/E873n833HlYrU7P1Gqm4XaZeU 7tpArsu1ewd+e0YdcUljsufSQWYEY5nKz7U7tNfmnPWic0p4rjvUI/Azuqzh7r6AiJ0+ D+oQ== X-Gm-Message-State: AAQBX9d94nvh4Z3AwO2e8OtrOnKGN6Y4wwCTfmFHCv2HIR4b0pJ0J/Xf coreho72d1z2fSEO6qSk+prX7PPogKnj X-Google-Smtp-Source: AKy350YggGaNwlCiD44A9fbZNxJ9fiMPPjkEibtO9jlaqdKe41qSgM6COfug3Ijk1CVuzPPiqZRrxlXOyJRa X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a81:af02:0:b0:544:8bc1:a179 with SMTP id n2-20020a81af02000000b005448bc1a179mr2383526ywh.4.1679599279347; Thu, 23 Mar 2023 12:21:19 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:24 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-6-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 5/9] perf vendor events: Haswellx v27 events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Signed-off-by: Ian Rogers --- .../perf/pmu-events/arch/x86/haswellx/cache.json | 2 +- .../pmu-events/arch/x86/haswellx/pipeline.json | 8 ++++++++ .../arch/x86/haswellx/uncore-cache.json | 16 ++++++++-------- .../arch/x86/haswellx/uncore-other.json | 6 +++--- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 5 files changed, 21 insertions(+), 13 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/per= f/pmu-events/arch/x86/haswellx/cache.json index 1836ed62694e..a6c81010b394 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/= perf/pmu-events/arch/x86/haswellx/pipeline.json index 9ac36c1c24b6..540f4372623c 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json @@ -194,6 +194,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/to= ols/perf/pmu-events/arch/x86/haswellx/uncore-cache.json index 183bcac99642..e969dc71bea1 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json @@ -3114,7 +3114,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE R= equests", + "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE = Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -3123,7 +3123,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE = Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE= Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -3132,7 +3132,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requ= ests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Read Req= uests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -3141,7 +3141,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Req= uests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Re= quests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -3150,7 +3150,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Write Req= uests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Write Re= quests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -3159,7 +3159,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Re= quests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Write R= equests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -3168,7 +3168,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Local Requ= ests", + "BriefDescription": "Data Pending Occupancy Accumulator; Local Req= uests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -3177,7 +3177,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Remote Req= uests", + "BriefDescription": "Data Pending Occupancy Accumulator; Remote Re= quests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json b/to= ols/perf/pmu-events/arch/x86/haswellx/uncore-other.json index 4c3e2a794117..d30e3b16c1af 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json @@ -474,7 +474,7 @@ "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outboun= d requests from the IRP to the switch (towards the devices). This can be u= sed in conjuection with the allocations event in order to calculate average= latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbou= nd requests from the IRP to the switch (towards the devices). This can be = used in conjunction with the allocations event in order to calculate averag= e latency of outbound requests.", "Unit": "IRP" }, { @@ -2256,7 +2256,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transferred). Therefore, this event will increment by the number = of credits acquired in each cycle. Filtering based on message class is not= provided. One can count the number of packets transferred in a given mess= age class using an qfclk event.; Filter for the Home (HOM) message class. = HOM is generally used to send requests, request responses, and snoop respon= ses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credits from the VN0 pool. = Note that a single packet may require multiple flit buffers (i.e. when data= is being transferred). Therefore, this event will increment by the number= of credits acquired in each cycle. Filtering based on message class is no= t provided. One can count the number of packets transferred in a given mes= sage class using an qfclk event.; Filter for the Home (HOM) message class. = HOM is generally used to send requests, request responses, and snoop respo= nses.", "UMask": "0x1", "Unit": "R3QPI" }, @@ -2265,7 +2265,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credts from the VN0 pool. N= ote that a single packet may require multiple flit buffers (i.e. when data = is being transferred). Therefore, this event will increment by the number = of credits acquired in each cycle. Filtering based on message class is not= provided. One can count the number of packets transferred in a given mess= age class using an qfclk event.; Filter for the Home (HOM) message class. = HOM is generally used to send requests, request responses, and snoop respon= ses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This= event can be used in conjunction with the VNA In-Use Accumulator to calcul= ate the average lifetime of a credit holder. VNA credits are used by all m= essage classes in order to communicate across QPI. If a packet is unable t= o acquire credits, it will then attempt to use credits from the VN0 pool. = Note that a single packet may require multiple flit buffers (i.e. when data= is being transferred). Therefore, this event will increment by the number= of credits acquired in each cycle. Filtering based on message class is no= t provided. One can count the number of packets transferred in a given mes= sage class using an qfclk event.; Filter for the Home (HOM) message class. = HOM is generally used to send requests, request responses, and snoop respo= nses.", "UMask": "0x4", "Unit": "R3QPI" }, diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 927e60f3417d..e1a609401fff 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -11,7 +11,7 @@ GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-A[DE],v1.01,graniterapids,core GenuineIntel-6-(3C|45|46),v33,haswell,core -GenuineIntel-6-3F,v26,haswellx,core +GenuineIntel-6-3F,v27,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.19,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 127F9C6FD1C for ; Thu, 23 Mar 2023 19:22:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231777AbjCWTWP (ORCPT ); Thu, 23 Mar 2023 15:22:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231540AbjCWTVq (ORCPT ); Thu, 23 Mar 2023 15:21:46 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0FC6ACDC9 for ; Thu, 23 Mar 2023 12:21:28 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 205-20020a2503d6000000b00b7411408308so4189948ybd.1 for ; Thu, 23 Mar 2023 12:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599287; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=ICoBRC5p7C47vzNPhCu4TQTxzhqKflbzynhlXLr/MKk=; b=NTv4v6z3Ry7/x16aUR6VsSc2k8sA9zVbyAhVQTlCenK4TKyrTtLzcVCpKnXXpMYMvz mnCi5FW6Ux9aGdiAkPcCiBPO4+hnZ4FncMdfsiCKN/qpAFzVrkRDXdsL2DgYYoOvBTJ+ 5d+Yacn36i26RyuFzNCVISlOJXf4MCzBjg/H95LHGb5HfwiQplhxgCzA+3YAKjzwTVcC KxdILpoPITXk1FkOALG7PUQAKKiH8bCcArW2Et3dbd/CtwpnZrnPDgURtyQng8zxIHWp ktEMzP1HbudPxSO69jZzUQC+v2yrGNGQsS2uBYTaXmsD6t/brrNCuwsbHF3SBl9CwKMm 0izw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599287; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ICoBRC5p7C47vzNPhCu4TQTxzhqKflbzynhlXLr/MKk=; b=SHTXGkGORKL/LsoqNhLlLv0zcYR+kbJmojxB76BrzGduzOpDKvquu8dBt61nFGWCps lIUAPVSKNrGYIcjRtRBcVuSfoRILnDa5qSW0Hj4MGBsjZEEIj6K3pmYaToWp0WfntL04 1zl/PDdXwnjOJhMOWCX/gh/XFJ673hGnZpU4qBeWGtFG1MklEXkFpDpimN8j4NGNDQEj nDd1LXIuyheJM5aQBSIuhS4QcTRvZrPDuuysnKhKJsEyNRjufY9NASdk1FvpFy9d2ayi F79bTqc3Dx8zQvvUGESSL8ojH5W9okQGZBR8+hG1SQorwNzAGD73OTn1iH9+ZFfWszwR pE9g== X-Gm-Message-State: AAQBX9fVLq7fLSUOCcGQMXQPtkQDXjlDywZ70++14VM/KBlAL+rnORxK mPN2Mn7ZZzZApFNZdiceaMgoqUaia+O5 X-Google-Smtp-Source: AKy350aykOl/2HKkfyrVxLlykwiNwGTV+2qSc99jTYQOFCt6cgGio9japBskZHWTdyIz90vOL8VmY1WwhukS X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a05:6902:70a:b0:b21:5fb4:c6e6 with SMTP id k10-20020a056902070a00b00b215fb4c6e6mr2790224ybt.11.1679599287786; Thu, 23 Mar 2023 12:21:27 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:25 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-7-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 6/9] perf vendor events: Jaketown v23 events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds BR_MISP_EXEC.INDIRECT event. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/jaketown/pipeline.json | 8 ++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/= perf/pmu-events/arch/x86/jaketown/pipeline.json index 85c04fe7632a..d0edfdec9f01 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -202,6 +202,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index e1a609401fff..e41c289fa427 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -16,7 +16,7 @@ GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.19,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core -GenuineIntel-6-2D,v22,jaketown,core +GenuineIntel-6-2D,v23,jaketown,core GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.01,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A338C74A5B for ; Thu, 23 Mar 2023 19:22:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230329AbjCWTWX (ORCPT ); Thu, 23 Mar 2023 15:22:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231614AbjCWTVr (ORCPT ); Thu, 23 Mar 2023 15:21:47 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CF7F1E2A9 for ; Thu, 23 Mar 2023 12:21:35 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5417f156cb9so230466057b3.8 for ; Thu, 23 Mar 2023 12:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599294; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=+twZgD2lANnEj4Ejgw/Tmpo0NzizDYZveDuYYTFvBkQ=; b=DOLfyLdfXIIJboU8zkl6Uhv2DoOuJI7tOmholFicsh5wHtqPfHBoa4d/ksaQZ4UpZX 0Ev8jrFOmVtp7YhsQdV9BHyssb4h1LrsqfMVJDUD8lg9Oo+8pCZssHgEnNAjDxZhZ0wP 555bUqffvW2GDA+AXwxnpF/XJAB9zHUGgOTS9L9GKnqu8ZQhl1/hXf5lzv6TiXYKcs5v qLOwjbPkhgcSb+9G5g3Sn6KV53JpIz/EnMJp5CUmlYfmgXbjtzGrK8IzLmmG158kQxjk VWfqj+7HlJ9BIg0Jkp6HeprNltgm7EOSmmVdDc9NL08qGBUNIIB3zEqVuPrXsSRWYqbG FKgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599294; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+twZgD2lANnEj4Ejgw/Tmpo0NzizDYZveDuYYTFvBkQ=; b=UN2dVGnzBo31qwVdzxIzg0rLlRWHBHesdh/OeFgpE85f7J5JeGqLbUk23jrCYCAt48 zFRfa62GuCpnTcv01CfwPjT/pdEh9kJTKYmLIU12n13Myg9to/dp+OLQcwXEClBMSWZk Vq8S3Lf2vTUcT58NomTF38JZKoaPMRVxZTGu53xcKNwFA0U6d1KUcua0F8UlyQPIAF/i PMBei115LXm+JG+nhumaCjbS1AUR+pucKcvlP1eVLtXeScVn/08GgP12UrFx3tMWSnad gDDBZxSp+wGMxby+CNU7ihGrf3VnackED+kNewVVfnMWAO+OhTQsi4UVowp6+o0Mmcxz EDZQ== X-Gm-Message-State: AAQBX9e8ydgUaLWQHN+oeCNrz/z5iI60REZwctlXA5YuHzMbJjseOwhM nnYnCEEgwv42topiTU4V979/vUWKGCrB X-Google-Smtp-Source: AKy350YAsxyhvHlQHOGw0WgC47yvbSzbSDYgNoOHhjZ7NRm+hmzKEIv3YnQvdG7T6KSoQ5hl/QSBOAY1lj93 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a25:f407:0:b0:b6d:1483:bc18 with SMTP id q7-20020a25f407000000b00b6d1483bc18mr2938380ybd.7.1679599294516; Thu, 23 Mar 2023 12:21:34 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:26 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-8-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 7/9] perf vendor events: Sandybridge v19 events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds BR_MISP_EXEC.INDIRECT event. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index e41c289fa427..41d755d570e6 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -21,7 +21,7 @@ GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.01,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core -GenuineIntel-6-2A,v18,sandybridge,core +GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/too= ls/perf/pmu-events/arch/x86/sandybridge/pipeline.json index 54454e5e262c..ecaf94ccc9c7 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -210,6 +210,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", "EventCode": "0x89", --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75950C74A5B for ; Thu, 23 Mar 2023 19:22:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231494AbjCWTWc (ORCPT ); Thu, 23 Mar 2023 15:22:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231707AbjCWTVw (ORCPT ); Thu, 23 Mar 2023 15:21:52 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D0EB1EBF6 for ; Thu, 23 Mar 2023 12:21:44 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 204-20020a2514d5000000b00a3637aea9e1so23734348ybu.17 for ; Thu, 23 Mar 2023 12:21:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679599303; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Q3Z0gHxtmfZoBxhh4tWLHtA08dcRu+l0xhSXqfOrne0=; b=WGY7xAmNweh22oGHAaxaxszMGdLe6NedB+9iPB735C8A8CSkRd5a5xewpT3tZxgRE9 wsdBkdhH8uzOzswxN0vEU8NlwZb/82ndhAUQTyKYvPSKfL/QntlrzVSSU3AU+Dfbne/j 4rz4hg68ZaweYkw7zGoHENvoZ9LyRuqLeCPFSZDCXOZJuJcvKbAyXFf9kNHypMEksOFW S1C8uiD2uy3GUJPVEVEs99dt60YZcmWJD19hEaQOJePzG64XxGe/ssw196Dm9VpyREtk 6SaSJVWf5pKSZIewLhIjmVgxGLodzZndKhetpYVPUJR6f+PZfSP1pbRL7u+lw5oG6loq vN/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679599303; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Q3Z0gHxtmfZoBxhh4tWLHtA08dcRu+l0xhSXqfOrne0=; b=LGIloZCWGFse7jH3s4gyWvc26vSnEAyZBpkmz8UlkwuEH2bcj5A+QxqwcoBM+KMCAg hq3KbWmj4QlvKmMl4baIlKfLqGlbGKm9Cjw6G+V35UEJH7Ghz9BmHwEKkuWNic82hY2N YrVg5bQDyDdyZpNe3QPyWwhVLWFNmG2xquya6t0Vt1LCQZMoqyePm91vKWU6GPWK9a7l jMxCsi5DiGHtf8OouEd3zUKgSLXmBiV7ObFpTG7NStuLHwTqyMRRFsZ6tzwi1m09ZPd8 xY7zXSJ2Be6dqzs6AZq4GvOwtklJk7Y31B520oI5iFl0vCTxEkqqC8UsvgUoMtXPBCyZ 2RHw== X-Gm-Message-State: AAQBX9cBwWGELAaM6q+wg8dWLlRBUOdf0OallRIE+W3/i0k3gNrhAezJ 2Xfcxm8MifxyT2OLZptqAk+ExEZ2LkEv X-Google-Smtp-Source: AKy350aF17WKZObbDWKxDxkWyl/jUkcIB2KgCdJDGWqoPOOexrGmy4dQxHJXbirXJZQo+pj2xFWaAoj44JyR X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a05:6902:1021:b0:b77:3f5a:8a53 with SMTP id x1-20020a056902102100b00b773f5a8a53mr260388ybt.12.1679599302678; Thu, 23 Mar 2023 12:21:42 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:27 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-9-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 8/9] perf metrics: Add has_optane literal From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add literal so that if optane memory isn't installed we can record fewer events. The file detection mechanism was suggested by Dan Williams in: https://lore.kernel.org/linux-perf-users/641bbe1eced26_1b98bb29440@dwillia2= -xfh.jf.intel.com.notmuch/ Signed-off-by: Ian Rogers --- tools/perf/util/expr.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/tools/perf/util/expr.c b/tools/perf/util/expr.c index d46a1878bc9e..a43cdda0b044 100644 --- a/tools/perf/util/expr.c +++ b/tools/perf/util/expr.c @@ -14,6 +14,7 @@ #include "util/hashmap.h" #include "smt.h" #include "tsc.h" +#include #include #include #include @@ -400,6 +401,20 @@ double arch_get_tsc_freq(void) } #endif =20 +static double has_optane(void) +{ + static bool has_optane, cached; + const char *sysfs =3D sysfs__mountpoint(); + char path[PATH_MAX]; + + if (!cached) { + snprintf(path, sizeof(path), "%s/firmware/acpi/tables/NFIT", sysfs); + has_optane =3D access(path, F_OK) =3D=3D 0; + cached =3D true; + } + return has_optane ? 1.0 : 0.0; +} + double expr__get_literal(const char *literal, const struct expr_scanner_ct= x *ctx) { const struct cpu_topology *topology; @@ -449,6 +464,10 @@ double expr__get_literal(const char *literal, const st= ruct expr_scanner_ctx *ctx result =3D perf_pmu__cpu_slots_per_cycle(); goto out; } + if (!strcmp("#has_optane", literal)) { + result =3D has_optane(); + goto out; + } =20 pr_err("Unrecognized literal '%s'", literal); out: --=20 2.40.0.348.gf938b09366-goog From nobody Sat Feb 7 15:40:18 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 549CDC76196 for ; Thu, 23 Mar 2023 19:22:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231796AbjCWTWt (ORCPT ); Thu, 23 Mar 2023 15:22:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231161AbjCWTWV (ORCPT ); Thu, 23 Mar 2023 15:22:21 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C443310AA3 for ; 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bh=Xenl8HbHjUOf1l2xXBD3eq9W8bip5/6Vr49GtQAmSTQ=; b=MgfnvF0te0HElV/EfLvl1KLzuN2/Ja1UEUWJ6BS6RmDENIJzL+GIxJWLrNIPKtwYnj jmuWqsl2uMctUBJwqiEYznJdIff4/e1nKH9Ne2TeI/1gMd4tfynMx38jxkqgHEyNsEXD u/PAm9BFx9GhlJ/zYwMvsJut/Eo3tAjeVUSbrzPxDp7u9XB3ysapVjvy/0cGZKOWDRuV 2xpC/Q9YiDAPqyrTNmCsClemlc7+CGuRBR58B2h4m0Rfh8HBi22BcbNuZ0L7W77uczLs JajmfQ0UXnTuf4pxa1+Df+BZauYi6CIZ2RhNYPR680kuEXvBJ4a6Z00We1D/opVTTuip GcHA== X-Gm-Message-State: AAQBX9dBcP5UX60jG0atBVyrRLYUcxeU+JP4VuVrsEgPlvklwXetZB43 Pll/VHGsg1CrgcSwNG01e7dA4ZOIHved X-Google-Smtp-Source: AKy350bbUx56bdqhOHu+iALCV7RX7M705+rFo0Dv0Q7pH81pp9rKoPmhYmsJTqjAhiPmlGPuVnbWv7CfIby4 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e705:3a3d:46e5:fb50]) (user=irogers job=sendgmr) by 2002:a05:6902:1083:b0:98e:6280:74ca with SMTP id v3-20020a056902108300b0098e628074camr3104022ybu.1.1679599310975; Thu, 23 Mar 2023 12:21:50 -0700 (PDT) Date: Thu, 23 Mar 2023 12:20:28 -0700 In-Reply-To: <20230323192028.135759-1-irogers@google.com> Message-Id: <20230323192028.135759-10-irogers@google.com> Mime-Version: 1.0 References: <20230323192028.135759-1-irogers@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Subject: [PATCH v2 9/9] perf vendor events: Update metrics to detect optane memory at runtime From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Zhengjun Xing , Kan Liang , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Edward Baker , Dan Williams , perry.taylor@intel.com, caleb.biggers@intel.com, samantha.alt@intel.com, weilin.wang@intel.com Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" By detecting whether optane memory is installed at runtime the number of events can be reduced if it isn't. These changes come from this PR: https://github.com/intel/perfmon/pull/63 Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/cascadelakex/clx-metrics.json | 10 +++++----- .../perf/pmu-events/arch/x86/icelakex/icx-metrics.json | 10 +++++----- .../arch/x86/sapphirerapids/spr-metrics.json | 10 +++++----- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b= /tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 4e993a3220e3..903f19ea1696 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -201,7 +201,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CY= CLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_cl= ks - tma_l2_bound - tma_pmm_bound", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (C= YCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_c= lks - tma_l2_bound - tma_pmm_bound if #has_optane > 0 else CYCLE_ACTIVITY.S= TALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACT= IVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound)", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2= & tma_backend_bound > 0.2)", @@ -933,7 +933,7 @@ }, { "BriefDescription": "Average latency of data read request to exter= nal 3D X-Point memory [in nanoseconds]", - "MetricExpr": "1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_= INSERTS) / imc_0@event\\=3D0x0@", + "MetricExpr": "(1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ= _INSERTS) / imc_0@event\\=3D0x0@ if #has_optane > 0 else 0)", "MetricGroup": "Mem;MemoryLat;Server;SoC", "MetricName": "tma_info_mem_pmm_read_latency", "PublicDescription": "Average latency of data read request to exte= rnal 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L= 2 data-read prefetches" @@ -998,13 +998,13 @@ }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [= GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time i= f #has_optane > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_read_bw" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes = [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time i= f #has_optane > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_write_bw" }, @@ -1310,7 +1310,7 @@ { "BriefDescription": "This metric roughly estimates (based on idle = latencies) how often the CPU was stalled on accesses to external 3D-Xpoint = (Crystal Ridge, a.k.a", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM *= (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD= _L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIR= ED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * = (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOA= D_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RET= IRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOT= E_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD= _L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_= PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE= _ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS = - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (= MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOA= D_RETIRED.L1_MISS else 0)", + "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM= * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LO= AD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RET= IRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM = * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_L= OAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOA= D_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REM= OTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LO= AD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RE= TIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_optane > 0 else 0) + 33 * (MEM_= LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS) if #has_optane > 0 else 0))) if #has_optane > 0 else 0)) * = (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D= _MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1= e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > M= EM_LOAD_RETIRED.L1_MISS else 0) if #has_optane > 0 else 0)", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group= ;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 8109088a4df7..e5fba27dfe80 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -186,7 +186,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CY= CLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_cl= ks - tma_l2_bound - tma_pmm_bound", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (C= YCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_c= lks - tma_l2_bound - tma_pmm_bound if #has_optane > 0 else CYCLE_ACTIVITY.S= TALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACT= IVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound)", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2= & tma_backend_bound > 0.2)", @@ -918,7 +918,7 @@ }, { "BriefDescription": "Average latency of data read request to exter= nal 3D X-Point memory [in nanoseconds]", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_= CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=3D0x0@", + "MetricExpr": "(1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC= _CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=3D0x0@ if #has_optane > 0= else 0)", "MetricGroup": "Mem;MemoryLat;Server;SoC", "MetricName": "tma_info_mem_pmm_read_latency", "PublicDescription": "Average latency of data read request to exte= rnal 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L= 2 data-read prefetches" @@ -984,13 +984,13 @@ }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [= GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time i= f #has_optane > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_read_bw" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes = [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time i= f #has_optane > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_write_bw" }, @@ -1298,7 +1298,7 @@ }, { "BriefDescription": "This metric roughly estimates (based on idle = latencies) how often the CPU was stalled on accesses to external 3D-Xpoint = (Crystal Ridge, a.k.a", - "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM *= (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD= _L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIR= ED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * = (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOA= D_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RET= IRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOT= E_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD= _L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_= PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE= _ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS = - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (= MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOA= D_RETIRED.L1_MISS else 0)", + "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM= * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LO= AD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RET= IRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM = * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_L= OAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOA= D_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REM= OTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LO= AD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RE= TIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_optane > 0 else 0) + 33 * (MEM_= LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS) if #has_optane > 0 else 0))) if #has_optane > 0 else 0)) * = (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D= _MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1= e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > M= EM_LOAD_RETIRED.L1_MISS else 0) if #has_optane > 0 else 0)", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group= ;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json= b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index 149cc4c07fb5..d23fd6921a7f 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -185,7 +185,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks - tm= a_pmm_bound", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks - t= ma_pmm_bound if #has_optane > 0 else MEMORY_ACTIVITY.STALLS_L3_MISS / tma_i= nfo_clks)", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2= & tma_backend_bound > 0.2)", @@ -968,7 +968,7 @@ }, { "BriefDescription": "Average latency of data read request to exter= nal 3D X-Point memory [in nanoseconds]", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_= CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=3D0x1@", + "MetricExpr": "(1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC= _CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=3D0x1@ if #has_opt= ane > 0 else 0)", "MetricGroup": "Mem;MemoryLat;Server;SoC", "MetricName": "tma_info_mem_pmm_read_latency", "PublicDescription": "Average latency of data read request to exte= rnal 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L= 2 data-read prefetches" @@ -1034,13 +1034,13 @@ }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [= GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time i= f #has_optane > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_read_bw" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes = [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time i= f #has_optane > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_write_bw" }, @@ -1406,7 +1406,7 @@ }, { "BriefDescription": "This metric roughly estimates (based on idle = latencies) how often the CPU was stalled on accesses to external 3D-Xpoint = (Crystal Ridge, a.k.a", - "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM *= (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD= _L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIR= ED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * = (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOA= D_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RET= IRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOT= E_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD= _L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.F= B_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_= PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (MEMOR= Y_ACTIVITY.STALLS_L3_MISS / tma_info_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIR= ED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else= 0)", + "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM= * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LO= AD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RET= IRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM = * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_L= OAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOA= D_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REM= OTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LO= AD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RE= TIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_optane > 0 else 0) + 33 * (MEM_= LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_R= ETIRED.L1_MISS) if #has_optane > 0 else 0))) if #has_optane > 0 else 0)) * = (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks) if 1e6 * (MEM_LOAD_L3_MISS= _RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MIS= S else 0) if #has_optane > 0 else 0)", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group= ;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", --=20 2.40.0.348.gf938b09366-goog