From nobody Tue Feb 10 00:58:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC1B5C76196 for ; Thu, 23 Mar 2023 05:31:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230343AbjCWFbg (ORCPT ); Thu, 23 Mar 2023 01:31:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230331AbjCWFbF (ORCPT ); Thu, 23 Mar 2023 01:31:05 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18BC022797 for ; Wed, 22 Mar 2023 22:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1679549456; x=1711085456; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aNL2KliVK/W0PGGaQa+13McnVurhskx2OOU+yOO7uSY=; b=ALhUWyojgqzHzE6KZpUEEJgv2r6amjn/APoDkMzpbwHmI2Ev+5f0wGkL GrQ1EeYTsQGiaArk4Se0fDL4P7Xwjp/rABdqYaK6BXjU1Wbgrdlyykfkp BWTijKAFWhhrYc2t8gRwFsp2l3fZDVW4skpvsWXy3bqJ2EnB7YFhRHtA7 XGuGkkRdKRZfXeXpi4ig3/KeLpEr6D1oD8ySB+b8SGQSc3LSZR/y+MisP N+ZC8dkWQB2HegBJfn0Z8cKqLCY+hgwE5r/Wi1kY8pKx67rlYxUhZX5zi St3A+hK6xOt5xJSdroWfcHVUU9UN60TM6J0WWh8WpM441bU3OfwRVwosE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="327779422" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="327779422" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2023 22:30:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10657"; a="675567132" X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="675567132" Received: from bard-ubuntu.sh.intel.com ([10.239.185.57]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2023 22:30:18 -0700 From: Bard Liao To: alsa-devel@alsa-project.org, vkoul@kernel.org, broonie@kernel.org Cc: vinod.koul@linaro.org, linux-kernel@vger.kernel.org, pierre-louis.bossart@linux.intel.com, bard.liao@intel.com, tiwai@suse.de Subject: [PATCH 12/20] soundwire: intel_ace2x: set SYNCPRD before powering-up Date: Thu, 23 Mar 2023 13:44:44 +0800 Message-Id: <20230323054452.1543233-13-yung-chuan.liao@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230323054452.1543233-1-yung-chuan.liao@linux.intel.com> References: <20230323054452.1543233-1-yung-chuan.liao@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pierre-Louis Bossart The registers used for multi-link synchronization are no longer in the SHIM but in the HDaudio multi-link capability space. Use helpers to configure the SYNCPRD value, and wait for SYNCPU to change after powering-up. Note that the SYNCPRD value is shared between all sublinks, for obvious reasons if those links are supposed to be synchronized. The value of SYNCPRD is programmed only once for all sublinks. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Rander Wang Reviewed-by: P=C3=A9ter Ujfalusi Reviewed-by: Ranjani Sridharan Signed-off-by: Bard Liao --- drivers/soundwire/intel_ace2x.c | 42 +++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/soundwire/intel_ace2x.c b/drivers/soundwire/intel_ace2= x.c index 5b6a608e63ba..01668246b7ba 100644 --- a/drivers/soundwire/intel_ace2x.c +++ b/drivers/soundwire/intel_ace2x.c @@ -17,17 +17,51 @@ =20 static int intel_link_power_up(struct sdw_intel *sdw) { + struct sdw_bus *bus =3D &sdw->cdns.bus; + struct sdw_master_prop *prop =3D &bus->prop; + u32 *shim_mask =3D sdw->link_res->shim_mask; + unsigned int link_id =3D sdw->instance; + u32 syncprd; int ret; =20 mutex_lock(sdw->link_res->shim_lock); =20 - ret =3D hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, sdw->inst= ance); + if (!*shim_mask) { + /* we first need to program the SyncPRD/CPU registers */ + dev_dbg(sdw->cdns.dev, "first link up, programming SYNCPRD\n"); + + if (prop->mclk_freq % 6000000) + syncprd =3D SDW_SHIM_SYNC_SYNCPRD_VAL_38_4; + else + syncprd =3D SDW_SHIM_SYNC_SYNCPRD_VAL_24; + + ret =3D hdac_bus_eml_sdw_set_syncprd_unlocked(sdw->link_res->hbus, sync= prd); + if (ret < 0) { + dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_set_syncprd failed: %d\n", + __func__, ret); + goto out; + } + } + + ret =3D hdac_bus_eml_sdw_power_up_unlocked(sdw->link_res->hbus, link_id); if (ret < 0) { dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_up failed: %d\n", __func__, ret); goto out; } =20 + if (!*shim_mask) { + /* SYNCPU will change once link is active */ + ret =3D hdac_bus_eml_sdw_wait_syncpu_unlocked(sdw->link_res->hbus); + if (ret < 0) { + dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_wait_syncpu failed: %d\n", + __func__, ret); + goto out; + } + } + + *shim_mask |=3D BIT(link_id); + sdw->cdns.link_up =3D true; out: mutex_unlock(sdw->link_res->shim_lock); @@ -37,13 +71,17 @@ static int intel_link_power_up(struct sdw_intel *sdw) =20 static int intel_link_power_down(struct sdw_intel *sdw) { + u32 *shim_mask =3D sdw->link_res->shim_mask; + unsigned int link_id =3D sdw->instance; int ret; =20 mutex_lock(sdw->link_res->shim_lock); =20 sdw->cdns.link_up =3D false; =20 - ret =3D hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, sdw->in= stance); + *shim_mask &=3D ~BIT(link_id); + + ret =3D hdac_bus_eml_sdw_power_down_unlocked(sdw->link_res->hbus, link_id= ); if (ret < 0) { dev_err(sdw->cdns.dev, "%s: hdac_bus_eml_sdw_power_down failed: %d\n", __func__, ret); --=20 2.25.1