From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5FC8C6FD1C for ; Wed, 22 Mar 2023 06:40:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229812AbjCVGkp (ORCPT ); Wed, 22 Mar 2023 02:40:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229524AbjCVGkl (ORCPT ); Wed, 22 Mar 2023 02:40:41 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBD0F5504C for ; Tue, 21 Mar 2023 23:40:39 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id x17so22068363lfu.5 for ; Tue, 21 Mar 2023 23:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FlGRV4Vhjc5QjOFgeSLcd0kZILFPjn08+TF/cmBPkFY=; b=uCKZa9QeBxerqrIsMoSQJ6uqAnomCynjZFwSl6qEn4TFlAEjxOPbHVrJB7E0BkwkTx SXiuYJCPdb89tZrSpddToqvKlV7M9biNNoTmfIIfiysX6PDTK6RgMj8IR821PiCndIeh V/MKInlsxlM3klGQKHXOBuH78FiYRdDxdaBgLTh/JjXDhug7nNmIh4UabesZkBtEQNXF oFZrCJteY8SDzfZQWVMeOUQ51rfeLvY3FDRe8QBZPsKL9JyvIwABfa0x0eCkVA+D/eSL K3XBdNI3USnjqXe5SRvKWHTEU6c3uJviMNSALz23RONNIjw9XZzrgmc+o+X4xm27vf2O 1l7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FlGRV4Vhjc5QjOFgeSLcd0kZILFPjn08+TF/cmBPkFY=; b=Cg3ZKmssu8uZR69eV9VUHMjPXs1P8gEg8SkUJuYDmwxJzt2XT6GpgYGBOqomNzZQXd 4KFiTmcM2BrT0e/JMssGOwehLBzXiMFYDSrioB9n5jAl5JLSUoxahAeqYCO5NQzwqz0W GWF/iLWTHiiXHEI+Aml+X0oNX+JBmVlJPxrZNQtxOIbFYuUTHf4hJZqsJkky8PKXrpWi 13bQj3bQeJ/bA7QOocoDwefKLyFk/gAo4Gbd4iglbSfLGxpJMJJRpsA+Lu4Z7ifNMWyh DTpxTYtOiCfx9THADeLl7qQG/QMVddMvVx+6xQeizqTPcAfOc3q2FrOTZT+TTID6AtB+ MFdg== X-Gm-Message-State: AAQBX9czzK12y/L8huSQa7RKf6Ho0Lm3vgTCmYbwT/3KtMtIzmrM2ORA CCaTxNjpduZgNW6hPchbLNt8ng== X-Google-Smtp-Source: AK7set/gJMXStUd+2nNEyzeYJ/hzFyEM8ObZQirw/aRa36i7qRDdFoYiAf7/P5XnmOpjKyZIf1YtLw== X-Received: by 2002:ac2:48aa:0:b0:4d5:c96f:f7c7 with SMTP id u10-20020ac248aa000000b004d5c96ff7c7mr1606305lfg.23.1679467238091; Tue, 21 Mar 2023 23:40:38 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:37 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 01/11] mtd: spi-nor: core: Move generic method to core - micron_st_nor_set_4byte_addr_mode Date: Wed, 22 Mar 2023 06:40:23 +0000 Message-Id: <20230322064033.2370483-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Move the method to core. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 24 ++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/micron-st.c | 24 ------------------------ 3 files changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 0a78045ca1d9..8d246b1b439a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -538,6 +538,30 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, b= ool enable) return ret; } =20 +/** + * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and + * Micron flashes. + * @nor: pointer to 'struct spi_nor'. + * @enable: true to enter the 4-byte address mode, false to exit the 4-byte + * address mode. + * + * Return: 0 on success, -errno otherwise. + */ +int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +{ + int ret; + + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + + ret =3D spi_nor_set_4byte_addr_mode(nor, enable); + if (ret) + return ret; + + return spi_nor_write_disable(nor); +} + /** * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion * flashes. diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 25423225c29d..aa44474c042a 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -635,6 +635,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); +int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_lock_and_prep(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 7bb86df52f0b..3bbf65234ebd 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -301,30 +301,6 @@ static const struct flash_info st_nor_parts[] =3D { { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) }, }; =20 -/** - * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and - * Micron flashes. - * @nor: pointer to 'struct spi_nor'. - * @enable: true to enter the 4-byte address mode, false to exit the 4-byte - * address mode. - * - * Return: 0 on success, -errno otherwise. - */ -static int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool ena= ble) -{ - int ret; - - ret =3D spi_nor_write_enable(nor); - if (ret) - return ret; - - ret =3D spi_nor_set_4byte_addr_mode(nor, enable); - if (ret) - return ret; - - return spi_nor_write_disable(nor); -} - /** * micron_st_nor_read_fsr() - Read the Flag Status Register. * @nor: pointer to 'struct spi_nor' --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFB83C6FD1F for ; Wed, 22 Mar 2023 06:40:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230012AbjCVGks (ORCPT ); Wed, 22 Mar 2023 02:40:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229762AbjCVGkl (ORCPT ); Wed, 22 Mar 2023 02:40:41 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EDB659E6D for ; Tue, 21 Mar 2023 23:40:40 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id bi9so22026321lfb.12 for ; Tue, 21 Mar 2023 23:40:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sbdjw1RSh3TEpk/7p7usBCYi4BEXdtSILvnz97JipYc=; b=Sh9Cd9BbxyTKKZzOwojOx1zCCxqy5Farawal5XysHHeyLiixDg2zZEAvx3DSsuUTMT J5qsR9Xr7C2ELEZiaNIYPZfw23Cl/UUfuSYeX3550OtjgcVqPmgKZqWCbWJg60hgwaP+ i4q5n2DW/5pcwGqnNzqQupXmMBIJVa5J8bFUV93th0Jg8iuIuzgKvFlbqEQ+ToEfn2a9 Zv9m//fmuNrQkvSCbBY7l/l/g04xJDkUPmxX6Dc8lfA3MzfgT/EswH8ikyHm38REsuXs /wC+dvSlPGud69QrZqHXPIqDqR3CVPcq5AK7VhFT7jnPAoMMkVojT3041jY/jdY1mD7Z /xdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sbdjw1RSh3TEpk/7p7usBCYi4BEXdtSILvnz97JipYc=; b=7Km2hJApokNF/A62Ly5sgwDs4HMGeiON9kzOVaOSfVcrKuBlh+sayNqlAhuBZd6lYB 3q/10QTezL96ywOxS9SPw9OSqGglG/iBbSVbmtgTkwsekjlRsIBlgtKvsl8QBpzyYfyW sa7dzWokLBONPNZN2+imYSnps5893PJuVybpPFvBYPXkGJ9UYXV9J9eCyLcwTmNXXfrR gZkjLg2HOS74Dlo5s8kNE/KBlAw2zzpWu6RI91TSH6hb4ZjGgEPYZJ86BL4ekADQOwAq WLy3B8UTjX6neTP0QwRC3jhERpumzfRK4K/Y9I/TMiD1d3vCBS2ZQZfJ9dfV+C2imtn0 Lndg== X-Gm-Message-State: AO0yUKXPFj8I42zaiugTlY7ZMcHI2cMmU3UVGbVL5UPBuOa59Tk4HY+5 27srIh6F+pTdlryiOTADUWAt8Q== X-Google-Smtp-Source: AK7set/H6+Aq8gAk3QEpJ20qjtugTm4sRtXWEgnVic14jRpmQYPYNbdlWkA3NFahwpLABQCB0Afl2A== X-Received: by 2002:ac2:44d9:0:b0:4db:ee9:7684 with SMTP id d25-20020ac244d9000000b004db0ee97684mr1609008lfm.56.1679467238677; Tue, 21 Mar 2023 23:40:38 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:38 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 02/11] mtd: spi-nor: core: Update name and description of micron_st_nor_set_4byte_addr_mode Date: Wed, 22 Mar 2023 06:40:24 +0000 Message-Id: <20230322064033.2370483-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rename method to spi_nor_set_4byte_addr_mode_wren_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(30) and BIT(22). Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 7 ++++--- drivers/mtd/spi-nor/core.h | 3 ++- drivers/mtd/spi-nor/micron-st.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 8d246b1b439a..2cb7425b3694 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -539,15 +539,16 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, = bool enable) } =20 /** - * micron_st_nor_set_4byte_addr_mode() - Set 4-byte address mode for ST and - * Micron flashes. + * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode = using + * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically = used + * by ST and Micron flashes. * @nor: pointer to 'struct spi_nor'. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte * address mode. * * Return: 0 on success, -errno otherwise. */ -int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool e= nable) { int ret; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index aa44474c042a..2fc08c26081f 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -635,7 +635,8 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); -int micron_st_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, + bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_lock_and_prep(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 3bbf65234ebd..a75f0f4e1c38 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -425,7 +425,7 @@ static void micron_st_nor_default_init(struct spi_nor *= nor) nor->flags |=3D SNOR_F_HAS_LOCK; nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; nor->params->quad_enable =3D NULL; - nor->params->set_4byte_addr_mode =3D micron_st_nor_set_4byte_addr_mode; + nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4= b_ex4b; } =20 static void micron_st_nor_late_init(struct spi_nor *nor) --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4354C74A5B for ; Wed, 22 Mar 2023 06:40:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229751AbjCVGkv (ORCPT ); Wed, 22 Mar 2023 02:40:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229968AbjCVGkm (ORCPT ); Wed, 22 Mar 2023 02:40:42 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3745532A1 for ; Tue, 21 Mar 2023 23:40:40 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id t11so22078050lfr.1 for ; Tue, 21 Mar 2023 23:40:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T+znX5tPTNkGmk0JqPSC8AVns2+lpyBiaG5wqS+7IkU=; b=upBa8JoJB+dW1aq5RxiwsD3VkAe3BDxYlaWXFj12EKZi/U6P/pmFw4z0Wol2+Q3ONE GPeGTQMnf3Y1MOjSItUZk2NBpKmmMBo2+n1YkFo2w4bXZsYZdqnHMjGf9Dcgmpv4hPFe gtupyxjvFkaZIBDwMMRD72xYjvQwDRWy9zHNEMjmpTmVSnSnBcaxrbVUc+rCBfp55OCB I3Dse1PcyhPrSrksuBrQqbz696fAQk3wM9VsoMlkmZRqceeKZxIBvfF1juQuZUzoZSOY hVFFujtKuwZe9BTgR6ot58r3kOf4Jf4LA72DOjyWQllDyougtq+zi0PWEo676/YxJgqJ l8Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467239; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T+znX5tPTNkGmk0JqPSC8AVns2+lpyBiaG5wqS+7IkU=; b=ueflFq+cxK7e89Ed9wFU0bZ5TR7JDzeRkf/HZdovBsFiRqZvyqNWcwse+C3idWWEgX S5mg91FyEQDt7PmYXv2E66pEwgzEU3UPFnr84gTjXfrzifMKizpHi1/w2UcHYA/PFf5i eIfdflndejQg+WaXyG5j7Bm2hj9OrKxJjj83o4cyMcSQeVZmwpdNc6lVl7GULKRrrnkn zCzP8ZqbLPEepLOZ3l0F9wWmuwMRAr0k8kF05bL0ozi+BfSyV6F9Ad0i5QPMiLRwz+H6 3W6KC0r+OUaVP4554soWAVI/biLIMIlsZRUg5g89ywXcSjoFE7pZlSV19Tt6vu1jjJbz Ik+g== X-Gm-Message-State: AO0yUKUxHzTi/qM9InBYKEJ3DXQAb67TUt+xiodysQ5YT8WzxcWpBZ0M LsMT3l/dXGWmbPHCDWb0kOIenw== X-Google-Smtp-Source: AK7set8Hp2tr7q5+wrvsbOObm6X3ICWNwQTG0szK8hhiPXxRRBMP8UDsjz0rg5nsIHz+J3PHlcoMfQ== X-Received: by 2002:a05:6512:1285:b0:4e8:3cfe:98c7 with SMTP id u5-20020a056512128500b004e83cfe98c7mr337794lfs.4.1679467239263; Tue, 21 Mar 2023 23:40:39 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:38 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 03/11] mtd: spi-nor: core: Update name and description of spansion_set_4byte_addr_mode Date: Wed, 22 Mar 2023 06:40:25 +0000 Message-Id: <20230322064033.2370483-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rename method to spi_nor_set_4byte_addr_mode_brwr and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(28) and BIT(20). Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 2cb7425b3694..e80dcd87189b 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -564,15 +564,20 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct= spi_nor *nor, bool enable) } =20 /** - * spansion_set_4byte_addr_mode() - Set 4-byte address mode for Spansion - * flashes. + * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using + * SPINOR_OP_BRWR. Typically used by Spansion flashes. * @nor: pointer to 'struct spi_nor'. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte * address mode. * + * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]= ) is + * used to enable/disable 4-byte address mode. When MSB is set to =E2=80= =981=E2=80=99, 4-byte + * address mode is active and A[30:24] bits are don=E2=80=99t care. Write = instruction is + * SPINOR_OP_BRWR(17h) with 1 byte of data. + * * Return: 0 on success, -errno otherwise. */ -static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +static int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enab= le) { int ret; =20 @@ -2599,7 +2604,7 @@ static void spi_nor_init_default_params(struct spi_no= r *nor) struct device_node *np =3D spi_nor_get_flash_node(nor); =20 params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; - params->set_4byte_addr_mode =3D spansion_set_4byte_addr_mode; + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; params->otp.org =3D &info->otp_org; =20 /* Default to 16-bit Write Status (01h) Command */ --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1295AC761A6 for ; Wed, 22 Mar 2023 06:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230051AbjCVGky (ORCPT ); Wed, 22 Mar 2023 02:40:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbjCVGkm (ORCPT ); Wed, 22 Mar 2023 02:40:42 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90DFD59E7C for ; Tue, 21 Mar 2023 23:40:41 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id y20so22080462lfj.2 for ; Tue, 21 Mar 2023 23:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=onn7qzpEkAoSPCvz5HXi6C8mwJXx4hkbdPzDlnc9ItE=; b=pAABZrarHek863hg3GjsOPwFr4nfpKBBy0573hnYGg0V5rCZsduRAiguChBAceHph3 NWqdeR4Wt807f2NBJk7UsVYYBKKIvWOh7sv2YTqbp6yoinKlWmqBQhbDASWnMI7US5vx Wni0GuLip4ZiJA9f+AHqecKmOTyY0xWnK3kyyBUXu8Ad4ysaQlmmF8SlqKCjDy9BMTLl 5mECsjSb78wW4eLbPronCGSVt7z5/cLJ92+UwSs9hgReJzEj5QwmWiNHE7MKf67zFyeQ 9UQKtIrPEq9O5jfDDeWp433V5JRDhTo+d924hi2e2v10GnAL3es474+YiJB/+o2Q1fqW +0ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=onn7qzpEkAoSPCvz5HXi6C8mwJXx4hkbdPzDlnc9ItE=; b=b4o3cTQyenIfuY4Z/XggcKW4lY+2l3xOAD3Mprz2PiEC5SWYVusMPJPNzqA8SiCYwd rg2VSF9xZBJ2ItH5WlTVlzpf472dzyeHnOCI589NWahczvvuNyU6ibjv4Xvg/AFHvE13 ULCA6caXEV+TXalbXbYys+CNC+lrYP0QHAdZY8tzZXl7SEGT80yv5GDAgZ3g7BgViGuP fYgnwTht/tWeH6KpT6ej2yJF7s3cetLJ7VDkRZsSMb1gr+IuVRKotSDgz4tQ1L2Ua3+g wf7WSRrCdVRj/hQQX4uKEUSIpRJTyB95qdvMQgxL0zNUwDwvtr++6CPByMvm0MLyKwBe xouQ== X-Gm-Message-State: AO0yUKVPq/JVG7rm3cjms1Q4oBS0rRYKLPmkMEGQOQezWlIZGhRcDNif PHG5Z04afbnKGwhRdQa2np1eHg== X-Google-Smtp-Source: AK7set8WvTk1sxAAUY8QOewdfzC3II7UdJzeTUmibypMHp6nvVTMEbWr82rYaZExDxdvogSXvRDVog== X-Received: by 2002:ac2:442a:0:b0:4e8:3f38:7d21 with SMTP id w10-20020ac2442a000000b004e83f387d21mr1684219lfl.28.1679467239953; Tue, 21 Mar 2023 23:40:39 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:39 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 04/11] mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_mode Date: Wed, 22 Mar 2023 06:40:26 +0000 Message-Id: <20230322064033.2370483-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rename method to spi_nor_set_4byte_addr_mode_en4b_ex4b and extend its description. This method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(31) and BIT(23). Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 8 +++++--- drivers/mtd/spi-nor/core.h | 2 +- drivers/mtd/spi-nor/macronix.c | 2 +- drivers/mtd/spi-nor/winbond.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index e80dcd87189b..d80366f8a7e9 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -508,14 +508,16 @@ int spi_nor_read_cr(struct spi_nor *nor, u8 *cr) } =20 /** - * spi_nor_set_4byte_addr_mode() - Enter/Exit 4-byte address mode. + * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode + * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by + * Winbond and Macronix. * @nor: pointer to 'struct spi_nor'. * @enable: true to enter the 4-byte address mode, false to exit the 4-byte * address mode. * * Return: 0 on success, -errno otherwise. */ -int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) +int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable) { int ret; =20 @@ -556,7 +558,7 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct s= pi_nor *nor, bool enable) if (ret) return ret; =20 - ret =3D spi_nor_set_4byte_addr_mode(nor, enable); + ret =3D spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable); if (ret) return ret; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 2fc08c26081f..7961b81262db 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -634,7 +634,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, const enum spi_nor_protocol proto); int spi_nor_write_enable(struct spi_nor *nor); int spi_nor_write_disable(struct spi_nor *nor); -int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable= ); int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 6853ec9ae65d..91a8fa7d4512 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -105,7 +105,7 @@ static const struct flash_info macronix_nor_parts[] =3D= { static void macronix_nor_default_init(struct spi_nor *nor) { nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; - nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode; + nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex4= b; } =20 static const struct spi_nor_fixups macronix_nor_fixups =3D { diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index ca39acf4112c..9cea241c204b 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -188,7 +188,7 @@ static int winbond_nor_set_4byte_addr_mode(struct spi_n= or *nor, bool enable) { int ret; =20 - ret =3D spi_nor_set_4byte_addr_mode(nor, enable); + ret =3D spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable); if (ret || enable) return ret; =20 --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6C58C6FD1C for ; Wed, 22 Mar 2023 06:40:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230070AbjCVGk5 (ORCPT ); Wed, 22 Mar 2023 02:40:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229987AbjCVGkn (ORCPT ); Wed, 22 Mar 2023 02:40:43 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 547A85504C for ; Tue, 21 Mar 2023 23:40:42 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id g17so22067897lfv.4 for ; Tue, 21 Mar 2023 23:40:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yxz/5hnL2T7rNNpiPeZo7eIaeTKEHB7uXS6/jbC9PHU=; b=v+kPJMRJo1rQREWsNHIc9ZOfW9W4JUMXNoruq6ACxJ+y8XA1x0Ij4qJb7WVc0AtjCL yODyRwyU9PJKa3DShgHmzxs2t46D9W3SuVIb/ipRi754mWES3fu71jG8gpELb4lBZrNj mfs7Xt21ETj+Kgek445U2ysnqWzq9YbmypaiCc0SPhf8S6D1kkXVSbRJqjCey831Cvsj nniXhNZ7vMLe70dnsm+tJqWIQzlLylsFo4zuu9rlijzs9CH9K+l4kgebVSuNpsF4NVWm EZ8OR7gD6e/xofa7RWD5k5KBwWFEVOKQegdcgS93MimKFWyq/xkCSavYJZQTuWtKPfNy Ftrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467240; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yxz/5hnL2T7rNNpiPeZo7eIaeTKEHB7uXS6/jbC9PHU=; b=mhLgpw5A4ZBWhse91lrxDoBkLMrlFoc/R3xwzK0FZNBM+hx76oSM98Yd32kdKLLAyn ov68P2ubJcPTscYBy/pEta8yzXIrCiO308nZyjV0b2OEKJLO02DkZ0PzfpiSFYYuqMGF NZwZny44LWp/5KKpDb+4ptkZMiBeSTrkELWTrQH5xtHvvS2mR4WngULCtQQ7vQdS2GVf WbJCOdIUjjFsrurLuV2ILjBervMG+3M9GjImu8yFH5XfhcWVb7eS2D0ALWGUtjv5ju34 K77jhThur8vSnp7IdGKbODBI8BwqcwZqkRpmN2mAV+IJu+zHh8E75LgiwmPSUBf8Q9Ao 54xg== X-Gm-Message-State: AO0yUKXk1BXEgiUogn0DCQJjeCYR6is42VdewStnBMm4M1CufyjA/M36 caJ3b+3YlH2qmmr2gaVd1ux2bw== X-Google-Smtp-Source: AK7set/4hxkITfYD5g8YTDG4mtdd/X3KLEWegGCwXWTJigSb1WfNYd725qkEj86RzXzmzo1Ec/rcwA== X-Received: by 2002:ac2:434e:0:b0:4d5:8dd8:75f9 with SMTP id o14-20020ac2434e000000b004d58dd875f9mr1763398lfl.24.1679467240702; Tue, 21 Mar 2023 23:40:40 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:40 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 05/11] mtd: spi-nor: core: Make spi_nor_set_4byte_addr_mode_brwr public Date: Wed, 22 Mar 2023 06:40:27 +0000 Message-Id: <20230322064033.2370483-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This method can be retrieved at BFPT parsing time. The method is described in JESD216 BFPT[SFDP_DWORD(16)], BIT(28) and BIT(20). Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index d80366f8a7e9..e212cc3c630d 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -579,7 +579,7 @@ int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct s= pi_nor *nor, bool enable) * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enab= le) +int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable) { int ret; =20 diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 7961b81262db..394d251450f7 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -637,6 +637,7 @@ int spi_nor_write_disable(struct spi_nor *nor); int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable= ); int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_lock_and_prep(struct spi_nor *nor); --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E588C6FD1F for ; Wed, 22 Mar 2023 06:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229662AbjCVGlA (ORCPT ); Wed, 22 Mar 2023 02:41:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229992AbjCVGkp (ORCPT ); Wed, 22 Mar 2023 02:40:45 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 563F75B5D9 for ; Tue, 21 Mar 2023 23:40:43 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id y20so22080512lfj.2 for ; Tue, 21 Mar 2023 23:40:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jv+mpUAZwkOh2eeM+ctcdr1FWMN9cPSlCRNPkUJDfOM=; b=IsUHCsURkrKzfVF9FTo8CpXo5cdwqWMeHrhqOZXQ2LJ7Dxj125BHHR7lB0mgVaHrEB 6jqc2tIt/Ojae4grV8rz812MXaoiuYheF3e1g6KceYQ1CGvCvceU2YbBNUNxgusosHq9 tZ625ww5rA6Khu7QRyre8+Udyzoyn7W/3fIwloiYuqwvgmioJ4xs6mi7r26R5e8vlFPQ 8nK0M5PNnwmN2KilGY114n1OZC6dmd1ilfXfSQgyh+nCl8Kzu0n+LzGQxI3ROKqZoBji KzAo0qQWrOKXTGL2ZAsKhkPDJ8Af6qhXdieLEHXeU0g/uzKgTnVDdqE5S5M5j3qsbjJf AftQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467241; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jv+mpUAZwkOh2eeM+ctcdr1FWMN9cPSlCRNPkUJDfOM=; b=ZZQIQ02CguyBMC+gv0LMWKLamv7vz5ELyzhKAX8DAjWTZzMVCbpRk8ZU8NgihzXko8 k/yGZ//KJGdyeOmBafX3tuEs8ltOvAQfjPYIFhLkOmz/qtpNWfe8ESB8LKKkErCiPtes Y9gCbfckt5aIctKZ2VR/ykEi+3Qo6Tl/tlMNy3Wv0CHqMS8QZUmb7C/s4Yi/XKnWmK9D 5UPsK3wkpOnsDESdoOmaigHguoZ/m1/D4PXHXXRbOkq8JRIbxQqQhLsngOiNXvXWA57N R6c+0/bGzUjw6X4EATpzDCFghC+d62dI0qR/AWNoILlYQey4F0079QHw1hfLn7bdspu7 f2/w== X-Gm-Message-State: AO0yUKVvTkltPEnhIz9Jm1Nx6qi2NdnWpi1W5gjgWaN8ythCfGWFTxbM X9TXk5nkqp5HDMyXVpBKuptQcw== X-Google-Smtp-Source: AK7set/WXhgfu25geTxkrdgYFE1ioV5AxG+bYZaCiZxwqSgK04DjO1lvy2TvrbLCaxZcNxLJuRNEaA== X-Received: by 2002:a19:ae12:0:b0:4b5:26f3:2247 with SMTP id f18-20020a19ae12000000b004b526f32247mr1430002lfc.69.1679467241660; Tue, 21 Mar 2023 23:40:41 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:41 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 06/11] mtd: spi-nor: Parse BFPT to determine the 4-Byte Address Mode methods Date: Wed, 22 Mar 2023 06:40:28 +0000 Message-Id: <20230322064033.2370483-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" BFPT[DWORD(16)] defines the methods to enter and exit the 4-Byte Address Mode. Parse BFPT to determine the method. Will rename the methods with generic names in a further patch, to keep things trackable in this one. Some regressions may be introduced by this patch, because the params->set_4byte_addr_mode method that was set either in spi_nor_init_default_params() or later overwritten in default_init() hooks, may now be overwritten with a different value based on the BFPT data. If that's the case, the fix is to introduce a post_bfpt fixup hook where one should fix the wrong BFPT info. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/sfdp.c | 11 +++++++++++ drivers/mtd/spi-nor/sfdp.h | 28 ++++++++++++++++++++++++++++ drivers/mtd/spi-nor/winbond.c | 11 ++++++++++- 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 298ab5e53a8c..63b2810cf75e 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -438,6 +438,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, size_t len; int i, cmd, err; u32 addr, val; + u32 dword; u16 half; u8 erase_mask; =20 @@ -607,6 +608,16 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; } =20 + dword =3D bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_4B_ADDR_MODE_MASK; + if (sfdp_bits_set(dword, BFPT_DWORD16_4B_ADDR_MODE_BRWR)) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; + else if (sfdp_bits_set(dword, BFPT_DWORD16_4B_ADDR_MODE_WREN_EN4B_EX4B)) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4b_ex= 4b; + else if (sfdp_bits_set(dword, BFPT_DWORD16_4B_ADDR_MODE_EN4B_EX4B)) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex4b; + else + dev_dbg(nor->dev, "BFPT: 4-Byte Address Mode method is not recognized or= not implemented\n"); + /* Soft Reset support. */ if (bfpt.dwords[SFDP_DWORD(16)] & BFPT_DWORD16_SWRST_EN_RST) nor->flags |=3D SNOR_F_SOFT_RESET; diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index 500659b35655..a4b5fe795f18 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -16,6 +16,8 @@ /* SFDP DWORDS are indexed from 1 but C arrays are indexed from 0. */ #define SFDP_DWORD(i) ((i) - 1) =20 +#define sfdp_bits_set(dword, mask) (((dword) & (mask)) =3D=3D (mask)) + /* Basic Flash Parameter Table */ =20 /* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. */ @@ -89,6 +91,32 @@ struct sfdp_bfpt { #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ =20 +#define BFPT_DWORD16_EN4B_MASK GENMASK(31, 24) +#define BFPT_DWORD16_EN4B_ALWAYS_4B BIT(30) +#define BFPT_DWORD16_EN4B_4B_OPCODES BIT(29) +#define BFPT_DWORD16_EN4B_16BIT_NV_CR BIT(28) +#define BFPT_DWORD16_EN4B_BRWR BIT(27) +#define BFPT_DWORD16_EN4B_WREAR BIT(26) +#define BFPT_DWORD16_EN4B_WREN_EN4B BIT(25) +#define BFPT_DWORD16_EN4B_EN4B BIT(24) +#define BFPT_DWORD16_EX4B_MASK GENMASK(18, 14) +#define BFPT_DWORD16_EX4B_16BIT_NV_CR BIT(18) +#define BFPT_DWORD16_EX4B_BRWR BIT(17) +#define BFPT_DWORD16_EX4B_WREAR BIT(16) +#define BFPT_DWORD16_EX4B_WREN_EX4B BIT(15) +#define BFPT_DWORD16_EX4B_EX4B BIT(14) +#define BFPT_DWORD16_4B_ADDR_MODE_MASK \ + (BFPT_DWORD16_EN4B_MASK | BFPT_DWORD16_EX4B_MASK) +#define BFPT_DWORD16_4B_ADDR_MODE_16BIT_NV_CR \ + (BFPT_DWORD16_EN4B_16BIT_NV_CR | BFPT_DWORD16_EX4B_16BIT_NV_CR) +#define BFPT_DWORD16_4B_ADDR_MODE_BRWR \ + (BFPT_DWORD16_EN4B_BRWR | BFPT_DWORD16_EX4B_BRWR) +#define BFPT_DWORD16_4B_ADDR_MODE_WREAR \ + (BFPT_DWORD16_EN4B_WREAR | BFPT_DWORD16_EX4B_WREAR) +#define BFPT_DWORD16_4B_ADDR_MODE_WREN_EN4B_EX4B \ + (BFPT_DWORD16_EN4B_WREN_EN4B | BFPT_DWORD16_EX4B_WREN_EX4B) +#define BFPT_DWORD16_4B_ADDR_MODE_EN4B_EX4B \ + (BFPT_DWORD16_EN4B_EN4B | BFPT_DWORD16_EX4B_EX4B) #define BFPT_DWORD16_SWRST_EN_RST BIT(12) =20 #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) diff --git a/drivers/mtd/spi-nor/winbond.c b/drivers/mtd/spi-nor/winbond.c index 9cea241c204b..a1b387accc07 100644 --- a/drivers/mtd/spi-nor/winbond.c +++ b/drivers/mtd/spi-nor/winbond.c @@ -218,13 +218,22 @@ static const struct spi_nor_otp_ops winbond_nor_otp_o= ps =3D { =20 static void winbond_nor_default_init(struct spi_nor *nor) { - nor->params->set_4byte_addr_mode =3D winbond_nor_set_4byte_addr_mode; } =20 static void winbond_nor_late_init(struct spi_nor *nor) { if (nor->params->otp.org->n_regions) nor->params->otp.ops =3D &winbond_nor_otp_ops; + + /* + * Winbond seems to require that the Extended Address Register to be set + * to zero when exiting the 4-Byte Address Mode, at least for W25Q256FV. + * This requirement is not described in the JESD216 SFDP standard, thus + * it is Winbond specific. Since we do not know if other Winbond flashes + * have the same requirement, play safe and overwrite the method parsed + * from BFPT, if any. + */ + nor->params->set_4byte_addr_mode =3D winbond_nor_set_4byte_addr_mode; } =20 static const struct spi_nor_fixups winbond_nor_fixups =3D { --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99C78C6FD1C for ; Wed, 22 Mar 2023 06:41:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbjCVGlC (ORCPT ); Wed, 22 Mar 2023 02:41:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbjCVGkp (ORCPT ); Wed, 22 Mar 2023 02:40:45 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65B9C5BC83 for ; Tue, 21 Mar 2023 23:40:44 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id y15so22046534lfa.7 for ; Tue, 21 Mar 2023 23:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7CqzcpXczhyO/MskUeS2f3sX+qT4MR1so+/9l/YtqFc=; b=FBY/smWUsRVvtCRBAfu8tQadv6JK++O9TapE/YI0DuNHxOCWLhDs9GYPplwqqpsBN5 zVkmNEZr7JO0NIFOnoRkM+/kA0/flpg7UlxvUyezgLe69esU9lgSuei0bOORS9cW03t1 8O8XnEfpk2qVI3bQiPy4QJnSZXgQ7q7V1jXrcR+WhYuWOVcQLkiKD56DbPzvluSBTO92 RHlyaPq42jgfy73Onu8iS27AINcP82/5iYD/pTUwGROob5gLLEgz1EGBXIjz90Z8JoJt yYfsDmgzPJoGKQj6sLskGF4mSscx1fjW8OZHqHrIpN6RDcuSMlS503Hd+hGOEiuI/eL2 TutA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7CqzcpXczhyO/MskUeS2f3sX+qT4MR1so+/9l/YtqFc=; b=si/OrXoYGV6g0JOBdhTN80TEjOCaw1lCEUQ4QowNtGVidtbqKQM1KGw/gE5m0/WR4/ P8HrW7yd854SDEo87xUN45RmCjSR1/oGYcryyKZVRESnyP5xPE1vuOL89/1w77Wmjp+u lXOXp+7JueaNeC0lIIlVbB3xe0SOP0Lj0FJGAd8o09TlYNCVRnad4Ts68XN3KE+RPK0m NcGphwX/VqRQJl58BlxyqjFUEIDtZVaQCJ8ZLj4MBKZJFMUx9aa2vpDLVdEOck4yt4X/ 2jHnew3WdsONppzSxF7ss23hII2XpXSTDIuQnqFtjdCVOvYtl8ykbF3ZQpdD4v3seLtb sogA== X-Gm-Message-State: AO0yUKXTo+Nfo4GNjz1M7Ji9f4bYXuDb1WU1gX/eofXiVjYxtqI6cvYe F9571yq2ntGBECiKTKXF/jUNzgzK2Bw95egJBW4D7g== X-Google-Smtp-Source: AK7set+T+BKSGh6wjzTT0l/3oupZc6kAm36EV9dKkOOpmKKNSV807apEePn3kBnZaY/cn0m5+R86Lg== X-Received: by 2002:a05:6512:3751:b0:4a4:68b9:19e7 with SMTP id a17-20020a056512375100b004a468b919e7mr1642583lfs.15.1679467242589; Tue, 21 Mar 2023 23:40:42 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:41 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus , Pratyush Yadav Subject: [PATCH v4 07/11] mtd: spi-nor: Favor the BFPT-parsed set_4byte_addr_mode method Date: Wed, 22 Mar 2023 06:40:29 +0000 Message-Id: <20230322064033.2370483-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" JESD216 SFDP defines in the BFPT standard methods to enter and exit the 4-Byte Address Mode. The flash parameters and settings that are retrieved from SFDP have higher precedence than the static initialized ones, because they should be more accurate and less error prone than those initialized statically. Favor the BFPT-parsed set_4byte_addr_mode method and use the generic core methods where possible. This patch may introduce regressions in case BFPT contains wrong data. The fix is to introduce a post_bfpt() fixup hook and update the wrong BFPT data. Signed-off-by: Tudor Ambarus Reviewed-by: Pratyush Yadav --- drivers/mtd/spi-nor/core.c | 7 ++++++- drivers/mtd/spi-nor/macronix.c | 8 +++++++- drivers/mtd/spi-nor/micron-st.c | 6 ++++-- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index e212cc3c630d..2a08f8de97fa 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2533,6 +2533,8 @@ static void spi_nor_init_fixup_flags(struct spi_nor *= nor) */ static void spi_nor_late_init_params(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; + if (nor->manufacturer && nor->manufacturer->fixups && nor->manufacturer->fixups->late_init) nor->manufacturer->fixups->late_init(nor); @@ -2540,6 +2542,10 @@ static void spi_nor_late_init_params(struct spi_nor = *nor) if (nor->info->fixups && nor->info->fixups->late_init) nor->info->fixups->late_init(nor); =20 + /* Default method kept for backward compatibility. */ + if (!params->set_4byte_addr_mode) + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; + spi_nor_init_flags(nor); spi_nor_init_fixup_flags(nor); =20 @@ -2606,7 +2612,6 @@ static void spi_nor_init_default_params(struct spi_no= r *nor) struct device_node *np =3D spi_nor_get_flash_node(nor); =20 params->quad_enable =3D spi_nor_sr2_bit1_quad_enable; - params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; params->otp.org =3D &info->otp_org; =20 /* Default to 16-bit Write Status (01h) Command */ diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 91a8fa7d4512..075a26945f2d 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -105,11 +105,17 @@ static const struct flash_info macronix_nor_parts[] = =3D { static void macronix_nor_default_init(struct spi_nor *nor) { nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; - nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex4= b; +} + +static void macronix_nor_late_init(struct spi_nor *nor) +{ + if (!nor->params->set_4byte_addr_mode) + nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_en4b_ex= 4b; } =20 static const struct spi_nor_fixups macronix_nor_fixups =3D { .default_init =3D macronix_nor_default_init, + .late_init =3D macronix_nor_late_init, }; =20 const struct spi_nor_manufacturer spi_nor_macronix =3D { diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index a75f0f4e1c38..4d5333b14807 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -425,13 +425,15 @@ static void micron_st_nor_default_init(struct spi_nor= *nor) nor->flags |=3D SNOR_F_HAS_LOCK; nor->flags &=3D ~SNOR_F_HAS_16BIT_SR; nor->params->quad_enable =3D NULL; - nor->params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4= b_ex4b; } =20 static void micron_st_nor_late_init(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; + if (nor->info->mfr_flags & USE_FSR) - nor->params->ready =3D micron_st_nor_ready; + params->ready =3D micron_st_nor_ready; + params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_wren_en4b_ex4= b; } =20 static const struct spi_nor_fixups micron_st_nor_fixups =3D { --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 993C7C6FD1F for ; Wed, 22 Mar 2023 06:41:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230095AbjCVGlF (ORCPT ); Wed, 22 Mar 2023 02:41:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229843AbjCVGkq (ORCPT ); Wed, 22 Mar 2023 02:40:46 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E10055BC8A for ; Tue, 21 Mar 2023 23:40:44 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id q16so11212936lfe.10 for ; Tue, 21 Mar 2023 23:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DJfZKigBIeChWOChUBeVAQfEZHFms3jVy0ZK/PQ531k=; b=GXOWONJwTRivIy6517fCgO6hyO0N3AxoYQNRie7uPM3oSvUEtTfErM2Ju2Q+JMhwrh 02KdBggKf8GXBSQxTATLVlizdGXlaSxSk1nSP8Tk1dU0RQu0gDc5dlLb5Xud1wOVxLfm +05ecDO2Rhnr4cW/nwVFJcBZrtxcYO6gmrqcCHTIPM23CMFDE8QJ04GeT8A6TjZUW4fq vVnkmzNj5CwUGHY2SLY+QSAaudULkkR3Z0Nbm1VrNGgvRmj+wtfmUdW2AfeJ4Ci4Pr8c b216+98OAE3zfra/5eSupJyZ+f5v+4fR7Q1yHw7JoxAlzftJEEXq1By36uUSpgOHLBwg 2/Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DJfZKigBIeChWOChUBeVAQfEZHFms3jVy0ZK/PQ531k=; b=M8iD/NhXxpkyo9esRnjrVB90p3Hgw+tw1o3vZOW/VpM1kVaB/W2rfqcvQ7es0hF+IU TjLGVdAfi2eppUr1ZotCyL+CQEwLLkGhKiFe910aaRquuC1ETzb46RVCSHWiHKuZKRx9 ipipZscJMI1osz+R1qxbkUvcRLS536u/P2J1OCwpijzlzV9YXJu7gZ402OPrtST+gAOz d1Y/Mn0trR7+AXi11T4tikoKl92ytXIkeGHhoTGfEVFJOOCGwZ8Wn+MmsbrjZPK5eYCB Vu449R0hdKko1hcrfjxig6aPG9KLTmvtzbtqGMyzzyWtLxFTeqQJlOHg21ZY/tVokUg8 7S1w== X-Gm-Message-State: AO0yUKXiMgUVbBmNwXluXEB4j0XKwGR/e2apjNBXfjvZuv7+uI1Zw5dU Om5b6469KZK5t9pTFJPb1xdp9A== X-Google-Smtp-Source: AKy350aU6oZfJKOyA5joErp2v+jd3KokKBm3ODOpDtqzLBKBfJpb9+F7caJ9EwuQ56pHTjQbER2k6Q== X-Received: by 2002:ac2:428e:0:b0:4ea:c730:aac3 with SMTP id m14-20020ac2428e000000b004eac730aac3mr391733lfh.3.1679467243288; Tue, 21 Mar 2023 23:40:43 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:42 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 08/11] mtd: spi-nor: Stop exporting spi_nor_restore() Date: Wed, 22 Mar 2023 06:40:30 +0000 Message-Id: <20230322064033.2370483-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some SPI NOR controllers that used this method were moved to drivers/spi/. We don't accept new support for the existing SPI NOR controllers drivers under drivers/mtd/spi-nor/controllers/ and we encourage their owners to move the drivers under drivers/spi/. Make spi_nor_restore() private as we're going to use it just in core.c. Signed-off-by: Tudor Ambarus --- Documentation/driver-api/mtd/spi-nor.rst | 3 --- drivers/mtd/spi-nor/core.c | 3 +-- include/linux/mtd/spi-nor.h | 6 ------ 3 files changed, 1 insertion(+), 11 deletions(-) diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/drive= r-api/mtd/spi-nor.rst index 4a3adca417fd..c22f8c0f7950 100644 --- a/Documentation/driver-api/mtd/spi-nor.rst +++ b/Documentation/driver-api/mtd/spi-nor.rst @@ -63,6 +63,3 @@ The main API is spi_nor_scan(). Before you call the hook,= a driver should initialize the necessary fields for spi_nor{}. Please see drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to spi-fsl-qsp= i.c when you want to write a new driver for a SPI NOR controller. -Another API is spi_nor_restore(), this is used to restore the status of SPI -flash chip such as addressing mode. Call it whenever detach the driver from -device or reboot the system. diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 2a08f8de97fa..1cf566fed9c6 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2924,7 +2924,7 @@ static void spi_nor_put_device(struct mtd_info *mtd) module_put(dev->driver->owner); } =20 -void spi_nor_restore(struct spi_nor *nor) +static void spi_nor_restore(struct spi_nor *nor) { int ret; =20 @@ -2944,7 +2944,6 @@ void spi_nor_restore(struct spi_nor *nor) if (nor->flags & SNOR_F_SOFT_RESET) spi_nor_soft_reset(nor); } -EXPORT_SYMBOL_GPL(spi_nor_restore); =20 static const struct flash_info *spi_nor_match_name(struct spi_nor *nor, const char *name) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index a3f8cdca90c8..8aac4522bf2a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -437,10 +437,4 @@ static inline struct device_node *spi_nor_get_flash_no= de(struct spi_nor *nor) int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps); =20 -/** - * spi_nor_restore_addr_mode() - restore the status of SPI NOR - * @nor: the spi_nor structure - */ -void spi_nor_restore(struct spi_nor *nor); - #endif --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E0DAC6FD1F for ; Wed, 22 Mar 2023 06:41:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229939AbjCVGlI (ORCPT ); Wed, 22 Mar 2023 02:41:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229996AbjCVGkq (ORCPT ); Wed, 22 Mar 2023 02:40:46 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0719D5BC8D for ; Tue, 21 Mar 2023 23:40:45 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id h25so10392721lfv.6 for ; Tue, 21 Mar 2023 23:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OjibXlExvge37of3uq5kGMqBiMIjX3D2b9DBjXXdAOg=; b=UWFPA1O80E8Yvytt01jq2QIZlVrmn7Jcyha10uK9nvBUeZ9OymTt6B8Z9AX3M1FOVk FAgiDSO/jaNYlZwykZtkM6h8Br2W+Xz3Upj+p1cJ3G9NUWRYMew1DqmVVcxg5s3xhR6W P91VXlrP4QY4cVIZIPaw74N3GzXJs/CWhQEK6vuRWwkKRvwhFYhgMhM2OX/jvg3VuVOM 73Z/Q0t2qS9GkaccmEy2b5NdVtlgmhAPox9KqyABqgEIl07lkYOdVCdKoQoS9014wOwR 4MuZ77zV2HQU60wNZPhj+9F35cimJ5cg6Prcql48PgTM4ngXq9dDpTVf1swH+/8w6rq1 YMVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467244; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OjibXlExvge37of3uq5kGMqBiMIjX3D2b9DBjXXdAOg=; b=fnQ6b6TczLlDXUSMpy+OyNu/5PhHeeeIBhl0NWaLGe4BxUjADIY2AL3iCn2hniZD7I 348fJyqSNXtXQYPjYsi5RmLqf00oAGpkSKXEezSYaOjPoq1pyxKrpiv5auK+uyMZ5g8j VLiunWkoaQErpvXb0x1ZRQoEoq9wywiJ/uPSeRPzh/W1BsYID0Sfc+J7i3qfkyG6TeJc lLVut2O+i0o4DhqzJiZU7t9fWki58qXS0fGALGKPFoXmsX23eJhaN/KLOmCSbxkSoZ4x FipUKIUt50R+gbFgd9plaKmft9Vl2F9Wx6lehOJTWsSa8Z+jV1WMavqWbYdMb7Sr18nY RrAQ== X-Gm-Message-State: AO0yUKUb1+oeYn/o0xpu2Tn0xMirjsBnxEuzPXwVVCSJdBqUFt3aJTlc NmdzFoyW/gtfJWc62g4HOheJKQ== X-Google-Smtp-Source: AK7set8Qi0viAviwjYHM3w8QtxMrW5ArDewIDKji6YiN0pl8h2sw0lxNoFC7eh4swxgCw7JwHCrZQw== X-Received: by 2002:ac2:43a4:0:b0:4e8:47cd:b4ba with SMTP id t4-20020ac243a4000000b004e847cdb4bamr1676972lfl.13.1679467244027; Tue, 21 Mar 2023 23:40:44 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:43 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus , stable@vger.kernel.org Subject: [PATCH v4 09/11] mtd: spi-nor: core: Update flash's current address mode when changing address mode Date: Wed, 22 Mar 2023 06:40:31 +0000 Message-Id: <20230322064033.2370483-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The bug was obswerved while reading code. There are not many users of addr_mode_nbytes. Anyway, we should update the flash's current address mode when changing the address mode, fix it. We don't care for now about the set_4byte_addr_mode(nor, false) from spi_nor_restore(), as it is used at driver remove and shutdown. Cc: stable@vger.kernel.org Fixes: d7931a215063 ("mtd: spi-nor: core: Track flash's internal address mo= de") Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 1cf566fed9c6..868414017399 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2769,6 +2769,7 @@ static int spi_nor_quad_enable(struct spi_nor *nor) =20 static int spi_nor_init(struct spi_nor *nor) { + struct spi_nor_flash_parameter *params =3D nor->params; int err; =20 err =3D spi_nor_octal_dtr_enable(nor, true); @@ -2810,9 +2811,10 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - err =3D nor->params->set_4byte_addr_mode(nor, true); + err =3D params->set_4byte_addr_mode(nor, true); if (err && err !=3D -ENOTSUPP) return err; + params->addr_mode_nbytes =3D 4; } =20 return 0; --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C149BC6FD1F for ; Wed, 22 Mar 2023 06:41:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229663AbjCVGlL (ORCPT ); Wed, 22 Mar 2023 02:41:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230009AbjCVGkr (ORCPT ); Wed, 22 Mar 2023 02:40:47 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B784A59E6D for ; Tue, 21 Mar 2023 23:40:45 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id y20so22080649lfj.2 for ; Tue, 21 Mar 2023 23:40:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CiEhw/MYHGHqYkcULW44qvOE1f5BKxwdN9TbdhHpk2k=; b=BBaAP+qofU6gmMoZlFnCXX5iuME7bAK/wwLkOJ2EcO8w35hd21eorA711U2+NkSE4S w+wQs0/U5LhpKGGHGuv4FfUpvh2uYVqm5ngOKU9v+dayckn9I6DTisjrE5a78OR3Q/hn RQ5nyrPPfAyKHcgqgdwK1/U3W1DPhw9Rw9oYPLS8SGX42riKBlsh8rbob3BvhBmuoQ9K mPaktuupbfiZ7Gbp5WDnswM1DTGpEVy/Agr7lceidC9nW5BKWMqiOdkSCFW3d/a7B4Qe Vgb5Bcl2DmLLsyxc6bfcvECAcAInt/jzF22HK6lSJ8UvtjFCg4oTo1Skdu1WmI19gjYK BRjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467245; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CiEhw/MYHGHqYkcULW44qvOE1f5BKxwdN9TbdhHpk2k=; b=K92eZjY26k/CzVBYASQUxqsDGUjsn/2F7c4uvDtU3VW6tdRIKWjBIFfd6IGolYtrPI prQYeOMk09HULvEwx/WktwhVLi/EA6bLt2r4Im1t0K+QlSF0hqiZBW5Mj4KwijmbDNCi uPfKa1Z894NYAE2YFewlvSKHc+UDHhGtYgk1QxVV8S6w+Bz1YOWIuXc/G+kJTVAAg+lG YNI226f4n+xRzKR754orSY6k8qw9l9p/Kv4lOQ7yeBPem48QNpnM/Km+4bI5IqdgB1Ac zkOFxxm4MS+KFfmOlPTgUWZDff6bv2fq7fUNlYMMdLq5VhHUYHV8/Pw+H4O3mTh4Ehll 0uqQ== X-Gm-Message-State: AO0yUKUI21ZdFXD5a2cEkiozi7Z/JJQHkoxLViWPcNxLU1Y7T6ImboVP wCMV8jCW8MJs3Co1uWkWoOaKlw== X-Google-Smtp-Source: AK7set9mwp/p2VqPULgSXCe1sfhlNyAc9FbRP4BC0wGsaqvFqr85PMyc+ebH+CiHqgx0/P+pMV3taQ== X-Received: by 2002:a19:5210:0:b0:4ea:d6c7:c897 with SMTP id m16-20020a195210000000b004ead6c7c897mr1608728lfb.31.1679467245271; Tue, 21 Mar 2023 23:40:45 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:44 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 10/11] mtd: spi-nor: core: Introduce spi_nor_set_4byte_addr_mode() Date: Wed, 22 Mar 2023 06:40:32 +0000 Message-Id: <20230322064033.2370483-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make the method public, as it will be used as a last resort to enable 4byte address mode when we can't determine the address mode at runtime. Update the addr_nbytes and current address mode while exiting the 4byte address mode too, as it may be used in the future by manufacturer drivers. No functional change. spi_nor_restore didn't update the address mode nbytes, but updating them now doesn't harm as the method is called in the driver's remove and shutdown paths. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 35 ++++++++++++++++++++++++++++++----- drivers/mtd/spi-nor/core.h | 1 + 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 868414017399..4b2a6697a192 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2767,9 +2767,35 @@ static int spi_nor_quad_enable(struct spi_nor *nor) return nor->params->quad_enable(nor); } =20 -static int spi_nor_init(struct spi_nor *nor) +/** + * spi_nor_set_4byte_addr_mode() - Set address mode. + * @nor: pointer to a 'struct spi_nor'. + * @enable: enable/disable 4 byte address mode. + * + * Return: 0 on success, -errno otherwise. + */ +int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) { struct spi_nor_flash_parameter *params =3D nor->params; + int ret; + + ret =3D params->set_4byte_addr_mode(nor, enable); + if (ret && ret !=3D -ENOTSUPP) + return ret; + + if (enable) { + params->addr_nbytes =3D 4; + params->addr_mode_nbytes =3D 4; + } else { + params->addr_nbytes =3D 3; + params->addr_mode_nbytes =3D 3; + } + + return 0; +} + +static int spi_nor_init(struct spi_nor *nor) +{ int err; =20 err =3D spi_nor_octal_dtr_enable(nor, true); @@ -2811,10 +2837,9 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - err =3D params->set_4byte_addr_mode(nor, true); - if (err && err !=3D -ENOTSUPP) + err =3D spi_nor_set_4byte_addr_mode(nor, true); + if (err) return err; - params->addr_mode_nbytes =3D 4; } =20 return 0; @@ -2933,7 +2958,7 @@ static void spi_nor_restore(struct spi_nor *nor) /* restore the addressing mode */ if (nor->addr_nbytes =3D=3D 4 && !(nor->flags & SNOR_F_4B_OPCODES) && nor->flags & SNOR_F_BROKEN_RESET) { - ret =3D nor->params->set_4byte_addr_mode(nor, false); + ret =3D spi_nor_set_4byte_addr_mode(nor, false); if (ret) /* * Do not stop the execution in the hope that the flash diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 394d251450f7..7152688d3985 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -638,6 +638,7 @@ int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_no= r *nor, bool enable); int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable); int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable); +int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable); int spi_nor_wait_till_ready(struct spi_nor *nor); int spi_nor_global_block_unlock(struct spi_nor *nor); int spi_nor_lock_and_prep(struct spi_nor *nor); --=20 2.40.0.rc1.284.g88254d51c5-goog From nobody Mon Feb 9 01:06:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E20AC6FD1F for ; Wed, 22 Mar 2023 06:41:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229876AbjCVGlP (ORCPT ); Wed, 22 Mar 2023 02:41:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230022AbjCVGku (ORCPT ); Wed, 22 Mar 2023 02:40:50 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BC835B5FC for ; Tue, 21 Mar 2023 23:40:48 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id i13so6377693lfe.9 for ; Tue, 21 Mar 2023 23:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679467246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UB2d2IEiiJcGXzBHNy9s2vUD62/sXfHS54tkdN1U+34=; b=sAYham2shXJkNdF7HOQMen2SiiZX4gIz+Lgi/ueSbtSZtaCcRBgdtSxfVSP1UnNWhQ J/O+obHZp6SPmO/nkkEuwsxbqkah93ye/6a5tbm4+IxHdCeWfGz9OF6OORvNCwC3GjtL /WkBGlgwEfiI2vyBivW5ItzEpOteTz/6+lF/nzXoYZWO+ergRmPkKql0cRnrK30eJSaS padq4NJz/vRgRP+2781iVyDhgF+t9tbJdZVqDiFcCFHWxM4Vl4ELR3ZR9edmVKJyPamq c+q4MmPI3IGHJ9SxAnvEluDpz8a+UFmqHmn/0A7EI7aLPggqoA0WgSBkrORVbBLP/0YZ PtxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679467246; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UB2d2IEiiJcGXzBHNy9s2vUD62/sXfHS54tkdN1U+34=; b=Eoagjb8ag+2MgagGICzoLIvZUKQVjHflohShfsHZwnqz3+lIY8dqlTguYjVOPd9exb 1x/+dmfwKSB+2im2lrRXGxtpTsy/Tw0P0+/7elRgXzjoTQ0r7+/OVSVYAW79AIkJyEv4 7yQHVWQstbkthLr9UVHP7LSV4Jc8hQ6rYDpQlME11dM5CJY3fJEW5SGSe19FVQ+GHu5q Hmct9BDDw7R7i3pOpULCsoxRHz0sVPAkW9dHotRc/qVMz33jFM8rUqcL+DZWxBk0UFmZ DCYpfP27jUAephzqMpDo6C3pIKV1gYD+0dUA5DpWKL7flHAf28aUTv804KjOwAsmLPu6 vsYg== X-Gm-Message-State: AO0yUKVvYikoNBKxubewXbd5qDo/BgHX/CBZbCmeL2gMvp3eRcMyG+jX qkVqd0im1LlvlBx9HVmhnc9TsQ== X-Google-Smtp-Source: AK7set+xMoeEZ739iDZP0qDAY5AXuY0e5jSQ8XLUOpn1wXMnT5NNU5jq4Up+LET1pTHT3IQ6q7UIcw== X-Received: by 2002:a19:ad03:0:b0:4a4:6af4:43b7 with SMTP id t3-20020a19ad03000000b004a46af443b7mr1601504lfc.69.1679467246059; Tue, 21 Mar 2023 23:40:46 -0700 (PDT) Received: from ta1.c.googlers.com.com (61.215.228.35.bc.googleusercontent.com. [35.228.215.61]) by smtp.gmail.com with ESMTPSA id n20-20020ac242d4000000b004dafde0e7b7sm2462255lfl.279.2023.03.21.23.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 23:40:45 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, pratyush@kernel.org Cc: miquel.raynal@bootlin.com, richard@nod.at, Takahiro.Kuwano@infineon.com, bacem.daassi@infineon.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v4 11/11] mtd: spi-nor: spansion: Determine current address mode Date: Wed, 22 Mar 2023 06:40:33 +0000 Message-Id: <20230322064033.2370483-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230322064033.2370483-1-tudor.ambarus@linaro.org> References: <20230322064033.2370483-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Takahiro Kuwano Internal address mode (3- or 4-byte) affects to the address length in Read Any Reg op. Read Any Reg op is used in SMPT parse and other setup functions. Current driver assumes that address mode is factory default but users can change it via volatile and non-volatile registers. Current address mode can be checked by CFR2V[7] but Read Any Reg op is needed to read CFR2V (chicken-and-egg). This patch introduces a way to determine current address mode by comparing status register 1 values read by different address length. Suggested-by: Tudor Ambarus Signed-off-by: Takahiro Kuwano Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 131 ++++++++++++++++++++++++++++++++- 1 file changed, 128 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 1678b7b2e9f7..ab2103dace76 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -14,10 +14,12 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ +#define SPINOR_REG_CYPRESS_STR1V 0x00800000 #define SPINOR_REG_CYPRESS_CFR1V 0x00800002 #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ #define SPINOR_REG_CYPRESS_CFR2V 0x00800003 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb +#define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3V 0x00800004 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ #define SPINOR_REG_CYPRESS_CFR5V 0x00800006 @@ -188,6 +190,117 @@ static int cypress_nor_quad_enable_volatile(struct sp= i_nor *nor) return 0; } =20 +/** + * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mo= de + * (3 or 4-byte) by querying st= atus + * register 1 (SR1). + * @nor: pointer to a 'struct spi_nor' + * @addr_mode: ponter to a buffer where we return the determined + * address mode. + * + * This function tries to determine current address mode by comparing SR1 = value + * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address). + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor, + u8 *addr_mode) +{ + struct spi_mem_op op =3D + CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0, + nor->bouncebuf); + bool is3byte, is4byte; + int ret; + + ret =3D spi_nor_read_sr(nor, &nor->bouncebuf[1]); + if (ret) + return ret; + + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + is3byte =3D (nor->bouncebuf[0] =3D=3D nor->bouncebuf[1]); + + op =3D (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0, + nor->bouncebuf); + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + is4byte =3D (nor->bouncebuf[0] =3D=3D nor->bouncebuf[1]); + + if (is3byte =3D=3D is4byte) + return -EIO; + if (is3byte) + *addr_mode =3D 3; + else + *addr_mode =3D 4; + + return 0; +} + +/** + * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mo= de of + * current address mode. + * @nor: pointer to a 'struct spi_nor' + * + * Determine current address mode by reading SR1 with different methods, t= hen + * query CFR2V[7] to confirm. If determination is failed, force enter to 4= -byte + * address mode. + * + * Return: 0 on success, -errno otherwise. + */ +static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor) +{ + u8 addr_mode; + struct spi_mem_op op; + int ret; + + /* + * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable + * that sets bit-1 in SR1. + */ + ret =3D spi_nor_write_enable(nor); + if (ret) + return ret; + ret =3D cypress_nor_determine_addr_mode_by_sr1(nor, &addr_mode); + if (ret) { + ret =3D spi_nor_set_4byte_addr_mode(nor, true); + if (ret) + return ret; + return spi_nor_write_disable(nor); + } + ret =3D spi_nor_write_disable(nor); + if (ret) + return ret; + + /* + * Query CFR2V and make sure no contradiction between determined address + * mode and CFR2V[7]. + */ + op =3D (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode, SPINOR_REG_CYPRESS_CFR2V, + 0, nor->bouncebuf); + ret =3D spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + + if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { + if (addr_mode !=3D 4) + return spi_nor_set_4byte_addr_mode(nor, true); + } else { + if (addr_mode !=3D 3) + return spi_nor_set_4byte_addr_mode(nor, true); + } + + nor->params->addr_nbytes =3D addr_mode; + nor->params->addr_mode_nbytes =3D addr_mode; + + return 0; +} + /** * cypress_nor_set_page_size() - Set page size which corresponds to the fl= ash * configuration. @@ -227,9 +340,9 @@ s25fs256t_post_bfpt_fixup(struct spi_nor *nor, struct spi_mem_op op; int ret; =20 - /* 4-byte address mode is enabled by default */ - nor->params->addr_nbytes =3D 4; - nor->params->addr_mode_nbytes =3D 4; + ret =3D cypress_nor_set_addr_mode_nbytes(nor); + if (ret) + return ret; =20 /* Read Architecture Configuration Register (ARCFN) */ op =3D (struct spi_mem_op) @@ -280,6 +393,12 @@ s25hx_t_post_bfpt_fixup(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt) { + int ret; + + ret =3D cypress_nor_set_addr_mode_nbytes(nor); + if (ret) + return ret; + /* Replace Quad Enable with volatile version */ nor->params->quad_enable =3D cypress_nor_quad_enable_volatile; =20 @@ -375,6 +494,12 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, const struct sfdp_parameter_header *bfpt_header, const struct sfdp_bfpt *bfpt) { + int ret; + + ret =3D cypress_nor_set_addr_mode_nbytes(nor); + if (ret) + return ret; + return cypress_nor_set_page_size(nor); } =20 --=20 2.40.0.rc1.284.g88254d51c5-goog