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[2003:f6:af34:4e00:7f5e:5982:a136:b54e]) by smtp.gmail.com with ESMTPSA id w11-20020a1709067c8b00b009231714b3d4sm6356260ejo.151.2023.03.21.18.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 18:34:27 -0700 (PDT) From: Mathias Krause To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Paolo Bonzini , Mathias Krause Subject: [PATCH v4 1/6] KVM: x86/mmu: Avoid indirect call for get_cr3 Date: Wed, 22 Mar 2023 02:37:26 +0100 Message-Id: <20230322013731.102955-2-minipli@grsecurity.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322013731.102955-1-minipli@grsecurity.net> References: <20230322013731.102955-1-minipli@grsecurity.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini Most of the time, calls to get_guest_pgd result in calling kvm_read_cr3 (the exception is only nested TDP). Hardcode the default instead of using the get_cr3 function, avoiding a retpoline if they are enabled. Signed-off-by: Paolo Bonzini Signed-off-by: Mathias Krause --- arch/x86/kvm/mmu/mmu.c | 31 ++++++++++++++++++++----------- arch/x86/kvm/mmu/paging_tmpl.h | 2 +- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 144c5a01cd77..9046a892998e 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -242,6 +242,20 @@ static struct kvm_mmu_role_regs vcpu_to_role_regs(stru= ct kvm_vcpu *vcpu) return regs; } =20 +static unsigned long get_guest_cr3(struct kvm_vcpu *vcpu) +{ + return kvm_read_cr3(vcpu); +} + +static inline unsigned long kvm_mmu_get_guest_pgd(struct kvm_vcpu *vcpu, + struct kvm_mmu *mmu) +{ + if (IS_ENABLED(CONFIG_RETPOLINE) && mmu->get_guest_pgd =3D=3D get_guest_c= r3) + return kvm_read_cr3(vcpu); + + return mmu->get_guest_pgd(vcpu); +} + static inline bool kvm_available_flush_tlb_with_range(void) { return kvm_x86_ops.tlb_remote_flush_with_range; @@ -3731,7 +3745,7 @@ static int mmu_alloc_shadow_roots(struct kvm_vcpu *vc= pu) int quadrant, i, r; hpa_t root; =20 - root_pgd =3D mmu->get_guest_pgd(vcpu); + root_pgd =3D kvm_mmu_get_guest_pgd(vcpu, mmu); root_gfn =3D root_pgd >> PAGE_SHIFT; =20 if (mmu_check_root(vcpu, root_gfn)) @@ -4181,7 +4195,7 @@ static bool kvm_arch_setup_async_pf(struct kvm_vcpu *= vcpu, gpa_t cr2_or_gpa, arch.token =3D alloc_apf_token(vcpu); arch.gfn =3D gfn; arch.direct_map =3D vcpu->arch.mmu->root_role.direct; - arch.cr3 =3D vcpu->arch.mmu->get_guest_pgd(vcpu); + arch.cr3 =3D kvm_mmu_get_guest_pgd(vcpu, vcpu->arch.mmu); =20 return kvm_setup_async_pf(vcpu, cr2_or_gpa, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); @@ -4200,7 +4214,7 @@ void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,= struct kvm_async_pf *work) return; =20 if (!vcpu->arch.mmu->root_role.direct && - work->arch.cr3 !=3D vcpu->arch.mmu->get_guest_pgd(vcpu)) + work->arch.cr3 !=3D kvm_mmu_get_guest_pgd(vcpu, vcpu->arch.mmu)) return; =20 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true, NULL); @@ -4604,11 +4618,6 @@ void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t ne= w_pgd) } EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd); =20 -static unsigned long get_cr3(struct kvm_vcpu *vcpu) -{ - return kvm_read_cr3(vcpu); -} - static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, unsigned int access) { @@ -5159,7 +5168,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu, context->page_fault =3D kvm_tdp_page_fault; context->sync_page =3D nonpaging_sync_page; context->invlpg =3D NULL; - context->get_guest_pgd =3D get_cr3; + context->get_guest_pgd =3D get_guest_cr3; context->get_pdptr =3D kvm_pdptr_read; context->inject_page_fault =3D kvm_inject_page_fault; =20 @@ -5309,7 +5318,7 @@ static void init_kvm_softmmu(struct kvm_vcpu *vcpu, =20 kvm_init_shadow_mmu(vcpu, cpu_role); =20 - context->get_guest_pgd =3D get_cr3; + context->get_guest_pgd =3D get_guest_cr3; context->get_pdptr =3D kvm_pdptr_read; context->inject_page_fault =3D kvm_inject_page_fault; } @@ -5323,7 +5332,7 @@ static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu, return; =20 g_context->cpu_role.as_u64 =3D new_mode.as_u64; - g_context->get_guest_pgd =3D get_cr3; + g_context->get_guest_pgd =3D get_guest_cr3; g_context->get_pdptr =3D kvm_pdptr_read; g_context->inject_page_fault =3D kvm_inject_page_fault; =20 diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmpl.h index a056f2773dd9..8417ecbc3887 100644 --- a/arch/x86/kvm/mmu/paging_tmpl.h +++ b/arch/x86/kvm/mmu/paging_tmpl.h @@ -324,7 +324,7 @@ static int FNAME(walk_addr_generic)(struct guest_walker= *walker, trace_kvm_mmu_pagetable_walk(addr, access); retry_walk: walker->level =3D mmu->cpu_role.base.level; - pte =3D mmu->get_guest_pgd(vcpu); + pte =3D kvm_mmu_get_guest_pgd(vcpu, mmu); have_ad =3D PT_HAVE_ACCESSED_DIRTY(mmu); =20 #if PTTYPE =3D=3D 64 --=20 2.39.2 From nobody Sat Sep 13 15:03:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EC4EC7619A for ; Wed, 22 Mar 2023 01:34:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229983AbjCVBej (ORCPT ); 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[2003:f6:af34:4e00:7f5e:5982:a136:b54e]) by smtp.gmail.com with ESMTPSA id w11-20020a1709067c8b00b009231714b3d4sm6356260ejo.151.2023.03.21.18.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 18:34:28 -0700 (PDT) From: Mathias Krause To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Paolo Bonzini , Mathias Krause Subject: [PATCH v4 2/6] KVM: x86: Do not unload MMU roots when only toggling CR0.WP with TDP enabled Date: Wed, 22 Mar 2023 02:37:27 +0100 Message-Id: <20230322013731.102955-3-minipli@grsecurity.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322013731.102955-1-minipli@grsecurity.net> References: <20230322013731.102955-1-minipli@grsecurity.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is no need to unload the MMU roots with TDP enabled when only CR0.WP has changed -- the paging structures are still valid, only the permission bitmap needs to be updated. One heavy user of toggling CR0.WP is grsecurity's KERNEXEC feature to implement kernel W^X. The optimization brings a huge performance gain for this case as the following micro-benchmark running 'ssdd 10 50000' from rt-tests[1] on a grsecurity L1 VM shows (runtime in seconds, lower is better): legacy TDP shadow kvm-x86/next@d8708b 8.43s 9.45s 70.3s +patch 5.39s 5.63s 70.2s For legacy MMU this is ~36% faster, for TTP MMU even ~40% faster. Also TDP and legacy MMU now both have a similar runtime which vanishes the need to disable TDP MMU for grsecurity. Shadow MMU sees no measurable difference and is still slow, as expected. [1] https://git.kernel.org/pub/scm/utils/rt-tests/rt-tests.git Co-developed-by: Sean Christopherson Signed-off-by: Mathias Krause --- arch/x86/kvm/x86.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 237c483b1230..c6d909778b2c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -906,6 +906,18 @@ EXPORT_SYMBOL_GPL(load_pdptrs); =20 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsign= ed long cr0) { + /* + * CR0.WP is incorporated into the MMU role, but only for non-nested, + * indirect shadow MMUs. If TDP is enabled, the MMU's metadata needs + * to be updated, e.g. so that emulating guest translations does the + * right thing, but there's no need to unload the root as CR0.WP + * doesn't affect SPTEs. + */ + if (tdp_enabled && (cr0 ^ old_cr0) =3D=3D X86_CR0_WP) { + kvm_init_mmu(vcpu); + return; + } + if ((cr0 ^ old_cr0) & X86_CR0_PG) { kvm_clear_async_pf_completion_queue(vcpu); kvm_async_pf_hash_reset(vcpu); --=20 2.39.2 From nobody Sat Sep 13 15:03:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 464F0C74A5B for ; Wed, 22 Mar 2023 01:34:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229846AbjCVBen (ORCPT ); Tue, 21 Mar 2023 21:34:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229672AbjCVBec (ORCPT ); Tue, 21 Mar 2023 21:34:32 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47189521CC for ; Tue, 21 Mar 2023 18:34:31 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id ek18so66973975edb.6 for ; Tue, 21 Mar 2023 18:34:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=grsecurity.net; s=grsec; t=1679448870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xKfWyPdWdSRYOzolgK9AgL1vcMAf7TEF7SLZEQ3lWXY=; b=n43NCSzmVBHNDH1pvKVD3UejAZKe7GdCOXtD9IjVu53D9AoBVfyWszbm25SGWXrMBS gNNQEyrbYCPzPMTSdK3/fNXpCSlYogOcsWkp8CT5gcecpkllLzJdxGIeu98pdRU5HKrC M+pQV9qrY1LrzOODh4Kc58Y+wAjPdbJv+hRZliV/jG1zZxu2Habt3ZK0imwGGehhMvek d7/HAhPiChwz9xz/oH7WsEqxKJe0DIMxoTWy3q8BjyvjmauMYwkigyDGHnOtChcSVJZs 2tIdy1Psh9ZIDTD8ESiix4IYNQj20L/N6gERJWKcWfazGuwHX0KnIgw+CnQG2OJq1VmM /Grg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679448870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xKfWyPdWdSRYOzolgK9AgL1vcMAf7TEF7SLZEQ3lWXY=; b=WzAI6u6HMHJbkzcVk43fQzZKxTOykKAARwblvBuWD+S7yMt20B5cWV+NZl8XKLvS7W h1Eo1TS9TbTFLl6g1NgmD69ezWiKN5yyF6RMFv2AFvE0SRrum3/V2Ad/Nm480L5pZzBX k9z1zpp94fAq2/dJc055KGRdOH6NV4VuzMlhYkaXVo5Byls8mJz0UoaKTQWJQ285lvGy PptQYlhKaFBiHZYSfzB2sJlncgv0X6yuVpyK0SQs7B2x/jiJiMY7LzcDMB3bf8AO9Ooe BV2O2O/XQMJ/fVPB+qqMkXo4JXW6MKB+6FDTAppGhqcuCgwio9mEK2aFVbl1jXmBzs54 CDrw== X-Gm-Message-State: AO0yUKWdxdb4loTTg0qdfKDWBQQ3E85CeQIXOEqq76CoOlFDLXrTolrC LajjSMuI9nvxvZZNE49YgjWx1A== X-Google-Smtp-Source: AK7set9YdsjIstOiO2dDOTaGksvG818z1gQgHdBRTBCbR5Hw2FrIepdu6uYc0tPCILkxyXAh24Lp1w== X-Received: by 2002:a17:906:b084:b0:931:75f5:36db with SMTP id x4-20020a170906b08400b0093175f536dbmr5007473ejy.11.1679448869752; Tue, 21 Mar 2023 18:34:29 -0700 (PDT) Received: from nuc.fritz.box (p200300f6af344e007f5e5982a136b54e.dip0.t-ipconnect.de. [2003:f6:af34:4e00:7f5e:5982:a136:b54e]) by smtp.gmail.com with ESMTPSA id w11-20020a1709067c8b00b009231714b3d4sm6356260ejo.151.2023.03.21.18.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 18:34:29 -0700 (PDT) From: Mathias Krause To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Paolo Bonzini , Mathias Krause Subject: [PATCH v4 3/6] KVM: x86: Ignore CR0.WP toggles in non-paging mode Date: Wed, 22 Mar 2023 02:37:28 +0100 Message-Id: <20230322013731.102955-4-minipli@grsecurity.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322013731.102955-1-minipli@grsecurity.net> References: <20230322013731.102955-1-minipli@grsecurity.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If paging is disabled, there are no permission bits to emulate. Micro-optimize this case to avoid unnecessary work. Suggested-and-co-developed-by: Sean Christopherson Signed-off-by: Mathias Krause --- arch/x86/kvm/x86.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c6d909778b2c..8a66ac7a4878 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -908,14 +908,20 @@ void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned= long old_cr0, unsigned lon { /* * CR0.WP is incorporated into the MMU role, but only for non-nested, - * indirect shadow MMUs. If TDP is enabled, the MMU's metadata needs - * to be updated, e.g. so that emulating guest translations does the - * right thing, but there's no need to unload the root as CR0.WP - * doesn't affect SPTEs. + * indirect shadow MMUs. If paging is disabled, no updates are needed + * as there are no permission bits to emulate. If TDP is enabled, the + * MMU's metadata needs to be updated, e.g. so that emulating guest + * translations does the right thing, but there's no need to unload the + * root as CR0.WP doesn't affect SPTEs. */ - if (tdp_enabled && (cr0 ^ old_cr0) =3D=3D X86_CR0_WP) { - kvm_init_mmu(vcpu); - return; + if ((cr0 ^ old_cr0) =3D=3D X86_CR0_WP) { + if (!(cr0 & X86_CR0_PG)) + return; + + if (tdp_enabled) { + kvm_init_mmu(vcpu); + return; + } } =20 if ((cr0 ^ old_cr0) & X86_CR0_PG) { --=20 2.39.2 From nobody Sat Sep 13 15:03:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69253C6FD1D for ; Wed, 22 Mar 2023 01:34:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229747AbjCVBep (ORCPT ); Tue, 21 Mar 2023 21:34:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229816AbjCVBec (ORCPT ); Tue, 21 Mar 2023 21:34:32 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A2E5580FE for ; Tue, 21 Mar 2023 18:34:31 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id b20so34011789edd.1 for ; Tue, 21 Mar 2023 18:34:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=grsecurity.net; s=grsec; t=1679448870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+bcoTADskNJyZKsi62570ynPgg29dBb9TzGC3hyekEs=; b=MLpGqNNZmG7DyxQDvtV7eW5+R8C/FkHLGWDGr9njxiRu2yKpbwwwo7ilFiycWVwk6k Vc6qq/eVscXPdP2SwvCKrMwOjCd1T+ipt7HWzpEdrPZa/lfYT+GC44+jMGUVSBew9zF7 LcGsS1hIuaDN5Xg2prs5+HV7rn/pciGPD1aa1+T6d6dbnIcwg7+0C0mJthqnvrZqCQoa NBkLfft4nEz2sq0jfByEF40NYtBVoVUBDzCtitnEsyTxRtJ1sMRAMdCLDf4xL+ofinyR FYUaHnZO0ZE+8R9KLf/S4R3IC6NWZHF82AwwFih2fn5ue3scB8o236eub8PJWX0/Keu4 b1vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679448870; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+bcoTADskNJyZKsi62570ynPgg29dBb9TzGC3hyekEs=; b=ClGIcO15ipSMZYm0hkniEkOzrE5LXWOEzawahaqEjq0xLcpKFB+c/Lx4S2HavTnliP vFoXFTCmz6WCKZCrPvW3E8u13tw6MYCkizm6UykuBjf7XSpv9wuqr5i+FbNCqhOdAoIi UC8UUoSu+3Nnw29Ozn5dP0GWQnasYPeNU4SrxwtdJTacCWnHtfcSxqw39FaR7fIzzPg8 z2KjlFLRJaowWVJ4wz0fM2TTXLVjJhLDOxI0kxfWiq1eBbLpgEMcv94+CAjIumllRRN+ ha/oLRNAfzVGTvS46iBclY2S1vZvHx77vcZYEUqQ8VIZcPHXqWkapbWt649HY5KpUarp 9O6A== X-Gm-Message-State: AO0yUKUSAdC1fdVzs9gKTGDqiS5Xy7g9StxtNfNht2EswyJN5lwupV9h IZgxpNOGWVsMRsnTH2obXzkNZdQARzNIk6fBdeQ= X-Google-Smtp-Source: AK7set+7P7kfhQIf8H6NYtsYAeq8bpUEGtxWhSFjtGgbKdd25uEBAjLIb0prRt65smuru+dZHQ4SbQ== X-Received: by 2002:a17:907:2da0:b0:939:ad91:adf5 with SMTP id gt32-20020a1709072da000b00939ad91adf5mr6663206ejc.25.1679448870699; Tue, 21 Mar 2023 18:34:30 -0700 (PDT) Received: from nuc.fritz.box (p200300f6af344e007f5e5982a136b54e.dip0.t-ipconnect.de. [2003:f6:af34:4e00:7f5e:5982:a136:b54e]) by smtp.gmail.com with ESMTPSA id w11-20020a1709067c8b00b009231714b3d4sm6356260ejo.151.2023.03.21.18.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 18:34:30 -0700 (PDT) From: Mathias Krause To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Paolo Bonzini , Mathias Krause Subject: [PATCH v4 4/6] KVM: x86: Make use of kvm_read_cr*_bits() when testing bits Date: Wed, 22 Mar 2023 02:37:29 +0100 Message-Id: <20230322013731.102955-5-minipli@grsecurity.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322013731.102955-1-minipli@grsecurity.net> References: <20230322013731.102955-1-minipli@grsecurity.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Make use of the kvm_read_cr{0,4}_bits() helper functions when we only want to know the state of certain bits instead of the whole register. This not only makes the intent cleaner, it also avoids a potential VMREAD in case the tested bits aren't guest owned. Signed-off-by: Mathias Krause --- arch/x86/kvm/pmu.c | 4 ++-- arch/x86/kvm/vmx/vmx.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 612e6c70ce2e..f4aa170b5b97 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -540,9 +540,9 @@ int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, = u64 *data) if (!pmc) return 1; =20 - if (!(kvm_read_cr4(vcpu) & X86_CR4_PCE) && + if (!(kvm_read_cr4_bits(vcpu, X86_CR4_PCE)) && (static_call(kvm_x86_get_cpl)(vcpu) !=3D 0) && - (kvm_read_cr0(vcpu) & X86_CR0_PE)) + (kvm_read_cr0_bits(vcpu, X86_CR0_PE))) return 1; =20 *data =3D pmc_read_counter(pmc) & mask; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index d7bf14abdba1..8fc1a0c7856f 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -5517,7 +5517,7 @@ static int handle_cr(struct kvm_vcpu *vcpu) break; case 3: /* lmsw */ val =3D (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; - trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); + trace_kvm_cr_write(0, (kvm_read_cr0_bits(vcpu, ~0xful) | val)); kvm_lmsw(vcpu, val); =20 return kvm_skip_emulated_instruction(vcpu); @@ -7575,7 +7575,7 @@ static u8 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_= t gfn, bool is_mmio) if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) return (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT) | VMX_EPT_IPAT_BIT; =20 - if (kvm_read_cr0(vcpu) & X86_CR0_CD) { + if (kvm_read_cr0_bits(vcpu, X86_CR0_CD)) { if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) cache =3D MTRR_TYPE_WRBACK; else --=20 2.39.2 From nobody Sat Sep 13 15:03:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5E61C6FD20 for ; Wed, 22 Mar 2023 01:34:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230035AbjCVBes (ORCPT ); Tue, 21 Mar 2023 21:34:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229884AbjCVBee (ORCPT ); Tue, 21 Mar 2023 21:34:34 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 025AD509A8 for ; Tue, 21 Mar 2023 18:34:33 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id w9so66998342edc.3 for ; Tue, 21 Mar 2023 18:34:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=grsecurity.net; s=grsec; t=1679448871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9S6DLSaz+uk2ZH/3jWZtx5Az5bSp7as8qYLxRe1iiAg=; b=wJWLjVUhjUTxSKGzugStwodUsPdXdHnfCS4e4erp/ANgNbFHTkXoCdvfKJjUzgUosB uAkN/6nuradReBSnnjR2LZX0wuZPJuAqzK9UqJEWrwgIiiC3DSmL7kfZw8V7cXg9wxzu LqB8kWeBotwel/McwqJs6yCo7ALREpf/bLi/JhQ4wdOGZ2dYt92KOeNR6XiSBsEywqUd t4mPjoPpG1LfJR7GEbQvA/iHLx5wKIPzfxg2JOph/jglkZq7k6Ye3i00OjHrCcOkoGVX fQgdwleihe5KNGnxPVbvkx2/phajSzfLRJypAH6wtkOa32STmPdy7B6UGKyjwoL5AMzo z1NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679448871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9S6DLSaz+uk2ZH/3jWZtx5Az5bSp7as8qYLxRe1iiAg=; b=Z4P5/BG0NBqsg/DXN/xYw0aEhMHIYw7Bug2qB2UTusAix4N2LmD+Dll+RLbKLiD78/ EszauauNXE0lzX1ss/YXuCKfNUroWKLIciVsK6sErJfmwXturT6QvWaxWJ20bFAgQQEP nVJem+fjRI4cXzNAH8arykmUTgdWdxCVgdk9isP3QIjEovUteTfRXr/af7Udhvpc3AOy I0yrJbjOkGPNBs9jB5QU08njtke4abfvf4ktXu2rY05kwV4LBwaOjMn8aEhncylYEjum HyqoQwuytLEE31oSnh1u7Ao4MxaOodKuVJWAboFYeMh0Cw0qv/v/zLAvSF0Q3M0WOOHp pxlw== X-Gm-Message-State: AO0yUKWdSQTUOR2yj2kiMijTf35VvPaVUgJBdu+gCDLQNGqapznOYHsg hSCQ4B66l3Nq2WO5dJSwj2WZZreCeAnYlBwy5B8= X-Google-Smtp-Source: AK7set8K6fX9IVsxbATaDWD8G8s3XSQPFJHhQGwToQdLSsGXRRK/FSrR6e9Kxv9zZqIBMgksdY6NqA== X-Received: by 2002:a17:906:5a8f:b0:931:41af:8ecb with SMTP id l15-20020a1709065a8f00b0093141af8ecbmr4848403ejq.49.1679448871605; Tue, 21 Mar 2023 18:34:31 -0700 (PDT) Received: from nuc.fritz.box (p200300f6af344e007f5e5982a136b54e.dip0.t-ipconnect.de. [2003:f6:af34:4e00:7f5e:5982:a136:b54e]) by smtp.gmail.com with ESMTPSA id w11-20020a1709067c8b00b009231714b3d4sm6356260ejo.151.2023.03.21.18.34.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 18:34:31 -0700 (PDT) From: Mathias Krause To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Paolo Bonzini , Mathias Krause Subject: [PATCH v4 5/6] KVM: x86/mmu: Fix comment typo Date: Wed, 22 Mar 2023 02:37:30 +0100 Message-Id: <20230322013731.102955-6-minipli@grsecurity.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322013731.102955-1-minipli@grsecurity.net> References: <20230322013731.102955-1-minipli@grsecurity.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix a small comment typo in make_spte(). Signed-off-by: Mathias Krause --- arch/x86/kvm/mmu/spte.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c index c15bfca3ed15..cf2c6426a6fc 100644 --- a/arch/x86/kvm/mmu/spte.c +++ b/arch/x86/kvm/mmu/spte.c @@ -164,7 +164,7 @@ bool make_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_pa= ge *sp, /* * For simplicity, enforce the NX huge page mitigation even if not * strictly necessary. KVM could ignore the mitigation if paging is - * disabled in the guest, as the guest doesn't have an page tables to + * disabled in the guest, as the guest doesn't have any page tables to * abuse. But to safely ignore the mitigation, KVM would have to * ensure a new MMU is loaded (or all shadow pages zapped) when CR0.PG * is toggled on, and that's a net negative for performance when TDP is --=20 2.39.2 From nobody Sat Sep 13 15:03:11 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DEE6C6FD1D for ; Wed, 22 Mar 2023 01:34:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230146AbjCVBew (ORCPT ); Tue, 21 Mar 2023 21:34:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229876AbjCVBee (ORCPT ); Tue, 21 Mar 2023 21:34:34 -0400 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9410497D7 for ; Tue, 21 Mar 2023 18:34:32 -0700 (PDT) Received: by mail-ed1-x531.google.com with SMTP id ek18so66974266edb.6 for ; Tue, 21 Mar 2023 18:34:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=grsecurity.net; s=grsec; t=1679448872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=61LlI0wVrzyKbUKk1uZrrjDNEa+G+M4L4TNEr5FBml0=; b=uH52rgmzsnuWeB0VO7aOqkV8sqiJNKbZQAh4B5wn86LpfCG/SHlUKSf/Eae+YYUSq5 zyvPtQdQbV2tGzeyNMDnLFslNbRydJ3Qp+O9Hnm8vDktBjV5e49KoZORlHdOO05T6QBi 4FVXnALNSY2VDGvUtYgasT1LhDxOO07rXdDdAQLwpidkY6Ez1BWfPPVG6cg3EWIp0ta9 JWSSojqVHBgYWBOsFfHaqZ3pe6YxCfqTBwTiE87wsB8NiPcnTseyVaztW+X8FfDuOLK0 Bnlm87dMK2bCVHw54utaEFvb1RqMu8na571n10CMPi+IEo6lZXekBCa+ee4allBJtebC MXVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679448872; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=61LlI0wVrzyKbUKk1uZrrjDNEa+G+M4L4TNEr5FBml0=; b=l9sRZd4nGSQAadwUgR0FW02wxqb5ivLjf2JZ5kaEe18hKEJTUKfCfbTCPYLhmW0r10 mfSPds2gJeejQj2Z4ss8zJJkFlMVgFRXwKyNvOVtTwJ1S4UhpmT4I46bRncY1w5W/9g/ aDwzQ3oQdB3K6sU7lUzCvaIEi/xaNsT/gNdzSzwQtsuzO4NSHYeZTcYPcRrc8yjsw1mc oav4Q7/HmAHo7XQrXngXsCnm0eu8PjLtKsmYgrAdUnCO24Moc4QLPPDrh73OJSAS66ec AgpEVRnYnuiGFMMR3wgStrCINvWsdR1qioAGu1u2fYJn7DiGkqs9Ak4uwFTClaheKds1 0FPA== X-Gm-Message-State: AO0yUKVLiIYhRUjg7dX3mC86pVsQ1V7qb4piC69OuLRgpn95g5l7ev3C 3meREf7CmIFWPX12ue93+1Ix7w== X-Google-Smtp-Source: AK7set+dnUf8hf0VCL6Kf3L+V9cFUvDBubdmyWb8DP97ojj1fpAZIQ0UCHlhdYNf8Ry/GDl5UG4HsQ== X-Received: by 2002:a17:906:9154:b0:930:bcee:eed with SMTP id y20-20020a170906915400b00930bcee0eedmr5088715ejw.9.1679448872523; Tue, 21 Mar 2023 18:34:32 -0700 (PDT) Received: from nuc.fritz.box (p200300f6af344e007f5e5982a136b54e.dip0.t-ipconnect.de. [2003:f6:af34:4e00:7f5e:5982:a136:b54e]) by smtp.gmail.com with ESMTPSA id w11-20020a1709067c8b00b009231714b3d4sm6356260ejo.151.2023.03.21.18.34.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 18:34:32 -0700 (PDT) From: Mathias Krause To: kvm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Sean Christopherson , Paolo Bonzini , Mathias Krause Subject: [PATCH v4 6/6] KVM: VMX: Make CR0.WP a guest owned bit Date: Wed, 22 Mar 2023 02:37:31 +0100 Message-Id: <20230322013731.102955-7-minipli@grsecurity.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322013731.102955-1-minipli@grsecurity.net> References: <20230322013731.102955-1-minipli@grsecurity.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Guests like grsecurity that make heavy use of CR0.WP to implement kernel level W^X will suffer from the implied VMEXITs. With EPT there is no need to intercept a guest change of CR0.WP, so simply make it a guest owned bit if we can do so. This implies that a read of a guest's CR0.WP bit might need a VMREAD. However, the only potentially affected user seems to be kvm_init_mmu() which is a heavy operation to begin with. But also most callers already cache the full value of CR0 anyway, so no additional VMREAD is needed. The only exception is nested_vmx_load_cr3(). This change is VMX-specific, as SVM has no such fine grained control register intercept control. Suggested-and-co-developed-by: Sean Christopherson Signed-off-by: Mathias Krause --- arch/x86/kvm/kvm_cache_regs.h | 2 +- arch/x86/kvm/vmx/nested.c | 4 ++-- arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/kvm/vmx/vmx.h | 18 ++++++++++++++++++ 4 files changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h index 4c91f626c058..e50d353b5c1c 100644 --- a/arch/x86/kvm/kvm_cache_regs.h +++ b/arch/x86/kvm/kvm_cache_regs.h @@ -4,7 +4,7 @@ =20 #include =20 -#define KVM_POSSIBLE_CR0_GUEST_BITS X86_CR0_TS +#define KVM_POSSIBLE_CR0_GUEST_BITS (X86_CR0_TS | X86_CR0_WP) #define KVM_POSSIBLE_CR4_GUEST_BITS \ (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ | X86_CR4_OSXMMEXCPT | X86_CR4_PGE | X86_CR4_TSD | X86_CR4_FSGSBASE) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index f63b28f46a71..61d940fc91ba 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -4481,7 +4481,7 @@ static void load_vmcs12_host_state(struct kvm_vcpu *v= cpu, * CR0_GUEST_HOST_MASK is already set in the original vmcs01 * (KVM doesn't change it); */ - vcpu->arch.cr0_guest_owned_bits =3D KVM_POSSIBLE_CR0_GUEST_BITS; + vcpu->arch.cr0_guest_owned_bits =3D vmx_l1_guest_owned_cr0_bits(); vmx_set_cr0(vcpu, vmcs12->host_cr0); =20 /* Same as above - no reason to call set_cr4_guest_host_mask(). */ @@ -4632,7 +4632,7 @@ static void nested_vmx_restore_host_state(struct kvm_= vcpu *vcpu) */ vmx_set_efer(vcpu, nested_vmx_get_vmcs01_guest_efer(vmx)); =20 - vcpu->arch.cr0_guest_owned_bits =3D KVM_POSSIBLE_CR0_GUEST_BITS; + vcpu->arch.cr0_guest_owned_bits =3D vmx_l1_guest_owned_cr0_bits(); vmx_set_cr0(vcpu, vmcs_readl(CR0_READ_SHADOW)); =20 vcpu->arch.cr4_guest_owned_bits =3D ~vmcs_readl(CR4_GUEST_HOST_MASK); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 8fc1a0c7856f..e501f6864a72 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4790,7 +4790,7 @@ static void init_vmcs(struct vcpu_vmx *vmx) /* 22.2.1, 20.8.1 */ vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); =20 - vmx->vcpu.arch.cr0_guest_owned_bits =3D KVM_POSSIBLE_CR0_GUEST_BITS; + vmx->vcpu.arch.cr0_guest_owned_bits =3D vmx_l1_guest_owned_cr0_bits(); vmcs_writel(CR0_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr0_guest_owned_bits); =20 set_cr4_guest_host_mask(vmx); diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 2acdc54bc34b..423e9d3c9c40 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -640,6 +640,24 @@ BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_= CONTROL, 64) (1 << VCPU_EXREG_EXIT_INFO_1) | \ (1 << VCPU_EXREG_EXIT_INFO_2)) =20 +static inline unsigned long vmx_l1_guest_owned_cr0_bits(void) +{ + unsigned long bits =3D KVM_POSSIBLE_CR0_GUEST_BITS; + + /* + * CR0.WP needs to be intercepted when KVM is shadowing legacy paging + * in order to construct shadow PTEs with the correct protections. + * Note! CR0.WP technically can be passed through to the guest if + * paging is disabled, but checking CR0.PG would generate a cyclical + * dependency of sorts due to forcing the caller to ensure CR0 holds + * the correct value prior to determining which CR0 bits can be owned + * by L1. Keep it simple and limit the optimization to EPT. + */ + if (!enable_ept) + bits &=3D ~X86_CR0_WP; + return bits; +} + static __always_inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm) { return container_of(kvm, struct kvm_vmx, kvm); --=20 2.39.2