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[79.146.124.255]) by smtp.gmail.com with ESMTPSA id b13-20020adff90d000000b002c54c92e125sm12107693wrr.46.2023.03.21.13.10.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 13:10:26 -0700 (PDT) From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de, f.fainelli@gmail.com, jonas.gorski@gmail.com, william.zhang@broadcom.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= , Rob Herring Subject: [PATCH v3 1/4] dt-bindings: clk: add BCM63268 timer clock definitions Date: Tue, 21 Mar 2023 21:10:19 +0100 Message-Id: <20230321201022.1052743-2-noltari@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230321201022.1052743-1-noltari@gmail.com> References: <20210315122605.28437-1-noltari@gmail.com> <20230321201022.1052743-1-noltari@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add missing timer clock definitions for BCM63268. Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas Acked-by: Rob Herring --- v3: no changes v2: change commit title, as suggested by Stephen Boyd include/dt-bindings/clock/bcm63268-clock.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/dt-bindings/clock/bcm63268-clock.h b/include/dt-bindin= gs/clock/bcm63268-clock.h index da23e691d359..dea8adc8510e 100644 --- a/include/dt-bindings/clock/bcm63268-clock.h +++ b/include/dt-bindings/clock/bcm63268-clock.h @@ -27,4 +27,17 @@ #define BCM63268_CLK_TBUS 27 #define BCM63268_CLK_ROBOSW250 31 =20 +#define BCM63268_TCLK_EPHY1 0 +#define BCM63268_TCLK_EPHY2 1 +#define BCM63268_TCLK_EPHY3 2 +#define BCM63268_TCLK_GPHY1 3 +#define BCM63268_TCLK_DSL 4 +#define BCM63268_TCLK_WAKEON_EPHY 6 +#define BCM63268_TCLK_WAKEON_DSL 7 +#define BCM63268_TCLK_FAP1 11 +#define BCM63268_TCLK_FAP2 15 +#define BCM63268_TCLK_UTO_50 16 +#define BCM63268_TCLK_UTO_EXTIN 17 +#define BCM63268_TCLK_USB_REF 18 + #endif /* __DT_BINDINGS_CLOCK_BCM63268_H */ --=20 2.30.2 From nobody Sun Feb 8 02:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CA12C6FD20 for ; Tue, 21 Mar 2023 20:10:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230128AbjCUUKi (ORCPT ); Tue, 21 Mar 2023 16:10:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230182AbjCUUKc (ORCPT ); Tue, 21 Mar 2023 16:10:32 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9BD42278A; Tue, 21 Mar 2023 13:10:29 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id e18so3408779wra.9; Tue, 21 Mar 2023 13:10:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679429428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=csPGK0TWyrblGaU2v5rP7OM4tMKhIMMOEo+dKBDUlxM=; b=CM+07WX8kDSichtgGVeeC35gI1J2+jom7KiqyMplH29+62EeLgLhf8ecrmM5E5Ffzu xC84rkOA1l67XEA490UBK1eJtGi+A9WFN1wWkXVSZJkCTfg2Pwy7lKhQXEfmKL6I9bWa kL3aH3Wr5iE8LEcuRH9vyaIGDJU0uoGBjamzK1JXbIUs7UezJFKJ9ldm8OkF52G26exl MwJEPwU1S04RLnlB04oOi2dS7x+lJ6siH6IsqrRJV86RmdAzfdcZ4dogx5hPsP0tcWyZ FxWkgU4pPX8kLCMjzVxNbV3ux4K8znvOShnkXK3e+h21vSHj9XFQfXvuS+2SPcfkNDVO 8khw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679429428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=csPGK0TWyrblGaU2v5rP7OM4tMKhIMMOEo+dKBDUlxM=; b=B5wo7v4RauunIRkfegmaLqneR+7q48hU76s6L18L7ErukAkf8QSrHpVPvYL6zXpL8+ Iptf6guHSOt/ZqF6qdHzGG1TAklaVIrENPEZZHlOTopmkQJIh0Q5TgVJ2kKuNq4f5Vuo /coYFlDP6tuY2/g+C1pX+8wYNhkzX2XppyTDB60K36d/CkbbvPE3xzQEM/s60exqVy7E GMv8bC8/ROSCwuCPrKvBVhovaD3sgYR0407mHr+60+lMca37X7bobeSBjAJuOlW3puD0 BW49MvfBnKsKrR8/m2Bf1aCh/DdfAsBQqOyofUc6ynzLRdaAu2AQCOGYMx+i1r6eujlY h8FQ== X-Gm-Message-State: AO0yUKW1hcN6EML4mdrP6zaE6dghSCqQeSL+xTbWAIjJFbStvAVb/hw9 jD5DGysQ+Dc/5Ozrd/Jgd7A= X-Google-Smtp-Source: AK7set+MlRcBfqCvuCChX8ua/5CwJtIcpB2g6zidWNwnVkcSgsX5Xer1oTxh5C7n5dWO84thLzbuVA== X-Received: by 2002:a5d:590f:0:b0:2ce:50bb:dd11 with SMTP id v15-20020a5d590f000000b002ce50bbdd11mr3098755wrd.27.1679429428203; Tue, 21 Mar 2023 13:10:28 -0700 (PDT) Received: from atlantis.lan (255.red-79-146-124.dynamicip.rima-tde.net. [79.146.124.255]) by smtp.gmail.com with ESMTPSA id b13-20020adff90d000000b002c54c92e125sm12107693wrr.46.2023.03.21.13.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 13:10:27 -0700 (PDT) From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de, f.fainelli@gmail.com, jonas.gorski@gmail.com, william.zhang@broadcom.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= , Rob Herring Subject: [PATCH v3 2/4] dt-bindings: reset: add BCM63268 timer reset definitions Date: Tue, 21 Mar 2023 21:10:20 +0100 Message-Id: <20230321201022.1052743-3-noltari@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230321201022.1052743-1-noltari@gmail.com> References: <20210315122605.28437-1-noltari@gmail.com> <20230321201022.1052743-1-noltari@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add missing timer reset definitions for BCM63268. Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas Acked-by: Rob Herring --- v3: no changes v2: change commit title, as suggested by Stephen Boyd include/dt-bindings/reset/bcm63268-reset.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindin= gs/reset/bcm63268-reset.h index 6a6403a4c2d5..d87a7882782a 100644 --- a/include/dt-bindings/reset/bcm63268-reset.h +++ b/include/dt-bindings/reset/bcm63268-reset.h @@ -23,4 +23,8 @@ #define BCM63268_RST_PCIE_HARD 17 #define BCM63268_RST_GPHY 18 =20 +#define BCM63268_TRST_SW 29 +#define BCM63268_TRST_HW 30 +#define BCM63268_TRST_POR 31 + #endif /* __DT_BINDINGS_RESET_BCM63268_H */ --=20 2.30.2 From nobody Sun Feb 8 02:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 630BDC6FD1D for ; Tue, 21 Mar 2023 20:10:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229663AbjCUUKk (ORCPT ); Tue, 21 Mar 2023 16:10:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230187AbjCUUKd (ORCPT ); Tue, 21 Mar 2023 16:10:33 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C88C4AFDF; Tue, 21 Mar 2023 13:10:31 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id v1so8851189wrv.1; Tue, 21 Mar 2023 13:10:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679429429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fWnw8tQIl1eV2yzunsb3XCftBZMuQrLVFpbCt6WM/74=; b=HlYmfnfQ4BzlqB+bwgyqO8Eq6S/dB+y2NPaaHH+3KiFwsen70eI9ZoNh9PI4f2wZQb kwAPc9K0NHkBvpyXYVDhy4mprsyAgNnFymRSu5Xuwz7x8ujxRC/P1ZthWFQbvz/DyQ58 HuUWE4k8SoEGBC2JFGtt29tpJGtm174HRtwxw63TXJ59cTZciTtbcW392+GszXOZZEtT +I1Fu++oJE+Nuif3gfkJEddZAP5VPN+40QmnAY0Ku+jx930733ArJIM/AO9PtfMQ7Q+4 F1RsdyYtEgs7QDGln4fSwNKgiRB2cvFdnCl2CJ7b1H0kRaOBhJ+SUmPGpKVGIbBKubDJ gNVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679429429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fWnw8tQIl1eV2yzunsb3XCftBZMuQrLVFpbCt6WM/74=; b=3LVqUIiun7UhLSkLYgaKGvfw5/mE02n7v17N8+qiuvCoEyTyKDn+WECU5NSV+/kfra HzFNeSo9Kwj5wBbEPiUHro2qgTGBR7PjYzzRqDvK4UewQzw30TQf0wMsNOhbsPudNkYy 030+J0oD6VBxVT4O/TTQbUMHw62Qb1Ukr8IRsGJWZ6LX0VmohkeUYpeXTFTvAR1RSvn4 CH8oiNKpeKQzA8bmhZxokpkknRFTBZqq2BtN1uJdPgImWtezXNCdjZXWIPOraZu4Sdnw CId9cAIkHzmGfxb+DwFK8b64JG/sAECDVZblwPPRkiusV+ggiRIpUza3DHNiOuU0IbLQ MHFg== X-Gm-Message-State: AO0yUKWkjS0b7HXABsdBHLaI7H8yiMFNEEO2B1H2TURvmnbTGXWyKD0h nXAeHnsLmj9rKX85C6y3HKQ= X-Google-Smtp-Source: AK7set+3DIdHlqhcrd6oqC3P+07f8ehmA/TGtvm6ziiJVvtseHgLBK8KePvtfTfzBO78QBMScqkaog== X-Received: by 2002:adf:ea86:0:b0:2c9:23c4:8f93 with SMTP id s6-20020adfea86000000b002c923c48f93mr3355724wrm.57.1679429429443; Tue, 21 Mar 2023 13:10:29 -0700 (PDT) Received: from atlantis.lan (255.red-79-146-124.dynamicip.rima-tde.net. [79.146.124.255]) by smtp.gmail.com with ESMTPSA id b13-20020adff90d000000b002c54c92e125sm12107693wrr.46.2023.03.21.13.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 13:10:28 -0700 (PDT) From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de, f.fainelli@gmail.com, jonas.gorski@gmail.com, william.zhang@broadcom.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= , Rob Herring Subject: [PATCH v3 3/4] dt-bindings: clock: Add BCM63268 timer binding Date: Tue, 21 Mar 2023 21:10:21 +0100 Message-Id: <20230321201022.1052743-4-noltari@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230321201022.1052743-1-noltari@gmail.com> References: <20210315122605.28437-1-noltari@gmail.com> <20230321201022.1052743-1-noltari@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the Broadcom BCM63268 Clock and Reset controller. Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas Reviewed-by: Rob Herring --- v3: no changes v2: no changes .../clock/brcm,bcm63268-timer-clocks.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63268-t= imer-clocks.yaml diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-cl= ocks.yaml b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clo= cks.yaml new file mode 100644 index 000000000000..199818b2fb6d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.ya= ml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings + +maintainers: + - =C3=81lvaro Fern=C3=A1ndez Rojas + +properties: + compatible: + const: brcm,bcm63268-timer-clocks + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + timer_clk: clock-controller@100000ac { + compatible =3D "brcm,bcm63268-timer-clocks"; + reg =3D <0x100000ac 0x4>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.30.2 From nobody Sun Feb 8 02:55:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54404C76195 for ; Tue, 21 Mar 2023 20:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230093AbjCUUKt (ORCPT ); Tue, 21 Mar 2023 16:10:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229676AbjCUUKq (ORCPT ); Tue, 21 Mar 2023 16:10:46 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 576404C6DD; Tue, 21 Mar 2023 13:10:32 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id o11-20020a05600c4fcb00b003eb33ea29a8so10212456wmq.1; Tue, 21 Mar 2023 13:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679429430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=viHWNP8s4BI0z0vZNADv22A48oTfIdBG6AOV5RLn/v4=; b=qFIYQOZgV/KvbBYNrFJElcZIHZZyL/rcBKPBR6Y0+TZOS0MSJntGjGZfrEfoAq/Q7l x7wNZyHwq/Jv8YoWNovlOnCxk7dp0rAY8MmEM8867OAobxPwvenYRQw2k7HwptRQP8x4 3oa93FJNNf2Z62vFYND2iZbITkb53amPthA/HqYxdZ5ePxb3QxJ+mIZQCd4Q1t4nzgdY FFUR3HCHjxbQgZ8FqECn5npnSFcnVmUUBjS9qEeXdSaQohODXZ3FQJya5n3kpQSfqbTc JtIQj7lCFR1/BD63GR9aWpso7uE4puT8l419MqlbAtlQ0DaptGSX/q075Z0iuuIP5CMH m2Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679429430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=viHWNP8s4BI0z0vZNADv22A48oTfIdBG6AOV5RLn/v4=; b=mvxGhkKWDoPd0LtsT3FhhlQZJLzz8ryX3J7GDa+dbiAbebdjkLUV0OYUZbCSS6a6nP 2L6r/+hT5N8VMDuFyIhH5aTn8NcaIRsIMBZkFkuFrJjCeggq2IuOj4jd0U5tUvwkD/s1 ANDyAwNERUYG8YrJVcvA4hFwwdAB0ZbWHQjKb/cIj7dlcQdG3e2N0zid2SdZX20FjafF +258L09EU5gCeF+mmNP5LMnmod8b5fIi/QoLgzcYWLsCs+XP0KP4lElQGSFqYF7n7xs/ HfM1HVu31smpMyQz4NaCY01rJjRBQv89gQLIb8nhTW2tSb44rRV2k/uKAYO9rsjw+au0 95mg== X-Gm-Message-State: AO0yUKXEWQ1p3zWcxHmT+0GMDcIqx8vEwkOEDiQDp+iF0N/vc9s2wn8m BMnw/S+2QXQCRMHnVDbNqRM= X-Google-Smtp-Source: AK7set89DXSzpxj4qBQOvh0zoaFhuNNu8x3PeMw9mxOEUURcPtEzZSTAF7wd5RH1LYXTIHZUgznIDw== X-Received: by 2002:a7b:c5c1:0:b0:3ed:b349:e473 with SMTP id n1-20020a7bc5c1000000b003edb349e473mr3389880wmk.37.1679429430648; Tue, 21 Mar 2023 13:10:30 -0700 (PDT) Received: from atlantis.lan (255.red-79-146-124.dynamicip.rima-tde.net. [79.146.124.255]) by smtp.gmail.com with ESMTPSA id b13-20020adff90d000000b002c54c92e125sm12107693wrr.46.2023.03.21.13.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 13:10:30 -0700 (PDT) From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de, f.fainelli@gmail.com, jonas.gorski@gmail.com, william.zhang@broadcom.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Subject: [PATCH v3 4/4] clk: bcm: Add BCM63268 timer clock and reset driver Date: Tue, 21 Mar 2023 21:10:22 +0100 Message-Id: <20230321201022.1052743-5-noltari@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230321201022.1052743-1-noltari@gmail.com> References: <20210315122605.28437-1-noltari@gmail.com> <20230321201022.1052743-1-noltari@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add driver for BCM63268 timer clock and reset controller. Signed-off-by: =C3=81lvaro Fern=C3=A1ndez Rojas --- v3: add missing include to fix build warning v2: add changes suggested by Stephen Boyd drivers/clk/bcm/Kconfig | 9 ++ drivers/clk/bcm/Makefile | 1 + drivers/clk/bcm/clk-bcm63268-timer.c | 232 +++++++++++++++++++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/clk/bcm/clk-bcm63268-timer.c diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig index 77266afb1c79..a972d763eb77 100644 --- a/drivers/clk/bcm/Kconfig +++ b/drivers/clk/bcm/Kconfig @@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE Enable common clock framework support for Broadcom BCM63xx DSL SoCs based on the MIPS architecture =20 +config CLK_BCM63268_TIMER + bool "Broadcom BCM63268 timer clock and reset support" + depends on BMIPS_GENERIC || COMPILE_TEST + default BMIPS_GENERIC + select RESET_CONTROLLER + help + Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs + based on the MIPS architecture. + config CLK_BCM_KONA bool "Broadcom Kona CCU clock support" depends on ARCH_BCM_MOBILE || COMPILE_TEST diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile index edb66b44cb27..d0b6f4b1fb08 100644 --- a/drivers/clk/bcm/Makefile +++ b/drivers/clk/bcm/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CLK_BCM_63XX) +=3D clk-bcm63xx.o obj-$(CONFIG_CLK_BCM_63XX_GATE) +=3D clk-bcm63xx-gate.o +obj-$(CONFIG_CLK_BCM63268_TIMER) +=3D clk-bcm63268-timer.o obj-$(CONFIG_CLK_BCM_KONA) +=3D clk-kona.o obj-$(CONFIG_CLK_BCM_KONA) +=3D clk-kona-setup.o obj-$(CONFIG_CLK_BCM_KONA) +=3D clk-bcm281xx.o diff --git a/drivers/clk/bcm/clk-bcm63268-timer.c b/drivers/clk/bcm/clk-bcm= 63268-timer.c new file mode 100644 index 000000000000..6a1fdd193cb5 --- /dev/null +++ b/drivers/clk/bcm/clk-bcm63268-timer.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * BCM63268 Timer Clock and Reset Controller Driver + * + * Copyright (C) 2023 =C3=81lvaro Fern=C3=A1ndez Rojas + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define BCM63268_TIMER_RESET_SLEEP_MIN_US 10000 +#define BCM63268_TIMER_RESET_SLEEP_MAX_US 20000 + +struct bcm63268_tclkrst_hw { + void __iomem *regs; + spinlock_t lock; + + struct reset_controller_dev rcdev; + struct clk_hw_onecell_data data; +}; + +struct bcm63268_tclk_table_entry { + const char * const name; + u8 bit; +}; + +static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] =3D { + { + .name =3D "ephy1", + .bit =3D BCM63268_TCLK_EPHY1, + }, { + .name =3D "ephy2", + .bit =3D BCM63268_TCLK_EPHY2, + }, { + .name =3D "ephy3", + .bit =3D BCM63268_TCLK_EPHY3, + }, { + .name =3D "gphy1", + .bit =3D BCM63268_TCLK_GPHY1, + }, { + .name =3D "dsl", + .bit =3D BCM63268_TCLK_DSL, + }, { + .name =3D "wakeon_ephy", + .bit =3D BCM63268_TCLK_WAKEON_EPHY, + }, { + .name =3D "wakeon_dsl", + .bit =3D BCM63268_TCLK_WAKEON_DSL, + }, { + .name =3D "fap1_pll", + .bit =3D BCM63268_TCLK_FAP1, + }, { + .name =3D "fap2_pll", + .bit =3D BCM63268_TCLK_FAP2, + }, { + .name =3D "uto_50", + .bit =3D BCM63268_TCLK_UTO_50, + }, { + .name =3D "uto_extin", + .bit =3D BCM63268_TCLK_UTO_EXTIN, + }, { + .name =3D "usb_ref", + .bit =3D BCM63268_TCLK_USB_REF, + }, { + /* sentinel */ + } +}; + +static inline struct bcm63268_tclkrst_hw * +to_bcm63268_timer_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev); +} + +static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct bcm63268_tclkrst_hw *reset =3D to_bcm63268_timer_reset(rcdev); + unsigned long flags; + uint32_t val; + + spin_lock_irqsave(&reset->lock, flags); + val =3D __raw_readl(reset->regs); + if (assert) + val &=3D ~BIT(id); + else + val |=3D BIT(id); + __raw_writel(val, reset->regs); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return bcm63268_timer_reset_update(rcdev, id, true); +} + +static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcde= v, + unsigned long id) +{ + return bcm63268_timer_reset_update(rcdev, id, false); +} + +static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + bcm63268_timer_reset_update(rcdev, id, true); + usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US, + BCM63268_TIMER_RESET_SLEEP_MAX_US); + + bcm63268_timer_reset_update(rcdev, id, false); + /* + * Ensure component is taken out reset state by sleeping also after + * deasserting the reset. Otherwise, the component may not be ready + * for operation. + */ + usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US, + BCM63268_TIMER_RESET_SLEEP_MAX_US); + + return 0; +} + +static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct bcm63268_tclkrst_hw *reset =3D to_bcm63268_timer_reset(rcdev); + + return !(__raw_readl(reset->regs) & BIT(id)); +} + +static struct reset_control_ops bcm63268_timer_reset_ops =3D { + .assert =3D bcm63268_timer_reset_assert, + .deassert =3D bcm63268_timer_reset_deassert, + .reset =3D bcm63268_timer_reset_reset, + .status =3D bcm63268_timer_reset_status, +}; + +static int bcm63268_tclk_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + const struct bcm63268_tclk_table_entry *entry, *table; + struct bcm63268_tclkrst_hw *hw; + struct clk_hw *clk; + u8 maxbit =3D 0; + int i, ret; + + table =3D of_device_get_match_data(dev); + if (!table) + return -EINVAL; + + for (entry =3D table; entry->name; entry++) + maxbit =3D max(maxbit, entry->bit); + maxbit++; + + hw =3D devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit), + GFP_KERNEL); + if (!hw) + return -ENOMEM; + + platform_set_drvdata(pdev, hw); + + spin_lock_init(&hw->lock); + + hw->data.num =3D maxbit; + for (i =3D 0; i < maxbit; i++) + hw->data.hws[i] =3D ERR_PTR(-ENODEV); + + hw->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hw->regs)) + return PTR_ERR(hw->regs); + + for (entry =3D table; entry->name; entry++) { + clk =3D clk_hw_register_gate(dev, entry->name, NULL, 0, + hw->regs, entry->bit, + CLK_GATE_BIG_ENDIAN, &hw->lock); + if (IS_ERR(clk)) { + ret =3D PTR_ERR(clk); + goto out_err; + } + + hw->data.hws[entry->bit] =3D clk; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &hw->data); + if (ret) + return ret; + + hw->rcdev.of_node =3D dev->of_node; + hw->rcdev.ops =3D &bcm63268_timer_reset_ops; + + ret =3D devm_reset_controller_register(dev, &hw->rcdev); + if (ret) + dev_err(dev, "Failed to register reset controller\n"); + + return 0; + +out_err: + for (i =3D 0; i < hw->data.num; i++) { + if (!IS_ERR(hw->data.hws[i])) + clk_hw_unregister_gate(hw->data.hws[i]); + } + + return ret; +} + +static const struct of_device_id bcm63268_tclk_dt_ids[] =3D { + { + .compatible =3D "brcm,bcm63268-timer-clocks", + .data =3D &bcm63268_timer_clocks, + }, { + /* sentinel */ + } +}; + +static struct platform_driver bcm63268_tclk =3D { + .probe =3D bcm63268_tclk_probe, + .driver =3D { + .name =3D "bcm63268-timer-clock", + .of_match_table =3D bcm63268_tclk_dt_ids, + }, +}; +builtin_platform_driver(bcm63268_tclk); --=20 2.30.2