From nobody Sun Feb 8 14:11:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BBC1C74A5B for ; Tue, 21 Mar 2023 08:29:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231261AbjCUI3Z (ORCPT ); Tue, 21 Mar 2023 04:29:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231216AbjCUI2k (ORCPT ); Tue, 21 Mar 2023 04:28:40 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FCF92127; Tue, 21 Mar 2023 01:28:38 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32L8SUTQ124074; Tue, 21 Mar 2023 03:28:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679387310; bh=AL+AQcBC01d6YV7SvnuU5S6rp6sGaVR9UhfilG5W/14=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=v+ohLXBDjsQILb/x4ajW+VTQ1/JelwaFZpOgd0/Lyl3OJGWyAO6e6gKDXySMrFmN0 5uQGFT2Sex47r3Ax/7HLq6EXB/tUXmXvOo6qC8d3fby0vHwdxJ9PYe03vUFBh4wKb+ DczSLU8meLFv6NXEwoFHC4Mhb0jFxMq/wF8KLbfg= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32L8SUaX036166 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Mar 2023 03:28:30 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Mar 2023 03:28:30 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Mar 2023 03:28:30 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32L8STRp063906; Tue, 21 Mar 2023 03:28:30 -0500 From: Vaishnav Achath To: , , , , CC: , , , , , , Subject: [PATCH v3 1/4] arm64: dts: ti: k3-j721e: Add MCSPI nodes Date: Tue, 21 Mar 2023 13:58:24 +0530 Message-ID: <20230321082827.14274-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321082827.14274-1-vaishnav.a@ti.com> References: <20230321082827.14274-1-vaishnav.a@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" J721E has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Co-developed-by: Keerthy Signed-off-by: Keerthy Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V2->V3: * Update commit message to mention internal MCSPI loopback. V1->V2:=20 * Combine main, mcu domain, MCSPI node addition changes to single commit. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index bfa296dce3a3..a90f076776ce 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2328,4 +2328,92 @@ bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + main_spi0: spi@2100000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02100000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 266 1>; + status =3D "disabled"; + }; + + main_spi1: spi@2110000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02110000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 267 1>; + status =3D "disabled"; + }; + + main_spi2: spi@2120000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02120000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 268 1>; + status =3D "disabled"; + }; + + main_spi3: spi@2130000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02130000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 269 1>; + status =3D "disabled"; + }; + + main_spi4: spi@2140000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02140000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 270 1>; + status =3D "disabled"; + }; + + main_spi5: spi@2150000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02150000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 271 1>; + status =3D "disabled"; + }; + + main_spi6: spi@2160000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02160000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 272 1>; + status =3D "disabled"; + }; + + main_spi7: spi@2170000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02170000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 273 1>; + status =3D "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 8ac78034d5d6..24e8125db8c4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -425,4 +425,37 @@ bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + mcu_spi0: spi@40300000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040300000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 274 0>; + status =3D "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040310000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 275 0>; + status =3D "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040320000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 0>; + status =3D "disabled"; + }; }; --=20 2.17.1 From nobody Sun Feb 8 14:11:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90B6BC74A5B for ; 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Tue, 21 Mar 2023 03:28:32 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Mar 2023 03:28:32 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Mar 2023 03:28:32 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32L8SVNg071371; Tue, 21 Mar 2023 03:28:31 -0500 From: Vaishnav Achath To: , , , , CC: , , , , , , Subject: [PATCH v3 2/4] arm64: dts: ti: k3-j7200: Add MCSPI nodes Date: Tue, 21 Mar 2023 13:58:25 +0530 Message-ID: <20230321082827.14274-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321082827.14274-1-vaishnav.a@ti.com> References: <20230321082827.14274-1-vaishnav.a@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" J7200 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath Reviewed-by: Keerthy --- V2->V3: * Add Keerthy's Reviewed-by. * Update commit message to mention internal MCSPI loopback. V1->V2:=20 * Combine main, mcu domain, MCSPI node addition changes to single commit. arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 138381f43ce4..e7ede18e75fa 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -777,6 +777,94 @@ clock-names =3D "gpio"; }; =20 + main_spi0: spi@2100000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02100000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 266 1>; + status =3D "disabled"; + }; + + main_spi1: spi@2110000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02110000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 267 1>; + status =3D "disabled"; + }; + + main_spi2: spi@2120000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02120000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 268 1>; + status =3D "disabled"; + }; + + main_spi3: spi@2130000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02130000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 269 1>; + status =3D "disabled"; + }; + + main_spi4: spi@2140000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02140000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 270 1>; + status =3D "disabled"; + }; + + main_spi5: spi@2150000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02150000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 271 1>; + status =3D "disabled"; + }; + + main_spi6: spi@2160000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02160000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 272 1>; + status =3D "disabled"; + }; + + main_spi7: spi@2170000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02170000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 273 1>; + status =3D "disabled"; + }; + watchdog0: watchdog@2200000 { compatible =3D "ti,j7-rti-wdt"; reg =3D <0x0 0x2200000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index de56a0165bd0..331b4e482e41 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -305,6 +305,39 @@ status =3D "disabled"; }; =20 + mcu_spi0: spi@40300000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040300000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 274 0>; + status =3D "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040310000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 275 0>; + status =3D "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040320000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 276 0>; + status =3D "disabled"; + }; + fss: syscon@47000000 { compatible =3D "syscon", "simple-mfd"; reg =3D <0x00 0x47000000 0x00 0x100>; --=20 2.17.1 From nobody Sun Feb 8 14:11:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAB72C6FD1D for ; Tue, 21 Mar 2023 08:29:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231266AbjCUI3l (ORCPT ); Tue, 21 Mar 2023 04:29:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231222AbjCUI2t (ORCPT ); Tue, 21 Mar 2023 04:28:49 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D7DCB755; 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Tue, 21 Mar 2023 03:28:34 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32L8SXbe083095; Tue, 21 Mar 2023 03:28:33 -0500 From: Vaishnav Achath To: , , , , CC: , , , , , , Subject: [PATCH v3 3/4] arm64: dts: ti: k3-j721s2: Add MCSPI nodes Date: Tue, 21 Mar 2023 13:58:26 +0530 Message-ID: <20230321082827.14274-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321082827.14274-1-vaishnav.a@ti.com> References: <20230321082827.14274-1-vaishnav.a@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" J721S2 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath Reviewed-by: Keerthy --- V2->V3: * Add Keerthy's Reviewed-by. * Update commit message to mention internal MCSPI loopback. V1->V2:=20 * Combine main, mcu domain, MCSPI node addition changes to single commit. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 8915132efcc1..2dd7865f7654 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1014,4 +1014,92 @@ bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + main_spi0: spi@2100000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02100000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 339 1>; + status =3D "disabled"; + }; + + main_spi1: spi@2110000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02110000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 340 1>; + status =3D "disabled"; + }; + + main_spi2: spi@2120000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02120000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 341 1>; + status =3D "disabled"; + }; + + main_spi3: spi@2130000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02130000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 342 1>; + status =3D "disabled"; + }; + + main_spi4: spi@2140000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02140000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 343 1>; + status =3D "disabled"; + }; + + main_spi5: spi@2150000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02150000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 344 1>; + status =3D "disabled"; + }; + + main_spi6: spi@2160000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02160000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 345 1>; + status =3D "disabled"; + }; + + main_spi7: spi@2170000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02170000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 346 1>; + status =3D "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..9e5a8a35a01b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -203,6 +203,39 @@ status =3D "disabled"; }; =20 + mcu_spi0: spi@40300000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040300000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 347 0>; + status =3D "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040310000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 348 0>; + status =3D "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040320000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 349 0>; + status =3D "disabled"; + }; + mcu_navss: bus@28380000{ compatible =3D "simple-mfd"; #address-cells =3D <2>; --=20 2.17.1 From nobody Sun Feb 8 14:11:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39B4DC761A6 for ; Tue, 21 Mar 2023 08:29:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229749AbjCUI3i (ORCPT ); Tue, 21 Mar 2023 04:29:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbjCUI2r (ORCPT ); Tue, 21 Mar 2023 04:28:47 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 359DA3C3C; Tue, 21 Mar 2023 01:28:45 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32L8Sa7j069742; Tue, 21 Mar 2023 03:28:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679387316; bh=fPWWg7+iwrb/0eu92g15O3qnylPqBBWBHeXdc+SXMcE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bqMKMxfUFoGAIGBQ+Z7TzumoCEOXLoyaeY9UlM0uumphhe1/cWRmkuDwPw3aZWRC0 DShIj7UedA8KMQ1ZNObcOqytqXh3bxsylO41TxyQBVAg9g7SS2eBPAtRO2XPtET4Ka qJgw9wpjp+33+H17gcITjBFQMcKjXEM/JZczHkm8= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32L8SapN045180 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 21 Mar 2023 03:28:36 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 21 Mar 2023 03:28:36 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 21 Mar 2023 03:28:35 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32L8SZ9i008172; Tue, 21 Mar 2023 03:28:35 -0500 From: Vaishnav Achath To: , , , , CC: , , , , , , Subject: [PATCH v3 4/4] arm64: dts: ti: k3-j784s4: Add MCSPI nodes Date: Tue, 21 Mar 2023 13:58:27 +0530 Message-ID: <20230321082827.14274-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321082827.14274-1-vaishnav.a@ti.com> References: <20230321082827.14274-1-vaishnav.a@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" J784S4 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath Reviewed-by: Keerthy --- V2->V3: * Add Keerthy's Reviewed-by. V1->V2:=20 * Combine main, mcu domain, MCSPI node addition changes to single commit. arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 80a1b08c51a8..432592ef3bc4 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1005,4 +1005,92 @@ bosch,mram-cfg =3D <0x00 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + main_spi0: spi@2100000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02100000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 376 1>; + status =3D "disabled"; + }; + + main_spi1: spi@2110000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02110000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 377 1>; + status =3D "disabled"; + }; + + main_spi2: spi@2120000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02120000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 378 1>; + status =3D "disabled"; + }; + + main_spi3: spi@2130000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02130000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 379 1>; + status =3D "disabled"; + }; + + main_spi4: spi@2140000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02140000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 380 1>; + status =3D "disabled"; + }; + + main_spi5: spi@2150000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02150000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 381 1>; + status =3D "disabled"; + }; + + main_spi6: spi@2160000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02160000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 382 1>; + status =3D "disabled"; + }; + + main_spi7: spi@2170000 { + compatible =3D "ti,am654-mcspi","ti,omap4-mcspi"; + reg =3D <0x00 0x02170000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 383 1>; + status =3D "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 64bd3dee14aa..f04fcb614cbe 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -204,6 +204,39 @@ status =3D "disabled"; }; =20 + mcu_spi0: spi@40300000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040300000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 384 0>; + status =3D "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040310000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 385 0>; + status =3D "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible =3D "ti,am654-mcspi", "ti,omap4-mcspi"; + reg =3D <0x00 0x040320000 0x00 0x400>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <0>; + power-domains =3D <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 386 0>; + status =3D "disabled"; + }; + mcu_navss: bus@28380000{ compatible =3D "simple-bus"; #address-cells =3D <2>; --=20 2.17.1