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Tue, 21 Mar 2023 00:35:18 -0500 From: Harsha Harsha To: , , , , , CC: , , Harsha Harsha , Dhaval Shah Subject: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP RSA API for RSA encrypt/decrypt operation Date: Tue, 21 Mar 2023 11:04:44 +0530 Message-ID: <20230321053446.4303-3-harsha.harsha@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230321053446.4303-1-harsha.harsha@amd.com> References: <20230321053446.4303-1-harsha.harsha@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E64C:EE_|CY8PR12MB9034:EE_ X-MS-Office365-Filtering-Correlation-Id: 6a27238f-3e0a-40c8-90c3-08db29ce14a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +Cm9wWpJMcJstTzcY3MoCJP9Br6GdlpCm0JMlpcEexSlNZS581tx2+jIRNxLmmF24bNDpgUBI/mVNn0nf6vY3V1xWAOSRtUsL3gNGiqqP7w6sEpJEiikrAh1q6LF/RoclUL3dKkjWt/2KMhaDI4hAvrQYr8Ve79wOwKeNU0V9pAT/Mf8LN33DXHQLayd4Es17MJvsIlsE8DScgr53P9Txx5ZjOM566QRH+pUR87DJ6HFxTW3ua6ejBATtnUFEx9g96Ec2+FXZ5CKEUaqGn928aJuGwt1g3uuQTQ7qCKESFR1R0+kXeyq4imHMDUIEMD2XoQdath3u+PoeYHOJMcQLn3GgA6k+B1Ao09+obhfaZtLzrAxvaztlzgn+OYwncYdc35+pi13zaWjs8pts8t39PzdTxnIvCBm/9DBoiY5+dVbQzu5Tr9irlyAnHg9BliXGRau8d/4uI+3c+8LjoVsbM0RTgV4cpUgE2r0drqDYXxZOmC57u5erJmTHzqjF2/Zm4CZ4HwKzmU13hFZ7rMm0LwT7AZUY+fXIxcMYeYiPTZyGD9uRKDXolm4Q2km0C5fo5vn4svwXaw51QxTvRpcrg7E2/8+0hqGDcVc2mZu8y8hdrInz205BR3etCV/SLzRid1cGnCTGdtJeDg699HHrmHYOoL4pjEZCo2/U1bvRk/QsatAOreWqZfxT4B47koMYI6wstxvjLaR8CYkNPLkOacj21UHF48xnO1KXFj5LMwVcrpd9oVFtRv7rSUjBNC+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199018)(36840700001)(46966006)(40470700004)(110136005)(336012)(1076003)(2616005)(26005)(47076005)(426003)(6666004)(8676002)(4326008)(316002)(83380400001)(186003)(70206006)(70586007)(54906003)(478600001)(8936002)(5660300002)(82740400003)(44832011)(81166007)(2906002)(41300700001)(36860700001)(356005)(82310400005)(86362001)(36756003)(40480700001)(40460700003)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 05:35:28.8606 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a27238f-3e0a-40c8-90c3-08db29ce14a4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E64C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB9034 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add zynqmp_pm_rsa API in the ZynqMP firmware to encrypt and decrypt the datai using RSA hardware engine for ZynqMP. Signed-off-by: Harsha Harsha Co-developed-by: Dhaval Shah Signed-off-by: Dhaval Shah --- drivers/firmware/xilinx/zynqmp.c | 21 +++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zyn= qmp.c index 10ae42a2ae22..d6f73823bab4 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1426,6 +1426,27 @@ int zynqmp_pm_sha_hash(const u64 address, const u32 = size, const u32 flags) } EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash); =20 +/** + * zynqmp_pm_rsa - Access RSA hardware to encrypt/decrypt the data with RS= A. + * @address: Address of the data + * @size: Size of the data. + * @flags: + * BIT(0) - Encryption/Decryption + * 0 - RSA decryption with private key + * 1 - RSA encryption with public key. + * + * Return: Returns status, either success or error code. + */ +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags) +{ + u32 lower_32_bits =3D lower_32_bits(address); + u32 upper_32_bits =3D upper_32_bits(address); + + return zynqmp_pm_invoke_fn(PM_SECURE_RSA, upper_32_bits, lower_32_bits, + size, flags, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_rsa); + /** * zynqmp_pm_register_notifier() - PM API for register a subsystem * to be notified about specific diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/= xlnx-zynqmp.h index cd5acfa29cbc..8666b0c3cd66 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -117,6 +117,7 @@ enum pm_api_id { PM_FPGA_GET_STATUS =3D 23, PM_GET_CHIPID =3D 24, PM_SECURE_SHA =3D 26, + PM_SECURE_RSA =3D 27, PM_PINCTRL_REQUEST =3D 28, PM_PINCTRL_RELEASE =3D 29, PM_PINCTRL_GET_FUNCTION =3D 30, @@ -542,6 +543,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32= capabilities, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags= ); int zynqmp_pm_fpga_get_status(u32 *value); int zynqmp_pm_write_ggs(u32 index, u32 value); @@ -744,6 +746,12 @@ static inline int zynqmp_pm_sha_hash(const u64 address= , const u32 size, return -ENODEV; } =20 +static inline int zynqmp_pm_rsa(const u64 address, const u32 size, + const u32 flags) +{ + return -ENODEV; +} + static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { --=20 2.36.1