From nobody Tue Feb 10 02:43:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86D8DC6FD1C for ; Wed, 22 Mar 2023 12:40:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230390AbjCVMkN (ORCPT ); Wed, 22 Mar 2023 08:40:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230318AbjCVMkG (ORCPT ); Wed, 22 Mar 2023 08:40:06 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5627B4D603; Wed, 22 Mar 2023 05:40:04 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32MCdpeH061268; Wed, 22 Mar 2023 07:39:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679488791; bh=6H/hPJGtJSUE1B5vlPy/QUFC8opB7huwtt/IQA640GE=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=Z0WuMvR0bURGyP3hvFOSBlxs8EjwjV/Q7qen7cFPhPTfWtlEOeyq5ckOr8KQy5awX FzyjkLV8P2HGEBFp1DnCnHZF61SusV6GTnfUZWxBIFOfJ8idnAtVFrd0fh/BL+ejbH WG7SKuGrwPy07uqGLMvO4GJBnF0b8KFF7QBqeYzU= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32MCdpIA066300 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 Mar 2023 07:39:51 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 22 Mar 2023 07:39:51 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 22 Mar 2023 07:39:51 -0500 Received: from [127.0.1.1] (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32MCdcna098356; Wed, 22 Mar 2023 07:39:48 -0500 From: Vignesh Raghavendra Date: Wed, 22 Mar 2023 18:09:22 +0530 Subject: [PATCH v2 3/3] arm64: ti: dts: Add support for AM62x LP SK MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20230321-am62-lp-sk-v2-3-0a56e1694804@ti.com> References: <20230321-am62-lp-sk-v2-0-0a56e1694804@ti.com> In-Reply-To: <20230321-am62-lp-sk-v2-0-0a56e1694804@ti.com> To: Nishanth Menon , Vignesh Raghavendra , "Tero Kristo" , Rob Herring , "Krzysztof Kozlowski" CC: , , , , Anand Gadiyar X-Mailer: b4 0.12.2 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anand Gadiyar The AM62x LP SK board is similar to the AM62x SK board, but has some not-so-minor changes that requires different device tree. The differences are mainly: - AM62x SoC in the AMC package that meets AECQ100 automotive standard. - LPDDR4 versus DDR4 on the AM62x SK. - TPS65219 PMIC instead of discrete regulators. - IO expander pin names are wired differently. - Second ethernet port is currently disabled as the boards do not have the part physically installed. - OSPI NAND vs OSPI NOR. - No WLAN chip instead a SDIO M.2 connector. Signed-off-by: Anand Gadiyar [vigneshr@ti.com: Add PMIC node] Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 1 + arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 227 ++++++++++ 2 files changed, 228 insertions(+) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 6acd12409d59..785cc4f97e1e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -10,6 +10,7 @@ =20 # Boards with AM62x SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62-lp-sk.dtb =20 # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts new file mode 100644 index 000000000000..b2ca19e3042e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP + * + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +/dts-v1/; + +#include "k3-am62x-sk-common.dtsi" + +/ { + compatible =3D "ti,am62-lp-sk", "ti,am625"; + model =3D "Texas Instruments AM62x LP SK"; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vmain_pd"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS630702RNMR */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_sys"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vcc_3v3_sys>; + gpio =3D <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vddshv_sdio: regulator-4 { + compatible =3D "regulator-gpio"; + regulator-name =3D "vddshv_sdio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vddshv_sdio_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&ldo1_reg>; + gpios =3D <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; +}; + +&main_pmx0 { + vddshv_sdio_pins_default: vddshv-sdio-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */ + >; + }; +}; + +&main_i2c1 { + exp1: gpio@22 { + compatible =3D "ti,tca6424"; + reg =3D <0x22>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", + "GPIO_HDMI_RSTn", "CSI_GPIO0", + "CSI_GPIO1", "GPIO_OLDI_INT", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "", "IO_EXP_TEST_LED"; + + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells =3D <2>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_gpio1_ioexp_intr_pins_default>; + }; + + exp2: gpio@23 { + compatible =3D "ti,tca6424"; + reg =3D <0x23>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "", "", + "", "", + "", "", + "", "", + "WL_LT_EN", "CSI_RSTz", + "", "", + "", "", + "", "", + "SPI0_FET_SEL", "SPI0_FET_OE", + "GPIO_OLDI_RSTn", "PRU_3V3_EN", + "", "", + "CSI_VLDO_SEL", "SOC_WLAN_SDIO_RST"; + }; +}; + +&sdhci1 { + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vddshv_sdio>; +}; + +&cpsw_port2 { + status =3D "disabled"; +}; + +&main_i2c0 { + tps65219: pmic@30 { + compatible =3D "ti,tps65219"; + reg =3D <0x30>; + buck1-supply =3D <&vcc_3v3_sys>; + buck2-supply =3D <&vcc_3v3_sys>; + buck3-supply =3D <&vcc_3v3_sys>; + ldo1-supply =3D <&vcc_3v3_sys>; + ldo2-supply =3D <&buck2_reg>; + ldo3-supply =3D <&vcc_3v3_sys>; + ldo4-supply =3D <&vcc_3v3_sys>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + + interrupt-parent =3D <&gic500>; + interrupts =3D ; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name =3D "VDD_CORE"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name =3D "VCC1V8_SYS"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name =3D "VDD_LPDDR4"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name =3D "VDDSHV_SDIO"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + ldo2_reg: ldo2 { + regulator-name =3D "VDDAR_CORE"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name =3D "VDDA_1V8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name =3D "VDD_1V2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; --=20 2.40.0