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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id v11-20020a4aaecb000000b0053732f1acd2sm4428977oon.5.2023.03.20.16.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 16:39:33 -0700 (PDT) Received: (nullmailer pid 2920813 invoked by uid 1000); Mon, 20 Mar 2023 23:39:32 -0000 From: Rob Herring To: Thomas Gleixner , Marc Zyngier , Krzysztof Kozlowski , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Manivannan Sadhasivam , Linus Walleij , Imre Kaloz , Krzysztof Halasa , Palmer Dabbelt , Paul Walmsley Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-riscv@lists.infradead.org Subject: [PATCH] dt-bindings: interrupt-controller: Drop unneeded quotes Date: Mon, 20 Mar 2023 18:39:27 -0500 Message-Id: <20230320233928.2920693-1-robh@kernel.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij --- .../bindings/interrupt-controller/actions,owl-sirq.yaml | 4 ++-- .../bindings/interrupt-controller/fsl,irqsteer.yaml | 4 ++-- .../interrupt-controller/intel,ce4100-ioapic.yaml | 4 ++-- .../bindings/interrupt-controller/intel,ce4100-lapic.yaml | 4 ++-- .../interrupt-controller/intel,ixp4xx-interrupt.yaml | 4 ++-- .../bindings/interrupt-controller/loongson,htpic.yaml | 4 ++-- .../bindings/interrupt-controller/loongson,htvec.yaml | 4 ++-- .../bindings/interrupt-controller/loongson,liointc.yaml | 8 ++++---- .../bindings/interrupt-controller/loongson,pch-msi.yaml | 8 ++++---- .../bindings/interrupt-controller/loongson,pch-pic.yaml | 6 +++--- .../bindings/interrupt-controller/mrvl,intc.yaml | 4 ++-- .../interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++-- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 2 +- 13 files changed, 30 insertions(+), 30 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/actions= ,owl-sirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/act= ions,owl-sirq.yaml index 5da333c644c9..27756d0c5419 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/actions,owl-si= rq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/actions,owl-si= rq.yaml @@ -32,7 +32,7 @@ properties: The first cell is the input IRQ number, between 0 and 2, while the s= econd cell is the trigger type as defined in interrupt.txt in this directo= ry. =20 - 'interrupts': + interrupts: description: | Contains the GIC SPI IRQs mapped to the external interrupt lines. They shall be specified sequentially from output 0 to 2. @@ -44,7 +44,7 @@ required: - reg - interrupt-controller - '#interrupt-cells' - - 'interrupts' + - interrupts =20 additionalProperties: false =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irq= steer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irq= steer.yaml index bcb5e20fa9ca..20ad4ad82ad6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.y= aml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.y= aml @@ -48,13 +48,13 @@ properties: const: 1 =20 fsl,channel: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: | u32 value representing the output channel that all input IRQs should= be steered into. =20 fsl,num-irqs: - $ref: '/schemas/types.yaml#/definitions/uint32' + $ref: /schemas/types.yaml#/definitions/uint32 description: | u32 value representing the number of input interrupts of this channe= l, should be multiple of 32 input interrupts and up to 512 interrupts. diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.yaml index 39ab8cdd19b4..a3ac818f067d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioap= ic.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapi= c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml index d2d0145cb889..6b20a5fa8590 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapi= c.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic= .yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,i= xp4xx-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/intel,ixp4xx-interrupt.yaml index 14dced11877b..a02a6b5af205 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-i= nterrupt.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-i= nterrupt.yaml @@ -2,8 +2,8 @@ # Copyright 2018 Linaro Ltd. %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-inte= rrupt.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-inter= rupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Intel IXP4xx XScale Networking Processors Interrupt Controller =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,htpic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loong= son,htpic.yaml index d6bc1a687fc7..f0acd5671bb1 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic= .yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htpic= .yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.ya= ml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Loongson-3 HyperTransport Interrupt Controller =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,htvec.yaml b/Documentation/devicetree/bindings/interrupt-controller/loong= son,htvec.yaml index 87a74558204f..1d145763908e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec= .yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,htvec= .yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.ya= ml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Loongson-3 HyperTransport Interrupt Vector Controller =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loo= ngson,liointc.yaml index 750cc44628e9..00b570c82903 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,lioin= tc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,lioin= tc.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.= yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Loongson Local I/O Interrupt Controller =20 @@ -54,7 +54,7 @@ properties: '#interrupt-cells': const: 2 =20 - 'loongson,parent_int_map': + loongson,parent_int_map: description: | This property points how the children interrupts will be mapped into= CPU interrupt lines. Each cell refers to a parent interrupt line from 0 = to 3 @@ -71,7 +71,7 @@ required: - interrupts - interrupt-controller - '#interrupt-cells' - - 'loongson,parent_int_map' + - loongson,parent_int_map =20 =20 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,pch-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/loo= ngson,pch-msi.yaml index 31e6bfbc3fd3..a71fc2218ede 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-m= si.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-m= si.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.= yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Loongson PCH MSI Controller =20 @@ -25,7 +25,7 @@ properties: description: u32 value of the base of parent HyperTransport vector allocated to PCH MSI. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 255 =20 @@ -33,7 +33,7 @@ properties: description: u32 value of the number of parent HyperTransport vectors allocated to PCH MSI. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 256 =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongso= n,pch-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/loo= ngson,pch-pic.yaml index fdd6a38a31db..b7bc5cb1dff2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-p= ic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,pch-p= ic.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.= yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Loongson PCH PIC Controller =20 @@ -25,7 +25,7 @@ properties: description: u32 value of the base of parent HyperTransport vector allocated to PCH PIC. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 192 =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,in= tc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.= yaml index 9acc21028413..b7c5022eec84 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml @@ -53,8 +53,8 @@ allOf: maxItems: 1 reg-names: items: - - const: 'mux status' - - const: 'mux mask' + - const: mux status + - const: mux mask required: - interrupts else: diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,oc= elot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controlle= r/mscc,ocelot-icpu-intr.yaml index 27b798bfe29b..4ff609faba32 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-ic= pu-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-ic= pu-intr.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-= intr.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-i= ntr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Microsemi Ocelot SoC ICPU Interrupt Controller =20 diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 63bc89e13480..b089e62f90aa 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -90,7 +90,7 @@ properties: riscv,cpu-intc node, which has a riscv node as parent. =20 riscv,ndev: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Specifies how many external interrupts are supported by this control= ler. =20 --=20 2.39.2