From nobody Mon Feb 9 23:44:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9781FC6FD1C for ; Mon, 20 Mar 2023 20:41:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbjCTUlu (ORCPT ); Mon, 20 Mar 2023 16:41:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230138AbjCTUln (ORCPT ); Mon, 20 Mar 2023 16:41:43 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7113A211D1; Mon, 20 Mar 2023 13:41:09 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id j3-20020a17090adc8300b0023d09aea4a6so17901116pjv.5; Mon, 20 Mar 2023 13:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679344866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aLzZHqL9WDRVGnePjQNNc3Xx0tLOUWtULszDoChdvHo=; b=T4RdoTqAUyheVLcBUfrCxFvnSphcUj0QvLw1PMhUbSSN0oFEK06cNB028UQ+o/Gb4j sc6/x0t07Y+AVdculX3dPV3XrIfIKA9cOyH3MBHEvnT/cT1600YGmWC5891w5A/MorFx wVS9IZaGUdj5ma1OOOEiOo1PuGwbUphe1bnAKBUkd8/ogHFNyH7CNz3Fk29MmotNnY/z O9FezS0T+DcvXBTyqRlqWsPAfi1t0hvaeOxv//q7vChivDKu3rwvver5vTw5hbX4vd8Y wCJAyhaSE9ZKwAei5Z+AOZmBoOWLxPUkRmw6ZfyuEE4uECMzVH9ShhzjVUsOA4aEDawe Z3/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679344866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aLzZHqL9WDRVGnePjQNNc3Xx0tLOUWtULszDoChdvHo=; b=dD0wFNrv970FFOwHVXtkzZ5fvTL3+F3qy9F1wMkub6vOxQbLmfZpTEAhF18xnklUcx mFVA+VIjgOIYNBIQ78oZjjZSlrsL5nXHk1yM7I3Eu+dyJO26nL8VXMxVAr3AVN/phhxX A/m4MtSkX15MQvCuJrboLqeR5rST8M0aDpaaX9Kj3ZIICq3dQO0caKX7Xv/GsU+zvC4I lmHudNrlKIFPpoqC7okKHr52+yE4RxWTqB/SLIv8cMaPFMEP1aNh+PVEwUd35+9ZAIpj WAbOihNrH7excrhCtahptiF2y6NQNb0m4mjXg9eaeF0fkjhaT9hYTcDyakvbSvjcdIpl 8R5A== X-Gm-Message-State: AO0yUKUUeb1eXxC6f0pK2Vt6a1yYtubVUDgII7mfJEF8cSA6/YFmKiTP veoYXa7j/G6NTV+17LYgkt0= X-Google-Smtp-Source: AK7set+KqwsbSiOyUKu2Sad44ttZL1lvUwQmBmPdg3RKV4lLPY7XeLWk7LScu+kGyIEHEsnydyPbww== X-Received: by 2002:a17:90b:4d8f:b0:237:5a3c:e86c with SMTP id oj15-20020a17090b4d8f00b002375a3ce86cmr452331pjb.24.1679344865643; Mon, 20 Mar 2023 13:41:05 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.202]) by smtp.gmail.com with ESMTPSA id c3-20020a17090aa60300b0023b29b464f9sm6580943pjq.27.2023.03.20.13.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 13:41:05 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/5] clk: hisilicon: Rename Hi3798CV200 to Hi3798 Date: Tue, 21 Mar 2023 04:40:34 +0800 Message-Id: <20230320204042.980708-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320204042.980708-1-mmyangfl@gmail.com> References: <20230320204042.980708-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rename Hisilicon Hi3798CV200 to Hi3798, to be reused with other Hi3798 series SoCs. Signed-off-by: David Yang --- drivers/clk/hisilicon/Kconfig | 6 +- drivers/clk/hisilicon/Makefile | 2 +- .../{crg-hi3798cv200.c =3D> crg-hi3798.c} | 181 +++++++++--------- 3 files changed, 95 insertions(+), 94 deletions(-) rename drivers/clk/hisilicon/{crg-hi3798cv200.c =3D> crg-hi3798.c} (68%) diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index c1ec75aa4..fa2d9920f 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -37,13 +37,13 @@ config COMMON_CLK_HI3670 help Build the clock driver for hi3670. =20 -config COMMON_CLK_HI3798CV200 - tristate "Hi3798CV200 Clock Driver" +config COMMON_CLK_HI3798 + tristate "Hi3798 Clock Driver" depends on ARCH_HISI || COMPILE_TEST select RESET_HISI default ARCH_HISI help - Build the clock driver for hi3798cv200. + Build the clock driver for hi3798. =20 config COMMON_CLK_HI6220 bool "Hi6220 Clock Driver" diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 2978e56cb..cfef47a19 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_COMMON_CLK_HI3519) +=3D clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI3559A) +=3D clk-hi3559a.o obj-$(CONFIG_COMMON_CLK_HI3660) +=3D clk-hi3660.o obj-$(CONFIG_COMMON_CLK_HI3670) +=3D clk-hi3670.o -obj-$(CONFIG_COMMON_CLK_HI3798CV200) +=3D crg-hi3798cv200.o +obj-$(CONFIG_COMMON_CLK_HI3798) +=3D crg-hi3798.o obj-$(CONFIG_COMMON_CLK_HI6220) +=3D clk-hi6220.o obj-$(CONFIG_RESET_HISI) +=3D reset.o obj-$(CONFIG_STUB_CLK_HI6220) +=3D clk-hi6220-stub.o diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilico= n/crg-hi3798.c similarity index 68% rename from drivers/clk/hisilicon/crg-hi3798cv200.c rename to drivers/clk/hisilicon/crg-hi3798.c index 08a19ba77..7e9507de2 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Hi3798CV200 Clock and Reset Generator Driver + * Hi3798 Clock and Reset Generator Driver * * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. */ @@ -14,75 +14,76 @@ #include "crg.h" #include "reset.h" =20 -/* hi3798CV200 core CRG */ -#define HI3798CV200_INNER_CLK_OFFSET 64 -#define HI3798CV200_FIXED_24M 65 -#define HI3798CV200_FIXED_25M 66 -#define HI3798CV200_FIXED_50M 67 -#define HI3798CV200_FIXED_75M 68 -#define HI3798CV200_FIXED_100M 69 -#define HI3798CV200_FIXED_150M 70 -#define HI3798CV200_FIXED_200M 71 -#define HI3798CV200_FIXED_250M 72 -#define HI3798CV200_FIXED_300M 73 -#define HI3798CV200_FIXED_400M 74 -#define HI3798CV200_MMC_MUX 75 -#define HI3798CV200_ETH_PUB_CLK 76 -#define HI3798CV200_ETH_BUS_CLK 77 -#define HI3798CV200_ETH_BUS0_CLK 78 -#define HI3798CV200_ETH_BUS1_CLK 79 -#define HI3798CV200_COMBPHY1_MUX 80 -#define HI3798CV200_FIXED_12M 81 -#define HI3798CV200_FIXED_48M 82 -#define HI3798CV200_FIXED_60M 83 -#define HI3798CV200_FIXED_166P5M 84 -#define HI3798CV200_SDIO0_MUX 85 -#define HI3798CV200_COMBPHY0_MUX 86 - -#define HI3798CV200_CRG_NR_CLKS 128 - -static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = =3D { +/* hi3798 core CRG */ +#define HI3798_INNER_CLK_OFFSET 64 +#define HI3798_FIXED_24M 65 +#define HI3798_FIXED_25M 66 +#define HI3798_FIXED_50M 67 +#define HI3798_FIXED_75M 68 +#define HI3798_FIXED_100M 69 +#define HI3798_FIXED_150M 70 +#define HI3798_FIXED_200M 71 +#define HI3798_FIXED_250M 72 +#define HI3798_FIXED_300M 73 +#define HI3798_FIXED_400M 74 +#define HI3798_MMC_MUX 75 +#define HI3798_ETH_PUB_CLK 76 +#define HI3798_ETH_BUS_CLK 77 +#define HI3798_ETH_BUS0_CLK 78 +#define HI3798_ETH_BUS1_CLK 79 +#define HI3798_COMBPHY1_MUX 80 +#define HI3798_FIXED_12M 81 +#define HI3798_FIXED_48M 82 +#define HI3798_FIXED_60M 83 +#define HI3798_FIXED_166P5M 84 +#define HI3798_SDIO0_MUX 85 +#define HI3798_COMBPHY0_MUX 86 + +#define HI3798_CRG_NR_CLKS 128 + +static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] =3D { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, - { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, }, - { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, - { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, - { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, }, - { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, - { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, }, - { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, - { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, - { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, - { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, - { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, }, - { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, }, + { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, + { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, + { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, + { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, + { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, + { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, + { HI3798_FIXED_200M, "200m", NULL, 0, 200000000, }, + { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; =20 -static const char *const mmc_mux_p[] =3D { +static const char *const hi3798cv200_mmc_mux_p[] =3D { "100m", "50m", "25m", "200m", "150m" }; -static u32 mmc_mux_table[] =3D {0, 1, 2, 3, 6}; +static u32 hi3798cv200_mmc_mux_table[] =3D {0, 1, 2, 3, 6}; =20 -static const char *const comphy_mux_p[] =3D { +static const char *const hi3798cv200_comphy_mux_p[] =3D { "100m", "25m"}; -static u32 comphy_mux_table[] =3D {2, 3}; +static u32 hi3798cv200_comphy_mux_table[] =3D {2, 3}; =20 -static const char *const sdio_mux_p[] =3D { +static const char *const hi3798cv200_sdio_mux_p[] =3D { "100m", "50m", "150m", "166p5m" }; -static u32 sdio_mux_table[] =3D {0, 1, 2, 3}; +static u32 hi3798cv200_sdio_mux_table[] =3D {0, 1, 2, 3}; =20 static struct hisi_mux_clock hi3798cv200_mux_clks[] =3D { - { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), - CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, - { HI3798CV200_COMBPHY0_MUX, "combphy0_mux", - comphy_mux_p, ARRAY_SIZE(comphy_mux_p), - CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, }, - { HI3798CV200_COMBPHY1_MUX, "combphy1_mux", - comphy_mux_p, ARRAY_SIZE(comphy_mux_p), - CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, }, - { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p, - ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT, - 0x9c, 8, 2, 0, sdio_mux_table, }, + { HI3798_MMC_MUX, "mmc_mux", hi3798cv200_mmc_mux_p, + ARRAY_SIZE(hi3798cv200_mmc_mux_p), CLK_SET_RATE_PARENT, + 0xa0, 8, 3, 0, hi3798cv200_mmc_mux_table, }, + { HI3798_COMBPHY0_MUX, "combphy0_mux", hi3798cv200_comphy_mux_p, + ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT, + 0x188, 2, 2, 0, hi3798cv200_comphy_mux_table, }, + { HI3798_COMBPHY1_MUX, "combphy1_mux", hi3798cv200_comphy_mux_p, + ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT, + 0x188, 10, 2, 0, hi3798cv200_comphy_mux_table, }, + { HI3798_SDIO0_MUX, "sdio0_mux", hi3798cv200_sdio_mux_p, + ARRAY_SIZE(hi3798cv200_sdio_mux_p), CLK_SET_RATE_PARENT, + 0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, }, }; =20 static u32 mmc_phase_regvals[] =3D {0, 1, 2, 3, 4, 5, 6, 7}; @@ -117,7 +118,7 @@ static const struct hisi_gate_clock hi3798cv200_gate_cl= ks[] =3D { CLK_SET_RATE_PARENT, 0x70, 0, 0, }, /* SDIO */ { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", - CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, + CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, /* EMMC */ @@ -135,13 +136,13 @@ static const struct hisi_gate_clock hi3798cv200_gate_= clks[] =3D { { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m", CLK_SET_RATE_PARENT, 0x18c, 3, 0, }, /* Ethernet */ - { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL, + { HI3798_ETH_PUB_CLK, "clk_pub", NULL, CLK_SET_RATE_PARENT, 0xcc, 5, 0, }, - { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub", + { HI3798_ETH_BUS_CLK, "clk_bus", "clk_pub", CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, - { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", + { HI3798_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, - { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", + { HI3798_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", CLK_SET_RATE_PARENT, 0xcc, 2, 0, }, { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0", CLK_SET_RATE_PARENT, 0xcc, 3, 0, }, @@ -199,7 +200,7 @@ static struct hisi_clock_data *hi3798cv200_clk_register( struct hisi_clock_data *clk_data; int ret; =20 - clk_data =3D hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); + clk_data =3D hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); =20 @@ -211,8 +212,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register( if (ret) return ERR_PTR(ret); =20 - ret =3D hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + ret =3D hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); @@ -245,8 +246,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register( ARRAY_SIZE(hi3798cv200_mux_clks), clk_data); unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), clk_data); return ERR_PTR(ret); } @@ -263,8 +264,8 @@ static void hi3798cv200_clk_unregister(struct platform_= device *pdev) hisi_clk_unregister_mux(hi3798cv200_mux_clks, ARRAY_SIZE(hi3798cv200_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), crg->clk_data); } =20 @@ -273,9 +274,9 @@ static const struct hisi_crg_funcs hi3798cv200_crg_func= s =3D { .unregister_clks =3D hi3798cv200_clk_unregister, }; =20 -/* hi3798CV200 sysctrl CRG */ +/* hi3798 sysctrl CRG */ =20 -#define HI3798CV200_SYSCTRL_NR_CLKS 16 +#define HI3798_SYSCTRL_NR_CLKS 16 =20 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] =3D { { HISTB_IR_CLK, "clk_ir", "24m", @@ -292,7 +293,7 @@ static struct hisi_clock_data *hi3798cv200_sysctrl_clk_= register( struct hisi_clock_data *clk_data; int ret; =20 - clk_data =3D hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); + clk_data =3D hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); =20 @@ -332,16 +333,16 @@ static const struct hisi_crg_funcs hi3798cv200_sysctr= l_funcs =3D { .unregister_clks =3D hi3798cv200_sysctrl_clk_unregister, }; =20 -static const struct of_device_id hi3798cv200_crg_match_table[] =3D { +static const struct of_device_id hi3798_crg_match_table[] =3D { { .compatible =3D "hisilicon,hi3798cv200-crg", .data =3D &hi3798cv200_crg_funcs }, { .compatible =3D "hisilicon,hi3798cv200-sysctrl", .data =3D &hi3798cv200_sysctrl_funcs }, { } }; -MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table); +MODULE_DEVICE_TABLE(of, hi3798_crg_match_table); =20 -static int hi3798cv200_crg_probe(struct platform_device *pdev) +static int hi3798_crg_probe(struct platform_device *pdev) { struct hisi_crg_dev *crg; =20 @@ -367,7 +368,7 @@ static int hi3798cv200_crg_probe(struct platform_device= *pdev) return 0; } =20 -static int hi3798cv200_crg_remove(struct platform_device *pdev) +static int hi3798_crg_remove(struct platform_device *pdev) { struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); =20 @@ -376,26 +377,26 @@ static int hi3798cv200_crg_remove(struct platform_dev= ice *pdev) return 0; } =20 -static struct platform_driver hi3798cv200_crg_driver =3D { - .probe =3D hi3798cv200_crg_probe, - .remove =3D hi3798cv200_crg_remove, - .driver =3D { - .name =3D "hi3798cv200-crg", - .of_match_table =3D hi3798cv200_crg_match_table, +static struct platform_driver hi3798_crg_driver =3D { + .probe =3D hi3798_crg_probe, + .remove =3D hi3798_crg_remove, + .driver =3D { + .name =3D "hi3798-crg", + .of_match_table =3D hi3798_crg_match_table, }, }; =20 -static int __init hi3798cv200_crg_init(void) +static int __init hi3798_crg_init(void) { - return platform_driver_register(&hi3798cv200_crg_driver); + return platform_driver_register(&hi3798_crg_driver); } -core_initcall(hi3798cv200_crg_init); +core_initcall(hi3798_crg_init); =20 -static void __exit hi3798cv200_crg_exit(void) +static void __exit hi3798_crg_exit(void) { - platform_driver_unregister(&hi3798cv200_crg_driver); + platform_driver_unregister(&hi3798_crg_driver); } -module_exit(hi3798cv200_crg_exit); +module_exit(hi3798_crg_exit); =20 MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver"); +MODULE_DESCRIPTION("HiSilicon Hi3798 CRG Driver"); --=20 2.39.2 From nobody Mon Feb 9 23:44:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2BD0C761A6 for ; Mon, 20 Mar 2023 20:41:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230289AbjCTUlp (ORCPT ); Mon, 20 Mar 2023 16:41:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229886AbjCTUlj (ORCPT ); Mon, 20 Mar 2023 16:41:39 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B70B2BED0; Mon, 20 Mar 2023 13:41:15 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id e15-20020a17090ac20f00b0023d1b009f52so17919888pjt.2; Mon, 20 Mar 2023 13:41:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679344873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nkthGZ8hQmB63+z0P86zjPOZhKQbhtrGN77pfJie3Dc=; b=H0EhE8FYH02W0vkiRASe0tU29xa8EdRpbEA/oZwW4J3lPA8C1hRR0/FMcEQKRmWZ4L rDLO+/JweuzrczFtbq9I0Qgsn+AaXZL/ox1h8NMHHFlBhvD7SB9NHno/AXKOuk5RHBlQ +dN/83yD/9/L8ZEZV65n8BZRnvl8uodNbZFTDJNlAU5iFPTeRgN7atiri8JpEMKUmyGm Ko+oB/VyMU/aYKccNSpa128YjW4Zbe6qMDnNWiBG/d2t4dIbIr6yMvxHL66Pk74nFW0N ZfjYBZg6Rc0w4x4OTfOCr1A+D+czEHL06ia5oaWrjJzD5VjG5aVKcdqfez9Xokxl5muC ZAxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679344873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nkthGZ8hQmB63+z0P86zjPOZhKQbhtrGN77pfJie3Dc=; b=yPxJYJaRx4IXFM8XbEJxmaT6M1kAl6vwHIrrVKzWdK6gevJrPjbZ50KF/KAKuqDf2p guu8ekujMZBD8wCRYPMg1K97I76Q2XB3GTZakCvvKxxva3uJxfeO5Zb3z7PQF/uus/ER s7ONfK3lHOFJrztFXK2M6uMSdGw1umQkHGWP5k/D1iz+LfUTOR0rvfEcIF256bhN8cR9 /frzYhdlL6OyvctZ6ybJ+oMmQECPLP/amMoTGpXhnTmwkcNeT8XU8oBV0zUUHEczzp7o r3YO3RrhOaPj7RCrBUrKrbFQSk0+vwbo1+2rit9JealjrcAlm8ahVkPiyiSdxz9lvA5q Qmdg== X-Gm-Message-State: AO0yUKXmNf+EOY/bJu46q93Eu1vYOPmKr8bacUsef1thf52JwyvPE2Vi ol9+U+/qeI/Gn5evihSLZns= X-Google-Smtp-Source: AK7set8RVQaS9D7t8SxfdrkWqP9l7IwGixCu7FRAFWlxaDFUGZyQRj4yiQ5BUHzKV+HeuXYRS5r8AA== X-Received: by 2002:a17:90b:380e:b0:23f:a810:c077 with SMTP id mq14-20020a17090b380e00b0023fa810c077mr386357pjb.40.1679344873611; Mon, 20 Mar 2023 13:41:13 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.202]) by smtp.gmail.com with ESMTPSA id c3-20020a17090aa60300b0023b29b464f9sm6580943pjq.27.2023.03.20.13.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 13:41:13 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/5] clk: hisilicon: Extract common functions Date: Tue, 21 Mar 2023 04:40:35 +0800 Message-Id: <20230320204042.980708-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320204042.980708-1-mmyangfl@gmail.com> References: <20230320204042.980708-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To be reused with other Hi3798 series SoCs. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 233 ++++++++++++++++------------- 1 file changed, 131 insertions(+), 102 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg= -hi3798.c index 7e9507de2..2f8f14e73 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -59,6 +59,119 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_= rate_clks[] =3D { { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; =20 +struct hi3798_clks { + const struct hisi_gate_clock *gate_clks; + int gate_clks_nums; + const struct hisi_mux_clock *mux_clks; + int mux_clks_nums; + const struct hisi_phase_clock *phase_clks; + int phase_clks_nums; +}; + +static struct hisi_clock_data *hi3798_clk_register( + struct platform_device *pdev, const struct hi3798_clks *clks) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data =3D hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + /* hisi_phase_clock is resource managed */ + ret =3D hisi_clk_register_phase(&pdev->dev, clks->phase_clks, + clks->phase_clks_nums, clk_data); + if (ret) + return ERR_PTR(ret); + + ret =3D hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + clk_data); + if (ret) + return ERR_PTR(ret); + + ret =3D hisi_clk_register_mux(clks->mux_clks, clks->mux_clks_nums, clk_da= ta); + if (ret) + goto unregister_fixed_rate; + + ret =3D hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk= _data); + if (ret) + goto unregister_mux; + + ret =3D of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); +unregister_mux: + hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, clk_data); +unregister_fixed_rate: + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + clk_data); + return ERR_PTR(ret); +} + +static void hi3798_clk_unregister( + struct platform_device *pdev, const struct hi3798_clks *clks) +{ + struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_= data); + hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, crg->clk_dat= a); + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + crg->clk_data); +} + +/* hi3798 sysctrl CRG */ + +#define HI3798_SYSCTRL_NR_CLKS 16 + +static struct hisi_clock_data *hi3798_sysctrl_clk_register( + struct platform_device *pdev, const struct hi3798_clks *clks) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data =3D hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + ret =3D hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk= _data); + if (ret) + return ERR_PTR(ret); + + ret =3D of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); + return ERR_PTR(ret); +} + +static void hi3798_sysctrl_clk_unregister( + struct platform_device *pdev, const struct hi3798_clks *clks) +{ + struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_= data); +} + +/* hi3798CV200 */ + static const char *const hi3798cv200_mmc_mux_p[] =3D { "100m", "50m", "25m", "200m", "150m" }; static u32 hi3798cv200_mmc_mux_table[] =3D {0, 1, 2, 3, 6}; @@ -194,79 +307,24 @@ static const struct hisi_gate_clock hi3798cv200_gate_= clks[] =3D { CLK_SET_RATE_PARENT, 0xb0, 18, 0 }, }; =20 +static const struct hi3798_clks hi3798cv200_crg_clks =3D { + .gate_clks =3D hi3798cv200_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798cv200_gate_clks), + .mux_clks =3D hi3798cv200_mux_clks, + .mux_clks_nums =3D ARRAY_SIZE(hi3798cv200_mux_clks), + .phase_clks =3D hi3798cv200_phase_clks, + .phase_clks_nums =3D ARRAY_SIZE(hi3798cv200_phase_clks), +}; + static struct hisi_clock_data *hi3798cv200_clk_register( struct platform_device *pdev) { - struct hisi_clock_data *clk_data; - int ret; - - clk_data =3D hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - /* hisi_phase_clock is resource managed */ - ret =3D hisi_clk_register_phase(&pdev->dev, - hi3798cv200_phase_clks, - ARRAY_SIZE(hi3798cv200_phase_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret =3D hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret =3D hisi_clk_register_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); - if (ret) - goto unregister_fixed_rate; - - ret =3D hisi_clk_register_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); - if (ret) - goto unregister_mux; - - ret =3D of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - clk_data); - return ERR_PTR(ret); + return hi3798_clk_register(pdev, &hi3798cv200_crg_clks); } =20 static void hi3798cv200_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - crg->clk_data); - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - crg->clk_data); + hi3798_clk_unregister(pdev, &hi3798cv200_crg_clks); } =20 static const struct hisi_crg_funcs hi3798cv200_crg_funcs =3D { @@ -274,10 +332,6 @@ static const struct hisi_crg_funcs hi3798cv200_crg_fun= cs =3D { .unregister_clks =3D hi3798cv200_clk_unregister, }; =20 -/* hi3798 sysctrl CRG */ - -#define HI3798_SYSCTRL_NR_CLKS 16 - static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] =3D { { HISTB_IR_CLK, "clk_ir", "24m", CLK_SET_RATE_PARENT, 0x48, 4, 0, }, @@ -287,45 +341,20 @@ static const struct hisi_gate_clock hi3798cv200_sysct= rl_gate_clks[] =3D { CLK_SET_RATE_PARENT, 0x48, 10, 0, }, }; =20 +static const struct hi3798_clks hi3798cv200_sysctrl_clks =3D { + .gate_clks =3D hi3798cv200_sysctrl_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), +}; + static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( struct platform_device *pdev) { - struct hisi_clock_data *clk_data; - int ret; - - clk_data =3D hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret =3D hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret =3D of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - return ERR_PTR(ret); + return hi3798_sysctrl_clk_register(pdev, &hi3798cv200_sysctrl_clks); } =20 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pde= v) { - struct hisi_crg_dev *crg =3D platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - crg->clk_data); + hi3798_sysctrl_clk_unregister(pdev, &hi3798cv200_sysctrl_clks); } =20 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs =3D { --=20 2.39.2 From nobody Mon Feb 9 23:44:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6A88C6FD1C for ; Mon, 20 Mar 2023 20:41:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229612AbjCTUls (ORCPT ); Mon, 20 Mar 2023 16:41:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230128AbjCTUll (ORCPT ); Mon, 20 Mar 2023 16:41:41 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F05338475; Mon, 20 Mar 2023 13:41:22 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id x15so3136887pjk.2; Mon, 20 Mar 2023 13:41:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679344881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Glp/G+tr1mPfDBJEHiZ14zAl4MCfL3gDlRqKOfGi5w8=; b=BXRaRRBQXCXbQMPiuRzNLUEpSAMijPSy9JMoUzAT1pH8e23NJs8vw/XkODDGoo8l2G RV7wgtV5uRSWAg+SVwUFUQuu6r7KZxZDnKkjD7XKUzWwIjvtzCLv2nlmabdY3duACrND v9M6n+zKEgwxTcBmucggUFacjPwdTaHlVj2VBub4JvbrbAmc7jkxtWvia1FZ31Hh0pf9 y9N7lHimfpeKXsWOdj9O24ZHiM/KipN08wCrl2lKTFYm2Wqlo4ttdbE7ysCiOpd4UCOm /h2iU/WiX1uqrFvUnO5avmsjSKwi+vgqYE3XxdAuJLXnCOK3TOslRIx38qzUUGevkHLi 34Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679344881; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Glp/G+tr1mPfDBJEHiZ14zAl4MCfL3gDlRqKOfGi5w8=; b=WjFI04OKYwR6xhVBmb05bZ5LDIbLWQjcN1SowsCXhsT19UIKeqsyD94yAxkFpY4+ga 5eQ1LzPceJ2s7RAts0sts59dGaNb16B5Wr2HMKbuonPR75WdqFAXSu9Yn3wZb4CBaXvu E6/13NCoF8n1hACHnRskFJCgEZkzlVthChRV9UtasNmht/kzyGQ0xCle9afLsfIhM1s9 pZdls7cB3pYkmzGPlTLiuztq6vmFrYhHoV/5hYH/0Oy5RXWcfjptTA2OfYU7zvkCm8JS pLDx2YROUQ9JdW7RsS19MkAp1Q0yW7LCTuM6ItKo8Boh2LGcdd1D2QoQwPEac0H8jp6I AQWg== X-Gm-Message-State: AO0yUKUKORwZnaGeTtx+v2jrWwQzegXG+DDlk/thkZbbqqos/HJqehxw C0HULS10ay2qZX8oVgzP3Gc= X-Google-Smtp-Source: AK7set+sNN4Ttpic5J7HpSPnkZodxr68UgoarTv29kxtu9SnBR5Yl0OcDzpPN7cp/avUPGQctZDcQA== X-Received: by 2002:a17:90b:4b86:b0:23d:19c6:84b7 with SMTP id lr6-20020a17090b4b8600b0023d19c684b7mr453957pjb.16.1679344881485; Mon, 20 Mar 2023 13:41:21 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.202]) by smtp.gmail.com with ESMTPSA id c3-20020a17090aa60300b0023b29b464f9sm6580943pjq.27.2023.03.20.13.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 13:41:21 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/5] clk: hisilicon: Add complex clock for Hi3798 Date: Tue, 21 Mar 2023 04:40:36 +0800 Message-Id: <20230320204042.980708-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320204042.980708-1-mmyangfl@gmail.com> References: <20230320204042.980708-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Complex clock allows manipulating multiple bits simultaneously. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 138 ++++++++++++++++++++++++++++- 1 file changed, 137 insertions(+), 1 deletion(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg= -hi3798.c index 2f8f14e73..0b29c01c6 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -7,9 +7,11 @@ =20 #include #include +#include #include #include #include +#include #include "clk.h" #include "crg.h" #include "reset.h" @@ -59,6 +61,131 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_= rate_clks[] =3D { { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; =20 +struct hi3798_complex_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u32 mask; + u32 value; + const char *alias; +}; + +struct hi3798_clk_complex { + struct clk_hw hw; + void __iomem *reg; + u32 mask; + u32 value; +}; + +#define to_complex_clk(_hw) container_of(_hw, struct hi3798_clk_complex, h= w) + +static int hi3798_clk_complex_prepare(struct clk_hw *hw) +{ + struct hi3798_clk_complex *clk =3D to_complex_clk(hw); + u32 val; + + val =3D readl_relaxed(clk->reg); + val &=3D ~(clk->mask); + val |=3D clk->value; + writel_relaxed(val, clk->reg); + + return 0; +} + +static void hi3798_clk_complex_unprepare(struct clk_hw *hw) +{ + struct hi3798_clk_complex *clk =3D to_complex_clk(hw); + u32 val; + + val =3D readl_relaxed(clk->reg); + val &=3D ~(clk->mask); + writel_relaxed(val, clk->reg); +} + +static int hi3798_clk_complex_is_prepared(struct clk_hw *hw) +{ + struct hi3798_clk_complex *clk =3D to_complex_clk(hw); + u32 val; + + val =3D readl_relaxed(clk->reg); + return (val & clk->mask) =3D=3D clk->value; +} + +static const struct clk_ops hi3798_clk_complex_ops =3D { + .prepare =3D hi3798_clk_complex_prepare, + .unprepare =3D hi3798_clk_complex_unprepare, + .is_prepared =3D hi3798_clk_complex_is_prepared, +}; + +static int hi3798_clk_register_complex(const struct hi3798_complex_clock *= clks, int nums, + struct hisi_clock_data *data) +{ + void __iomem *base =3D data->base; + int i; + int ret; + + for (i =3D 0; i < nums; i++) { + struct hi3798_clk_complex *p_clk; + struct clk *clk; + struct clk_init_data init; + + p_clk =3D kzalloc(sizeof(*p_clk), GFP_KERNEL); + if (!p_clk) { + ret =3D -ENOMEM; + goto err_kzalloc; + } + + init.name =3D clks[i].name; + init.ops =3D &hi3798_clk_complex_ops; + + init.flags =3D 0; + init.parent_names =3D + (clks[i].parent_name ? &clks[i].parent_name : NULL); + init.num_parents =3D (clks[i].parent_name ? 1 : 0); + + p_clk->reg =3D base + clks[i].offset; + p_clk->mask =3D clks[i].mask; + p_clk->value =3D clks[i].value; + p_clk->hw.init =3D &init; + + clk =3D clk_register(NULL, &p_clk->hw); + if (IS_ERR(clk)) { + kfree(p_clk); +err_kzalloc: + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + goto err; + } + + if (clks[i].alias) + clk_register_clkdev(clk, clks[i].alias, NULL); + + data->clk_data.clks[clks[i].id] =3D clk; + } + + return 0; + +err: + while (i--) + clk_unregister(data->clk_data.clks[clks[i].id]); + + return ret; +} + +static void hi3798_clk_unregister_complex(const struct hi3798_complex_cloc= k *clks, int nums, + struct hisi_clock_data *data) +{ + struct clk **clocks =3D data->clk_data.clks; + int i; + + for (i =3D 0; i < nums; i++) { + if (clocks[clks[i].id]) + clk_unregister(clocks[clks[i].id]); + } +} + struct hi3798_clks { const struct hisi_gate_clock *gate_clks; int gate_clks_nums; @@ -66,6 +193,8 @@ struct hi3798_clks { int mux_clks_nums; const struct hisi_phase_clock *phase_clks; int phase_clks_nums; + const struct hi3798_complex_clock *complex_clks; + int complex_clks_nums; }; =20 static struct hisi_clock_data *hi3798_clk_register( @@ -98,13 +227,19 @@ static struct hisi_clock_data *hi3798_clk_register( if (ret) goto unregister_mux; =20 + ret =3D hi3798_clk_register_complex(clks->complex_clks, clks->complex_clk= s_nums, clk_data); + if (ret) + goto unregister_gate; + ret =3D of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data->clk_data); if (ret) - goto unregister_gate; + goto unregister_complex; =20 return clk_data; =20 +unregister_complex: + hi3798_clk_unregister_complex(clks->complex_clks, clks->complex_clks_nums= , clk_data); unregister_gate: hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); unregister_mux: @@ -123,6 +258,7 @@ static void hi3798_clk_unregister( =20 of_clk_del_provider(pdev->dev.of_node); =20 + hi3798_clk_unregister_complex(clks->complex_clks, clks->complex_clks_nums= , crg->clk_data); hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_= data); hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, crg->clk_dat= a); hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, --=20 2.39.2 From nobody Mon Feb 9 23:44:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5B41C6FD1D for ; Mon, 20 Mar 2023 20:42:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230249AbjCTUmV (ORCPT ); Mon, 20 Mar 2023 16:42:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229677AbjCTUmO (ORCPT ); Mon, 20 Mar 2023 16:42:14 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0B7C1EBDF; Mon, 20 Mar 2023 13:41:32 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id x15so3137214pjk.2; Mon, 20 Mar 2023 13:41:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679344891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P1nihvRARKpi6tkVd5cEgKMlSNEP4XWbbAUmPmevZWQ=; b=a0HcIxFpIjo1lSgr+MxW8pudqshXcHw+BiPZWFvBtQqePhHvgvVEQVZdmnTDBmMDK7 CmY91u5/YP6ybN/4gdZa8q8Mgky1m5JbY7TEnEZvulms39aEHxjr7Gf+psuJinYYj9cj tQAAVEnc4BPk5+UErXx38+ddx4LMuOzQaHgrcnEVEkmD1KOxTkCCqgAEGWlyOb7pT4SK LH9Rs8k5OVkK8NEwmDJmgpHNxtKcCBuGfvxI4+gLk40kdj/ZBp/MpdPdAjQbjiscQZd4 BS0SF8pqdy9NPUsz8F4A8dlnswapEQueHbN8FdH3agnrJmmSH0HgmvtdrgUKAAgRryhY UHXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679344891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P1nihvRARKpi6tkVd5cEgKMlSNEP4XWbbAUmPmevZWQ=; b=ei/3sFtFHynA7Q8IIOVuBQd69OGvue3l/NSyT/M0lzf1MvboJMfCqUCWvCZ/JI+rG+ W4Cj35DMfanwiyY9zuFH+noJ6qSGaoFHC3QX830quLGZihZ/VaLvF6uH8ebaP7DwXZYC NGZXGuDH68wd0RTSuktNawsnZ2+19qqs+cah15wQm2FfjJzCKx3suqELsN9YLvQS46Ec n6iJbEJgICydnj3SxvJuwYsqjxNj1bqZm1+Hvw9LpvJMgf3SVvQnArTn9MffOLjkQ/uR oXxJSOK1H0oSerb8us5ItJbWK0aOEWUED0j9KT+m2PVam7Xvyy+TzyoiqpmEr9NLL34z rlIA== X-Gm-Message-State: AO0yUKUAyFu/8q6U+32qUcXxjCbSQ8rMJyAjfACTtZVIY+T8seQBNibt E84jvl+C9rndy1ZbnwWrI9M= X-Google-Smtp-Source: AK7set8RQR+fc+qe2esmHZrxVXZ0nOPF1zAz+mZWdv/urEMxOguZoqyh1B3Hr75AJXbELY1VcDLbxA== X-Received: by 2002:a17:90b:1a8e:b0:234:e3f:f53b with SMTP id ng14-20020a17090b1a8e00b002340e3ff53bmr454210pjb.21.1679344891331; Mon, 20 Mar 2023 13:41:31 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.202]) by smtp.gmail.com with ESMTPSA id c3-20020a17090aa60300b0023b29b464f9sm6580943pjq.27.2023.03.20.13.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 13:41:31 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org Subject: [PATCH v5 4/5] dt-bindings: clock: Add Hi3798MV100 CRG Date: Tue, 21 Mar 2023 04:40:37 +0800 Message-Id: <20230320204042.980708-5-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320204042.980708-1-mmyangfl@gmail.com> References: <20230320204042.980708-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add CRG bindings for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: David Yang Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/hisi-crg.txt | 2 ++ include/dt-bindings/clock/histb-clock.h | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documen= tation/devicetree/bindings/clock/hisi-crg.txt index cc60b3d42..972c038c8 100644 --- a/Documentation/devicetree/bindings/clock/hisi-crg.txt +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt @@ -13,6 +13,8 @@ Required Properties: - "hisilicon,hi3516cv300-crg" - "hisilicon,hi3516cv300-sysctrl" - "hisilicon,hi3519-crg" + - "hisilicon,hi3798mv100-crg" + - "hisilicon,hi3798mv100-sysctrl" - "hisilicon,hi3798cv200-crg" - "hisilicon,hi3798cv200-sysctrl" =20 diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/= clock/histb-clock.h index e64e5770a..126b1f839 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -58,6 +58,19 @@ #define HISTB_USB3_UTMI_CLK1 48 #define HISTB_USB3_PIPE_CLK1 49 #define HISTB_USB3_SUSPEND_CLK1 50 +#define HISTB_USB2_UTMI_CLK1 51 +#define HISTB_USB2_2_BUS_CLK 52 +#define HISTB_USB2_2_PHY_CLK 53 +#define HISTB_USB2_2_UTMI_CLK 54 +#define HISTB_USB2_2_UTMI_CLK1 55 +#define HISTB_USB2_2_12M_CLK 56 +#define HISTB_USB2_2_48M_CLK 57 +#define HISTB_USB2_2_OTG_UTMI_CLK 58 +#define HISTB_USB2_2_PHY1_REF_CLK 59 +#define HISTB_USB2_2_PHY2_REF_CLK 60 +#define HISTB_FEPHY_CLK 61 +#define HISTB_GPU_BUS_CLK 62 +#define HISTB_GPU_CORE_CLK 63 =20 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 --=20 2.39.2 From nobody Mon Feb 9 23:44:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2521C6FD1C for ; Mon, 20 Mar 2023 20:42:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229511AbjCTUmS (ORCPT ); Mon, 20 Mar 2023 16:42:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230475AbjCTUmH (ORCPT ); Mon, 20 Mar 2023 16:42:07 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 566A838E86; Mon, 20 Mar 2023 13:41:40 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id bc12so13245751plb.0; Mon, 20 Mar 2023 13:41:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679344899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FkALHQCFG+C3/6EbCgaqcXTs7mWkVNlDLK3Ss/73Xio=; b=W4Yd0ngbXSAWA1z1wsrPDzqsW8VfzLrvcB8JQT+UzfHcZhmtCmuMya4IodOpxrcJCZ pqj7xW5FDHUdaKP53t+ndZLfuJ/eDGpCnCDwQS5ZeHokJsCN9PP0MZXdK/9akuuMzOoN rL75rmgGDo99khmBW6E5GejOMTFGaK/RY/IcEkcqPE/pZRAdtPoNybfgX0JdsJYzmNm3 ZWamLXvnA3bOD7TaeV7W9AOSY5fdJ5kS/JUFa9mAHdEN3N9FLulloyEhYsXzA2uV2/cG P3IzwVDUcB/U+kQD7dpxUyB7E6poKkhd6lf5M3llFvkf/acptQPB1RWKc9Hv3/zwDzLE miZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679344899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FkALHQCFG+C3/6EbCgaqcXTs7mWkVNlDLK3Ss/73Xio=; b=K5t0h2PnysrAYIwX5l36lY30A1lC/8B2rSLtWFZ0ANH/ERywSq9ssqgn/qhnFRr+Sq 1FahqajqdQT/JIV7yVJUH/1vklk5j1wo7WZxXi5GG+mT9KlNW2FrWaceMdRWStOxo8Bf RQCJXy3cnLWkHtvQqQGE6xAeY7SEkrJHBI0iuC1EGF+oTZX1vQYk8IGTGZ3maSKle03k X7NJs3W5huJJc6mn1w/j4lDnyFHQd3aOTf5cjwHWM5nHygLUbA3KEfDtrEaAkD8NJtv8 cMj6GgHb7iq1O/l3PK3Aj2QM8sc6g/eWS20PdzV/B8UzZt+kRpQVuzaDu1LObHBP2oiP KOkw== X-Gm-Message-State: AO0yUKWya82oxFWYKEfCJropPHfAnSEbYnmA4UDnfcbf9A3tZq6eFEeD tLR6nSWMRt3y90bQHYlhJ5Q= X-Google-Smtp-Source: AK7set839vciAiWmLIKxjdCr5X0rWeZqktnXf2aoMMmh0LsA5sp/hxZPjH/oNhjZKCpYrIxuuslUcw== X-Received: by 2002:a17:90b:3e88:b0:234:b964:5703 with SMTP id rj8-20020a17090b3e8800b00234b9645703mr482092pjb.18.1679344899520; Mon, 20 Mar 2023 13:41:39 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.213.202]) by smtp.gmail.com with ESMTPSA id c3-20020a17090aa60300b0023b29b464f9sm6580943pjq.27.2023.03.20.13.41.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 13:41:39 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/5] clk: hisilicon: Add CRG driver for Hi3798MV100 SoC Date: Tue, 21 Mar 2023 04:40:38 +0800 Message-Id: <20230320204042.980708-6-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320204042.980708-1-mmyangfl@gmail.com> References: <20230320204042.980708-1-mmyangfl@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 203 +++++++++++++++++++++++++++-- 1 file changed, 189 insertions(+), 14 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg= -hi3798.c index 0b29c01c6..3a8d70b7c 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -40,6 +40,9 @@ #define HI3798_FIXED_166P5M 84 #define HI3798_SDIO0_MUX 85 #define HI3798_COMBPHY0_MUX 86 +#define HI3798_FIXED_3M 87 +#define HI3798_FIXED_15M 88 +#define HI3798_FIXED_83P3M 89 =20 #define HI3798_CRG_NR_CLKS 128 =20 @@ -47,13 +50,16 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_= rate_clks[] =3D { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, + { HI3798_FIXED_3M, "3m", NULL, 0, 3000000, }, { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_15M, "15m", NULL, 0, 15000000, }, { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_83P3M, "83p3m", NULL, 0, 83333333, }, { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, @@ -306,6 +312,183 @@ static void hi3798_sysctrl_clk_unregister( hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_= data); } =20 +/* hi3798MV100 */ + +static const char *const hi3798mv100_mmc_mux_p[] =3D { + "75m", "100m", "50m", "15m" }; +static u32 hi3798mv100_mmc_mux_table[] =3D {0, 1, 2, 3}; + +static struct hisi_mux_clock hi3798mv100_mux_clks[] =3D { + { HI3798_MMC_MUX, "mmc_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0xa0, 8, 2, 0, hi3798mv100_mmc_mux_table, }, + { HI3798_SDIO0_MUX, "sdio0_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0x9c, 8, 2, 0, hi3798mv100_mmc_mux_table, }, +}; + +static u32 mmc_phase_regvals[] =3D {0, 1, 2, 3, 4, 5, 6, 7}; +static u32 mmc_phase_degrees[] =3D {0, 45, 90, 135, 180, 225, 270, 315}; + +static struct hisi_phase_clock hi3798mv100_phase_clks[] =3D { + { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, + { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", + CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees, + mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, +}; + +static const struct hisi_gate_clock hi3798mv100_gate_clks[] =3D { + /* NAND */ + /* hi3798MV100 NAND driver does not get into mainline yet, + * expose these clocks when it gets ready */ + /* { HISTB_NAND_CLK, "clk_nand", "clk_apb", + CLK_SET_RATE_PARENT, 0x60, 0, 0, }, */ + /* UART */ + { HISTB_UART1_CLK, "clk_uart1", "3m", + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x68, 0, 0, }, + { HISTB_UART2_CLK, "clk_uart2", "83p3m", + CLK_SET_RATE_PARENT, 0x68, 4, 0, }, + /* I2C */ + { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, + { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, + { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, + /* SPI */ + { HISTB_SPI0_CLK, "clk_spi0", "clk_apb", + CLK_SET_RATE_PARENT, 0x70, 0, 0, }, + /* SDIO */ + { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", + CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, + { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", + CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, + /* EMMC */ + { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", + CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, + { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", + CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, + /* USB2 */ + { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, + { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m", + CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, + { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m", + CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, + { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m", + CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, + { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, + { HISTB_USB2_UTMI_CLK1, "clk_u2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0xb8, 6, 0 }, + { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 3, 0 }, + { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, + { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, + /* USB2 2 */ + { HISTB_USB2_2_BUS_CLK, "clk_u2_2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0x198, 0, 0, }, + { HISTB_USB2_2_PHY_CLK, "clk_u2_2_phy", "60m", + CLK_SET_RATE_PARENT, 0x198, 4, 0, }, + { HISTB_USB2_2_12M_CLK, "clk_u2_2_12m", "12m", + CLK_SET_RATE_PARENT, 0x198, 2, 0 }, + { HISTB_USB2_2_48M_CLK, "clk_u2_2_48m", "48m", + CLK_SET_RATE_PARENT, 0x198, 1, 0 }, + { HISTB_USB2_2_UTMI_CLK, "clk_u2_2_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 5, 0 }, + { HISTB_USB2_2_UTMI_CLK1, "clk_u2_2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0x198, 6, 0 }, + { HISTB_USB2_2_OTG_UTMI_CLK, "clk_u2_2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 3, 0 }, + { HISTB_USB2_2_PHY1_REF_CLK, "clk_u2_2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 0, 0 }, + { HISTB_USB2_2_PHY2_REF_CLK, "clk_u2_2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 2, 0 }, + /* USB3 */ + { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL, + CLK_SET_RATE_PARENT, 0xb0, 0, 0 }, + { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL, + CLK_SET_RATE_PARENT, 0xb0, 4, 0 }, + { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL, + CLK_SET_RATE_PARENT, 0xb0, 3, 0 }, + { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL, + CLK_SET_RATE_PARENT, 0xb0, 2, 0 }, + /* GPU */ + { HISTB_GPU_BUS_CLK, "clk_gpu", "200m", + CLK_SET_RATE_PARENT, 0xd4, 0, 0 }, + /* FEPHY */ + { HISTB_FEPHY_CLK, "clk_fephy", "25m", + CLK_SET_RATE_PARENT, 0x120, 0, 0, }, +}; + +static const struct hi3798_complex_clock hi3798mv100_complex_clks[] =3D { + { HISTB_ETH0_MAC_CLK, "clk_mac0", NULL, + CLK_SET_RATE_PARENT, 0xcc, 0xf, 0xb, }, + { HISTB_GPU_CORE_CLK, "clk_gpu_gp", "200m", + CLK_SET_RATE_PARENT, 0xd4, 0x700, 0x700, }, +}; + +static const struct hi3798_clks hi3798mv100_crg_clks =3D { + .gate_clks =3D hi3798mv100_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798mv100_gate_clks), + .mux_clks =3D hi3798mv100_mux_clks, + .mux_clks_nums =3D ARRAY_SIZE(hi3798mv100_mux_clks), + .phase_clks =3D hi3798mv100_phase_clks, + .phase_clks_nums =3D ARRAY_SIZE(hi3798mv100_phase_clks), + .complex_clks =3D hi3798mv100_complex_clks, + .complex_clks_nums =3D ARRAY_SIZE(hi3798mv100_complex_clks), +}; + +static struct hisi_clock_data *hi3798mv100_clk_register( + struct platform_device *pdev) +{ + return hi3798_clk_register(pdev, &hi3798mv100_crg_clks); +} + +static void hi3798mv100_clk_unregister(struct platform_device *pdev) +{ + hi3798_clk_unregister(pdev, &hi3798mv100_crg_clks); +} + +static const struct hisi_crg_funcs hi3798mv100_crg_funcs =3D { + .register_clks =3D hi3798mv100_clk_register, + .unregister_clks =3D hi3798mv100_clk_unregister, +}; + +static const struct hisi_gate_clock hi3798mv100_sysctrl_gate_clks[] =3D { + { HISTB_IR_CLK, "clk_ir", "24m", + CLK_SET_RATE_PARENT, 0x48, 4, 0, }, + { HISTB_TIMER01_CLK, "clk_timer01", "24m", + CLK_SET_RATE_PARENT, 0x48, 6, 0, }, + { HISTB_UART0_CLK, "clk_uart0", "83p3m", + CLK_SET_RATE_PARENT, 0x48, 12, 0, }, +}; + +static const struct hi3798_clks hi3798mv100_sysctrl_clks =3D { + .gate_clks =3D hi3798mv100_sysctrl_gate_clks, + .gate_clks_nums =3D ARRAY_SIZE(hi3798mv100_sysctrl_gate_clks), +}; + +static struct hisi_clock_data *hi3798mv100_sysctrl_clk_register( + struct platform_device *pdev) +{ + return hi3798_sysctrl_clk_register(pdev, &hi3798mv100_sysctrl_clks); +} + +static void hi3798mv100_sysctrl_clk_unregister(struct platform_device *pde= v) +{ + hi3798_sysctrl_clk_unregister(pdev, &hi3798mv100_sysctrl_clks); +} + +static const struct hisi_crg_funcs hi3798mv100_sysctrl_funcs =3D { + .register_clks =3D hi3798mv100_sysctrl_clk_register, + .unregister_clks =3D hi3798mv100_sysctrl_clk_unregister, +}; + /* hi3798CV200 */ =20 static const char *const hi3798cv200_mmc_mux_p[] =3D { @@ -335,18 +518,6 @@ static struct hisi_mux_clock hi3798cv200_mux_clks[] = =3D { 0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, }, }; =20 -static u32 mmc_phase_regvals[] =3D {0, 1, 2, 3, 4, 5, 6, 7}; -static u32 mmc_phase_degrees[] =3D {0, 45, 90, 135, 180, 225, 270, 315}; - -static struct hisi_phase_clock hi3798cv200_phase_clks[] =3D { - { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu", - CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees, - mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, - { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu", - CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees, - mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) }, -}; - static const struct hisi_gate_clock hi3798cv200_gate_clks[] =3D { /* UART */ { HISTB_UART2_CLK, "clk_uart2", "75m", @@ -448,8 +619,8 @@ static const struct hi3798_clks hi3798cv200_crg_clks = =3D { .gate_clks_nums =3D ARRAY_SIZE(hi3798cv200_gate_clks), .mux_clks =3D hi3798cv200_mux_clks, .mux_clks_nums =3D ARRAY_SIZE(hi3798cv200_mux_clks), - .phase_clks =3D hi3798cv200_phase_clks, - .phase_clks_nums =3D ARRAY_SIZE(hi3798cv200_phase_clks), + .phase_clks =3D hi3798mv100_phase_clks, + .phase_clks_nums =3D ARRAY_SIZE(hi3798mv100_phase_clks), }; =20 static struct hisi_clock_data *hi3798cv200_clk_register( @@ -499,6 +670,10 @@ static const struct hisi_crg_funcs hi3798cv200_sysctrl= _funcs =3D { }; =20 static const struct of_device_id hi3798_crg_match_table[] =3D { + { .compatible =3D "hisilicon,hi3798mv100-crg", + .data =3D &hi3798mv100_crg_funcs }, + { .compatible =3D "hisilicon,hi3798mv100-sysctrl", + .data =3D &hi3798mv100_sysctrl_funcs }, { .compatible =3D "hisilicon,hi3798cv200-crg", .data =3D &hi3798cv200_crg_funcs }, { .compatible =3D "hisilicon,hi3798cv200-sysctrl", --=20 2.39.2