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[88.13.29.106]) by smtp.gmail.com with ESMTPSA id iv16-20020a05600c549000b003ee1acdaf95sm847776wmb.36.2023.03.20.09.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 09:18:27 -0700 (PDT) From: Sergio Paracuellos To: linux-clk@vger.kernel.org Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de, john@phrozen.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, arinc.unal@arinc9.com Subject: [PATCH 01/10] dt: bindings: clock: add mtmips SoCs clock device tree binding documentation Date: Mon, 20 Mar 2023 17:18:14 +0100 Message-Id: <20230320161823.1424278-2-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230320161823.1424278-1-sergio.paracuellos@gmail.com> References: <20230320161823.1424278-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds device tree binding documentation for clocks and resets in the Mediatek MIPS and Ralink SOCs. This covers RT2880, RT3050, RT3052, RT3350, RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mtmips-clock.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mtmips-clock.ya= ml diff --git a/Documentation/devicetree/bindings/clock/mtmips-clock.yaml b/Do= cumentation/devicetree/bindings/clock/mtmips-clock.yaml new file mode 100644 index 000000000000..c92969ce231d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mtmips-clock.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mtmips-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MTMIPS SoCs Clock + +maintainers: + - Sergio Paracuellos + +description: | + MediaTek MIPS and Ralink SoCs have an XTAL from where the cpu clock is + provided as well as derived clocks for the bus and the peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + The clocks are provided inside a system controller node. + + This node is also a reset provider for all the peripherals. + +properties: + compatible: + items: + - enum: + - ralink,rt2880-sysc + - ralink,rt3050-sysc + - ralink,rt3052-sysc + - ralink,rt3352-sysc + - ralink,rt3883-sysc + - ralink,rt5350-sysc + - ralink,mt7620-sysc + - ralink,mt7620a-sysc + - ralink,mt7628-sysc + - ralink,mt7688-sysc + - ralink,rt2880-reset + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + description: + The first cell indicates the clock number. + const: 1 + + '#reset-cells': + description: + The first cell indicates the reset bit within the register. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + sysc: sysc@0 { + compatible =3D "ralink,rt5350-sysc", "syscon"; + reg =3D <0x0 0x100>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.25.1