From nobody Mon Feb 9 13:01:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CDFCC7618D for ; Mon, 20 Mar 2023 11:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229508AbjCTLgU (ORCPT ); Mon, 20 Mar 2023 07:36:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231219AbjCTLgL (ORCPT ); Mon, 20 Mar 2023 07:36:11 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79F9F1114A; Mon, 20 Mar 2023 04:35:23 -0700 (PDT) Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 20 Mar 2023 19:35:20 +0800 From: Yu Tu To: , , , , "Neil Armstrong" , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , "Martin Blumenstingl" CC: , , Yu Tu Subject: [PATCH V2] clk: meson: vid-pll-div: added meson_vid_pll_div_ops support Date: Mon, 20 Mar 2023 19:34:45 +0800 Message-ID: <20230320113445.17260-1-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.18.11.248] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the previous code only provides "ro_ops" for the vid_pll_div clock. In fact, the clock can be set. So add "ops" that can set the clock, especially for later chips like S4 SOC and so on. Signed-off-by: Yu Tu --- drivers/clk/meson/vid-pll-div.c | 67 +++++++++++++++++++++++++++++++++ drivers/clk/meson/vid-pll-div.h | 3 ++ 2 files changed, 70 insertions(+) diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-di= v.c index daff235bc763..3c9015944f24 100644 --- a/drivers/clk/meson/vid-pll-div.c +++ b/drivers/clk/meson/vid-pll-div.c @@ -89,6 +89,73 @@ static unsigned long meson_vid_pll_div_recalc_rate(struc= t clk_hw *hw, return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider); } =20 +static int meson_vid_pll_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long parent_rate, best =3D 0, now =3D 0, rate; + unsigned long parent_rate_saved =3D req->best_parent_rate; + unsigned int i, best_i =3D 0; + + for (i =3D 0 ; i < VID_PLL_DIV_TABLE_SIZE; ++i) { + rate =3D DIV_ROUND_CLOSEST_ULL(req->rate * vid_pll_div_table[i].divider, + vid_pll_div_table[i].multiplier); + if (parent_rate_saved =3D=3D rate) { + req->best_parent_rate =3D parent_rate_saved; + best_i =3D i; + break; + } + + parent_rate =3D clk_hw_round_rate(req->best_parent_hw, rate); + now =3D DIV_ROUND_CLOSEST_ULL(parent_rate * + vid_pll_div_table[i].multiplier, + vid_pll_div_table[i].divider); + if (abs(now - req->rate) < abs(best - req->rate)) { + best =3D now; + best_i =3D i; + req->best_parent_rate =3D parent_rate; + } + } + + req->rate =3D DIV_ROUND_CLOSEST_ULL(req->best_parent_rate * + vid_pll_div_table[best_i].multiplier, + vid_pll_div_table[best_i].divider); + + return 0; +} + +static int meson_vid_pll_div_set_rate(struct clk_hw *hw, unsigned long rat= e, + unsigned long parent_rate) +{ + struct clk_regmap *clk =3D to_clk_regmap(hw); + struct meson_vid_pll_div_data *pll_div =3D meson_vid_pll_div_data(clk); + unsigned long best =3D 0, now =3D 0; + unsigned int i, best_i =3D 0; + + for (i =3D 0 ; i < VID_PLL_DIV_TABLE_SIZE; ++i) { + now =3D DIV_ROUND_CLOSEST_ULL(parent_rate * vid_pll_div_table[i].multipl= ier, + vid_pll_div_table[i].divider); + if (now =3D=3D rate) { + best_i =3D i; + break; + } else if (abs(now - rate) < abs(best - rate)) { + best =3D now; + best_i =3D i; + } + } + + meson_parm_write(clk->map, &pll_div->val, vid_pll_div_table[best_i].shift= _val); + meson_parm_write(clk->map, &pll_div->sel, vid_pll_div_table[best_i].shift= _sel); + + return 0; +} + +const struct clk_ops meson_vid_pll_div_ops =3D { + .recalc_rate =3D meson_vid_pll_div_recalc_rate, + .determine_rate =3D meson_vid_pll_div_determine_rate, + .set_rate =3D meson_vid_pll_div_set_rate, +}; +EXPORT_SYMBOL_GPL(meson_vid_pll_div_ops); + const struct clk_ops meson_vid_pll_div_ro_ops =3D { .recalc_rate =3D meson_vid_pll_div_recalc_rate, }; diff --git a/drivers/clk/meson/vid-pll-div.h b/drivers/clk/meson/vid-pll-di= v.h index c0128e33ccf9..bbccab340910 100644 --- a/drivers/clk/meson/vid-pll-div.h +++ b/drivers/clk/meson/vid-pll-div.h @@ -10,11 +10,14 @@ #include #include "parm.h" =20 +#define VID_PLL_DIV_TABLE_SIZE 14 + struct meson_vid_pll_div_data { struct parm val; struct parm sel; }; =20 extern const struct clk_ops meson_vid_pll_div_ro_ops; +extern const struct clk_ops meson_vid_pll_div_ops; =20 #endif /* __MESON_VID_PLL_DIV_H */ --=20 2.33.1