From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D140C76196 for ; Fri, 17 Mar 2023 21:30:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230263AbjCQVah (ORCPT ); Fri, 17 Mar 2023 17:30:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230116AbjCQVa3 (ORCPT ); Fri, 17 Mar 2023 17:30:29 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B83C547838; Fri, 17 Mar 2023 14:30:20 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id h8so25391049ede.8; Fri, 17 Mar 2023 14:30:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MnURxZI1suPSaEDTpxd+ifaQ2eMQxg73RycWrn38PLc=; b=Jj5cHoXuo5vzuSHuaVZbpDptwdnrQJOqG+lrz4fpGuSjXLn511bCvc6l8wzjYv/GF6 u1TlV+M9HKoSnT4HMg6PS5ZxqLlxUFNZKU7utAqqRzKzOXCqzDj3U5t02bIc6mb3VidN pBW+3W+37SarmpO6Qxe6gcwthXBTP6jUQQCDNfCOONMh8AaaQ2//fQ+Bdf1ktP2zhLhd dOTNWt5E6g/GnJrVTkvtAhqni2yaeijzNzWNYs3/HqUMY6kyABLhbHhDVuTonjK3RVoz i/wTryiWHA/rysxTvmicxdS/hcEu3vw375vYj00x/rarTD7vseoHWikl2Zpkwj+LRzZ/ pZxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MnURxZI1suPSaEDTpxd+ifaQ2eMQxg73RycWrn38PLc=; b=2B3r+UJggSgL4csRjmnNn3rO6Zq+vYA9H54zMvRUdxTLlAe63vI4okXX84eDoJZtpH ybGyHO/DyLEl/tD5eeuPJWVK/ORzcCWh4kJ5AR+/ke3LpWPgWtmNoq8LglbzN3wImSDg W8jMSotsIbwLDZQgVmonf17Ngb/4ZrRD7K6tYmeZI8nxCHU7UotRix7DYpFemAY+Y6do Wp0NIwjq+PJ5Gpjw3E0XBOL/1jxuIQI24Ez8gkZ0MigfkPMLmUOWgBMvrXimycH2vthy kIwiJi4b5fvRs5GlzYCc+qrn/j3tPfX0lVViTFfJFC85vesBe5n5HZc8wRFd0kK8UVqu y+sw== X-Gm-Message-State: AO0yUKWVWnJmSOs1RRn0VPdtqYvlsc+gPN75CT2PaD9n4rgidN3fMeq9 qwlrb4x7pIPqCTiBYQKv4jw= X-Google-Smtp-Source: AK7set8RLsaF8wDQPtds1b75SoWVe0h8Xb0S/esh2wCPRjjFFANgtzOE/9FwEcwd2mV/vp5opNVNpg== X-Received: by 2002:a17:906:2dd3:b0:931:52d4:1b7c with SMTP id h19-20020a1709062dd300b0093152d41b7cmr725214eji.62.1679088619024; Fri, 17 Mar 2023 14:30:19 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:18 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 01/21] pinctrl: ralink: reintroduce ralink,rt2880-pinmux compatible string Date: Sat, 18 Mar 2023 00:29:51 +0300 Message-Id: <20230317213011.13656-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There have been stable releases with the ralink,rt2880-pinmux compatible string included. Having it removed breaks the ABI. Reintroduce it. Fixes: e5981cd46183 ("pinctrl: ralink: add new compatible strings for each = pinctrl subdriver") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 1 + drivers/pinctrl/ralink/pinctrl-mt7621.c | 1 + drivers/pinctrl/ralink/pinctrl-rt2880.c | 1 + drivers/pinctrl/ralink/pinctrl-rt305x.c | 1 + drivers/pinctrl/ralink/pinctrl-rt3883.c | 1 + 5 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/rali= nk/pinctrl-mt7620.c index 4e8d26bb3430..06b86c726839 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -372,6 +372,7 @@ static int mt7620_pinctrl_probe(struct platform_device = *pdev) =20 static const struct of_device_id mt7620_pinctrl_match[] =3D { { .compatible =3D "ralink,mt7620-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/rali= nk/pinctrl-mt7621.c index eddc0ba6d468..fb5824922e78 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -97,6 +97,7 @@ static int mt7621_pinctrl_probe(struct platform_device *p= dev) =20 static const struct of_device_id mt7621_pinctrl_match[] =3D { { .compatible =3D "ralink,mt7621-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/rali= nk/pinctrl-rt2880.c index 3e2f1aaaf095..d7a65fcc7755 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -41,6 +41,7 @@ static int rt2880_pinctrl_probe(struct platform_device *p= dev) =20 static const struct of_device_id rt2880_pinctrl_match[] =3D { { .compatible =3D "ralink,rt2880-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/rali= nk/pinctrl-rt305x.c index bdaee5ce1ee0..f6092c64383e 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,7 @@ static int rt305x_pinctrl_probe(struct platform_device = *pdev) =20 static const struct of_device_id rt305x_pinctrl_match[] =3D { { .compatible =3D "ralink,rt305x-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/rali= nk/pinctrl-rt3883.c index 392208662355..5f766d76bafa 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -88,6 +88,7 @@ static int rt3883_pinctrl_probe(struct platform_device *p= dev) =20 static const struct of_device_id rt3883_pinctrl_match[] =3D { { .compatible =3D "ralink,rt3883-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match); --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CEBFC74A5B for ; Fri, 17 Mar 2023 21:30:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230318AbjCQVak (ORCPT ); Fri, 17 Mar 2023 17:30:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230317AbjCQVab (ORCPT ); Fri, 17 Mar 2023 17:30:31 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 133A84D433; Fri, 17 Mar 2023 14:30:23 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id cy23so25344398edb.12; Fri, 17 Mar 2023 14:30:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GPpFzY0H3ocypf25nzBsMZcz2jHpyh97I8lhoOmDtHQ=; b=Oa1shaEabrkzIwGb8LHYQAFL4Ho6oDqeN2TfX7YQ2U+J6nE9MJnwxk8BJXu/Yz7QrR 7y4b/1bBpU9uhFTVwl4aWiA/sjp7Dng38gIR2xBRj6c36Tvu0R3RcnKdVQrivH/plen3 fMVh5DVPROQHh7Q9m7pRrOTRKAGzZPVymRJ938lDQtpMLljFcx3OZrkhJgsosj2Qdkn/ SUTuqYHb6E+DLx7D9cm13g3Sm4ywaP7+gaBnmweMm7BRPWstbU1Hwe6zxnmNn9hC9BQW smH1zpvxq5MnPxx1x0pe0W+V988tQMmRuvKrQ5d3RsrL7F4w9XPwhSkP/8tElKFliT6I DVzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GPpFzY0H3ocypf25nzBsMZcz2jHpyh97I8lhoOmDtHQ=; b=rW5ICduGZ7LRkzJ/53WE2Gu8EqvsfdOzmpYZaS/D0i1fw6Ha/HBxKnu8S6dm7HWTpv dOwtr/9jnTWvUhifYClONH4LLKEPoO2KhYUPcvEUhS6U7Rl2mgAn2EKHAI49NZ+/81CW tsG34mf5Oceql5t1uUa2Xky9FNE0tYHj8cnyD/o3dNnpciRJqVqJP/xXBwtL/VqxQaPq LMxUNqyhXhRtaqbbX+bYzdO52trbmeO0KU96kDKYCqCxgiTrkNNozjtjIez1cgde9x27 wAYFhdT1lLDuc7pdAWexJiY6v6Hz9Rt11s4yGmbWY4ZHj8VF6MSIksnUoLB6KE2xv0Il V0vg== X-Gm-Message-State: AO0yUKXrluuG1ip7U/ITQAtNeJdgTzebrnwhXUzJNi7RZNZvTkRYy1np ocVi0lNGUV7ShCyWIBwIydA5Q2hic93gxyz8 X-Google-Smtp-Source: AK7set+tHHmi6qkolpcnuJDFVW4c6/ogWFo+Kv7rhpvUnOMQvShD3seRfaKPclm53t3IOgVIbOkX8A== X-Received: by 2002:aa7:cfc8:0:b0:4fc:73dc:5def with SMTP id r8-20020aa7cfc8000000b004fc73dc5defmr3832240edy.41.1679088621453; Fri, 17 Mar 2023 14:30:21 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:21 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 02/21] pinctrl: ralink: rt305x: add new compatible string for every SoC Date: Sat, 18 Mar 2023 00:29:52 +0300 Message-Id: <20230317213011.13656-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add new compatible strings to make every SoC, or SoCs that use the same pinmux data have a unique compatible string. This ensures that the pin muxing information of every SoC, or a set of SoCs that use the same pinmux data can be properly documented. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-rt305x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/rali= nk/pinctrl-rt305x.c index f6092c64383e..fa3743c7680f 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,8 @@ static int rt305x_pinctrl_probe(struct platform_device = *pdev) =20 static const struct of_device_id rt305x_pinctrl_match[] =3D { { .compatible =3D "ralink,rt305x-pinctrl" }, + { .compatible =3D "ralink,rt3352-pinctrl" }, + { .compatible =3D "ralink,rt5350-pinctrl" }, { .compatible =3D "ralink,rt2880-pinmux" }, {} }; --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADE8DC74A5B for ; Fri, 17 Mar 2023 21:30:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230377AbjCQVao (ORCPT ); Fri, 17 Mar 2023 17:30:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbjCQVad (ORCPT ); Fri, 17 Mar 2023 17:30:33 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCFFFEC74; Fri, 17 Mar 2023 14:30:25 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id fd5so25398016edb.7; Fri, 17 Mar 2023 14:30:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eZtcbxuenv5Hgd7He4MoaSBQyHio/C6M7ta0+avs8ds=; b=WSrV0fU2m5Wh2diMnpwUZhBdMSnmoYqbGIs54XQGgoWlnmvkJ2cX92tfz3O56F/nhQ 0qRtyTeJNF2AxGKwb/Eu9JQlB81bz1eOBJ0gKeEEPfDJuuBxGt/FZ7JWJEn768BIYYU9 rVhH9A2L753/4X/90Wgm17ZQUz5yEjjKkKenwrWa4CPZN+4SjggMPWZiqCECKXt4Mqa2 lGUJnzWog8MHFH/++4NEA3fjk3591g8imDpjSiLekbonj0ROx1VQcIO71dl92MT9p1aJ p/+10PYgiibNPEKmY1XRseE2jVJcjHBT7jA/4B6xAdh65i1tlDgZ0SaTFzQwCqBwx+8g J0UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eZtcbxuenv5Hgd7He4MoaSBQyHio/C6M7ta0+avs8ds=; b=SSKz9hDJZ4hiSslQ+N1wJ0QyDoaTgYK2s3p0kro1ruXyNTEviXJPvxCx2ZO+B+mxBx iIbHeMKCVTpXJ/NyP8NNIGyxsYdmXCwPmUYtIlPAOn0w0fjHAB+kxoX/jp34BDeWsHBx zWs/bjVzoesbWOkQzCaNltwa4kFe5S4pAdI8gMX0S6P4PCG/URaygEYUmsGLetVhzOp4 RNzMKyp3kBYRSVZA4bERjPxyOlRMFS3yhGpG1YfyararaT3EsedTuStHNEWtABejuuP2 jL/Qax9fMRHHonaB+Fm1NcvXdNsNq4kLMdSV8sYJIiX46rLV/TC9Wu5EEfiJ3p0JJ5K7 zkOw== X-Gm-Message-State: AO0yUKW8ZMOy/HBNg5jJnkktwYqVgpfmuCdjcSEIdS93aMmWaPQ38mPi J6oxJ7damKMH96beDTHTjeo= X-Google-Smtp-Source: AK7set+G4AmnAACcS2WO8v3IH0Z01X8prMZl4wEN2qCqWv+fKNTfOjF0G3frWV05Z7c3GhxRrVQj1Q== X-Received: by 2002:a17:907:381:b0:88f:9c29:d232 with SMTP id ss1-20020a170907038100b0088f9c29d232mr768885ejb.57.1679088624077; Fri, 17 Mar 2023 14:30:24 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:23 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 03/21] pinctrl: ralink: mt7620: split out to mt76x8 Date: Sat, 18 Mar 2023 00:29:53 +0300 Message-Id: <20230317213011.13656-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Split the driver out to pinctrl-mt76x8.c. Remove including the unnecessary headers since is_mt76x8() is not being used anymore. Introduce a new compatible string to be able to document the pin muxing information properly. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Sergio Paracuellos --- drivers/pinctrl/ralink/Kconfig | 5 + drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-mt7620.c | 257 +-------------------- drivers/pinctrl/ralink/pinctrl-mt76x8.c | 283 ++++++++++++++++++++++++ 4 files changed, 290 insertions(+), 256 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-mt76x8.c diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 1e4c5e43d69b..c5fe4c31aaea 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -17,6 +17,11 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RALINK =20 +config PINCTRL_MT76X8 + bool "MT76X8 pinctrl subdriver" + depends on RALINK && SOC_MT7620 + select PINCTRL_RALINK + config PINCTRL_RT2880 bool "RT2880 pinctrl subdriver" depends on RALINK && SOC_RT288X diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makef= ile index 0ebbe552526d..be9acf2e27fd 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_RALINK) +=3D pinctrl-ralink.o =20 obj-$(CONFIG_PINCTRL_MT7620) +=3D pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) +=3D pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) +=3D pinctrl-mt76x8.o obj-$(CONFIG_PINCTRL_RT2880) +=3D pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_RT305X) +=3D pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) +=3D pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/rali= nk/pinctrl-mt7620.c index 06b86c726839..3f6ffccc6882 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only =20 -#include -#include #include #include #include @@ -112,262 +110,9 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = =3D { { 0 } }; =20 -static struct ralink_pmx_func pwm1_grp_mt76x8[] =3D { - FUNC("sdxc d6", 3, 19, 1), - FUNC("utif", 2, 19, 1), - FUNC("gpio", 1, 19, 1), - FUNC("pwm1", 0, 19, 1), -}; - -static struct ralink_pmx_func pwm0_grp_mt76x8[] =3D { - FUNC("sdxc d7", 3, 18, 1), - FUNC("utif", 2, 18, 1), - FUNC("gpio", 1, 18, 1), - FUNC("pwm0", 0, 18, 1), -}; - -static struct ralink_pmx_func uart2_grp_mt76x8[] =3D { - FUNC("sdxc d5 d4", 3, 20, 2), - FUNC("pwm", 2, 20, 2), - FUNC("gpio", 1, 20, 2), - FUNC("uart2", 0, 20, 2), -}; - -static struct ralink_pmx_func uart1_grp_mt76x8[] =3D { - FUNC("sw_r", 3, 45, 2), - FUNC("pwm", 2, 45, 2), - FUNC("gpio", 1, 45, 2), - FUNC("uart1", 0, 45, 2), -}; - -static struct ralink_pmx_func i2c_grp_mt76x8[] =3D { - FUNC("-", 3, 4, 2), - FUNC("debug", 2, 4, 2), - FUNC("gpio", 1, 4, 2), - FUNC("i2c", 0, 4, 2), -}; - -static struct ralink_pmx_func refclk_grp_mt76x8[] =3D { FUNC("refclk", 0, = 37, 1) }; -static struct ralink_pmx_func perst_grp_mt76x8[] =3D { FUNC("perst", 0, 36= , 1) }; -static struct ralink_pmx_func wdt_grp_mt76x8[] =3D { FUNC("wdt", 0, 38, 1)= }; -static struct ralink_pmx_func spi_grp_mt76x8[] =3D { FUNC("spi", 0, 7, 4) = }; - -static struct ralink_pmx_func sd_mode_grp_mt76x8[] =3D { - FUNC("jtag", 3, 22, 8), - FUNC("utif", 2, 22, 8), - FUNC("gpio", 1, 22, 8), - FUNC("sdxc", 0, 22, 8), -}; - -static struct ralink_pmx_func uart0_grp_mt76x8[] =3D { - FUNC("-", 3, 12, 2), - FUNC("-", 2, 12, 2), - FUNC("gpio", 1, 12, 2), - FUNC("uart0", 0, 12, 2), -}; - -static struct ralink_pmx_func i2s_grp_mt76x8[] =3D { - FUNC("antenna", 3, 0, 4), - FUNC("pcm", 2, 0, 4), - FUNC("gpio", 1, 0, 4), - FUNC("i2s", 0, 0, 4), -}; - -static struct ralink_pmx_func spi_cs1_grp_mt76x8[] =3D { - FUNC("-", 3, 6, 1), - FUNC("refclk", 2, 6, 1), - FUNC("gpio", 1, 6, 1), - FUNC("spi cs1", 0, 6, 1), -}; - -static struct ralink_pmx_func spis_grp_mt76x8[] =3D { - FUNC("pwm_uart2", 3, 14, 4), - FUNC("utif", 2, 14, 4), - FUNC("gpio", 1, 14, 4), - FUNC("spis", 0, 14, 4), -}; - -static struct ralink_pmx_func gpio_grp_mt76x8[] =3D { - FUNC("pcie", 3, 11, 1), - FUNC("refclk", 2, 11, 1), - FUNC("gpio", 1, 11, 1), - FUNC("gpio", 0, 11, 1), -}; - -static struct ralink_pmx_func p4led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 30, 1), - FUNC("utif", 2, 30, 1), - FUNC("gpio", 1, 30, 1), - FUNC("p4led_kn", 0, 30, 1), -}; - -static struct ralink_pmx_func p3led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 31, 1), - FUNC("utif", 2, 31, 1), - FUNC("gpio", 1, 31, 1), - FUNC("p3led_kn", 0, 31, 1), -}; - -static struct ralink_pmx_func p2led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 32, 1), - FUNC("utif", 2, 32, 1), - FUNC("gpio", 1, 32, 1), - FUNC("p2led_kn", 0, 32, 1), -}; - -static struct ralink_pmx_func p1led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 33, 1), - FUNC("utif", 2, 33, 1), - FUNC("gpio", 1, 33, 1), - FUNC("p1led_kn", 0, 33, 1), -}; - -static struct ralink_pmx_func p0led_kn_grp_mt76x8[] =3D { - FUNC("jtag", 3, 34, 1), - FUNC("rsvd", 2, 34, 1), - FUNC("gpio", 1, 34, 1), - FUNC("p0led_kn", 0, 34, 1), -}; - -static struct ralink_pmx_func wled_kn_grp_mt76x8[] =3D { - FUNC("rsvd", 3, 35, 1), - FUNC("rsvd", 2, 35, 1), - FUNC("gpio", 1, 35, 1), - FUNC("wled_kn", 0, 35, 1), -}; - -static struct ralink_pmx_func p4led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 39, 1), - FUNC("utif", 2, 39, 1), - FUNC("gpio", 1, 39, 1), - FUNC("p4led_an", 0, 39, 1), -}; - -static struct ralink_pmx_func p3led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 40, 1), - FUNC("utif", 2, 40, 1), - FUNC("gpio", 1, 40, 1), - FUNC("p3led_an", 0, 40, 1), -}; - -static struct ralink_pmx_func p2led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 41, 1), - FUNC("utif", 2, 41, 1), - FUNC("gpio", 1, 41, 1), - FUNC("p2led_an", 0, 41, 1), -}; - -static struct ralink_pmx_func p1led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 42, 1), - FUNC("utif", 2, 42, 1), - FUNC("gpio", 1, 42, 1), - FUNC("p1led_an", 0, 42, 1), -}; - -static struct ralink_pmx_func p0led_an_grp_mt76x8[] =3D { - FUNC("jtag", 3, 43, 1), - FUNC("rsvd", 2, 43, 1), - FUNC("gpio", 1, 43, 1), - FUNC("p0led_an", 0, 43, 1), -}; - -static struct ralink_pmx_func wled_an_grp_mt76x8[] =3D { - FUNC("rsvd", 3, 44, 1), - FUNC("rsvd", 2, 44, 1), - FUNC("gpio", 1, 44, 1), - FUNC("wled_an", 0, 44, 1), -}; - -#define MT76X8_GPIO_MODE_MASK 0x3 - -#define MT76X8_GPIO_MODE_P4LED_KN 58 -#define MT76X8_GPIO_MODE_P3LED_KN 56 -#define MT76X8_GPIO_MODE_P2LED_KN 54 -#define MT76X8_GPIO_MODE_P1LED_KN 52 -#define MT76X8_GPIO_MODE_P0LED_KN 50 -#define MT76X8_GPIO_MODE_WLED_KN 48 -#define MT76X8_GPIO_MODE_P4LED_AN 42 -#define MT76X8_GPIO_MODE_P3LED_AN 40 -#define MT76X8_GPIO_MODE_P2LED_AN 38 -#define MT76X8_GPIO_MODE_P1LED_AN 36 -#define MT76X8_GPIO_MODE_P0LED_AN 34 -#define MT76X8_GPIO_MODE_WLED_AN 32 -#define MT76X8_GPIO_MODE_PWM1 30 -#define MT76X8_GPIO_MODE_PWM0 28 -#define MT76X8_GPIO_MODE_UART2 26 -#define MT76X8_GPIO_MODE_UART1 24 -#define MT76X8_GPIO_MODE_I2C 20 -#define MT76X8_GPIO_MODE_REFCLK 18 -#define MT76X8_GPIO_MODE_PERST 16 -#define MT76X8_GPIO_MODE_WDT 14 -#define MT76X8_GPIO_MODE_SPI 12 -#define MT76X8_GPIO_MODE_SDMODE 10 -#define MT76X8_GPIO_MODE_UART0 8 -#define MT76X8_GPIO_MODE_I2S 6 -#define MT76X8_GPIO_MODE_CS1 4 -#define MT76X8_GPIO_MODE_SPIS 2 -#define MT76X8_GPIO_MODE_GPIO 0 - -static struct ralink_pmx_group mt76x8_pinmux_data[] =3D { - GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt76x8, 1, MT76X8_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt76x8, 1, MT76X8_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt76x8, 1, MT76X8_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_KN), - { 0 } -}; - static int mt7620_pinctrl_probe(struct platform_device *pdev) { - if (is_mt76x8()) - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); - else - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); } =20 static const struct of_device_id mt7620_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/rali= nk/pinctrl-mt76x8.c new file mode 100644 index 000000000000..4283a54d2db0 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-mt76x8.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include "pinctrl-ralink.h" + +#define MT76X8_GPIO_MODE_MASK 0x3 + +#define MT76X8_GPIO_MODE_P4LED_KN 58 +#define MT76X8_GPIO_MODE_P3LED_KN 56 +#define MT76X8_GPIO_MODE_P2LED_KN 54 +#define MT76X8_GPIO_MODE_P1LED_KN 52 +#define MT76X8_GPIO_MODE_P0LED_KN 50 +#define MT76X8_GPIO_MODE_WLED_KN 48 +#define MT76X8_GPIO_MODE_P4LED_AN 42 +#define MT76X8_GPIO_MODE_P3LED_AN 40 +#define MT76X8_GPIO_MODE_P2LED_AN 38 +#define MT76X8_GPIO_MODE_P1LED_AN 36 +#define MT76X8_GPIO_MODE_P0LED_AN 34 +#define MT76X8_GPIO_MODE_WLED_AN 32 +#define MT76X8_GPIO_MODE_PWM1 30 +#define MT76X8_GPIO_MODE_PWM0 28 +#define MT76X8_GPIO_MODE_UART2 26 +#define MT76X8_GPIO_MODE_UART1 24 +#define MT76X8_GPIO_MODE_I2C 20 +#define MT76X8_GPIO_MODE_REFCLK 18 +#define MT76X8_GPIO_MODE_PERST 16 +#define MT76X8_GPIO_MODE_WDT 14 +#define MT76X8_GPIO_MODE_SPI 12 +#define MT76X8_GPIO_MODE_SDMODE 10 +#define MT76X8_GPIO_MODE_UART0 8 +#define MT76X8_GPIO_MODE_I2S 6 +#define MT76X8_GPIO_MODE_CS1 4 +#define MT76X8_GPIO_MODE_SPIS 2 +#define MT76X8_GPIO_MODE_GPIO 0 + +static struct ralink_pmx_func pwm1_grp[] =3D { + FUNC("sdxc d6", 3, 19, 1), + FUNC("utif", 2, 19, 1), + FUNC("gpio", 1, 19, 1), + FUNC("pwm1", 0, 19, 1), +}; + +static struct ralink_pmx_func pwm0_grp[] =3D { + FUNC("sdxc d7", 3, 18, 1), + FUNC("utif", 2, 18, 1), + FUNC("gpio", 1, 18, 1), + FUNC("pwm0", 0, 18, 1), +}; + +static struct ralink_pmx_func uart2_grp[] =3D { + FUNC("sdxc d5 d4", 3, 20, 2), + FUNC("pwm", 2, 20, 2), + FUNC("gpio", 1, 20, 2), + FUNC("uart2", 0, 20, 2), +}; + +static struct ralink_pmx_func uart1_grp[] =3D { + FUNC("sw_r", 3, 45, 2), + FUNC("pwm", 2, 45, 2), + FUNC("gpio", 1, 45, 2), + FUNC("uart1", 0, 45, 2), +}; + +static struct ralink_pmx_func i2c_grp[] =3D { + FUNC("-", 3, 4, 2), + FUNC("debug", 2, 4, 2), + FUNC("gpio", 1, 4, 2), + FUNC("i2c", 0, 4, 2), +}; + +static struct ralink_pmx_func refclk_grp[] =3D { FUNC("refclk", 0, 37, 1) = }; +static struct ralink_pmx_func perst_grp[] =3D { FUNC("perst", 0, 36, 1) }; +static struct ralink_pmx_func wdt_grp[] =3D { FUNC("wdt", 0, 38, 1) }; +static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 7, 4) }; + +static struct ralink_pmx_func sd_mode_grp[] =3D { + FUNC("jtag", 3, 22, 8), + FUNC("utif", 2, 22, 8), + FUNC("gpio", 1, 22, 8), + FUNC("sdxc", 0, 22, 8), +}; + +static struct ralink_pmx_func uart0_grp[] =3D { + FUNC("-", 3, 12, 2), + FUNC("-", 2, 12, 2), + FUNC("gpio", 1, 12, 2), + FUNC("uart0", 0, 12, 2), +}; + +static struct ralink_pmx_func i2s_grp[] =3D { + FUNC("antenna", 3, 0, 4), + FUNC("pcm", 2, 0, 4), + FUNC("gpio", 1, 0, 4), + FUNC("i2s", 0, 0, 4), +}; + +static struct ralink_pmx_func spi_cs1_grp[] =3D { + FUNC("-", 3, 6, 1), + FUNC("refclk", 2, 6, 1), + FUNC("gpio", 1, 6, 1), + FUNC("spi cs1", 0, 6, 1), +}; + +static struct ralink_pmx_func spis_grp[] =3D { + FUNC("pwm_uart2", 3, 14, 4), + FUNC("utif", 2, 14, 4), + FUNC("gpio", 1, 14, 4), + FUNC("spis", 0, 14, 4), +}; + +static struct ralink_pmx_func gpio_grp[] =3D { + FUNC("pcie", 3, 11, 1), + FUNC("refclk", 2, 11, 1), + FUNC("gpio", 1, 11, 1), + FUNC("gpio", 0, 11, 1), +}; + +static struct ralink_pmx_func p4led_kn_grp[] =3D { + FUNC("jtag", 3, 30, 1), + FUNC("utif", 2, 30, 1), + FUNC("gpio", 1, 30, 1), + FUNC("p4led_kn", 0, 30, 1), +}; + +static struct ralink_pmx_func p3led_kn_grp[] =3D { + FUNC("jtag", 3, 31, 1), + FUNC("utif", 2, 31, 1), + FUNC("gpio", 1, 31, 1), + FUNC("p3led_kn", 0, 31, 1), +}; + +static struct ralink_pmx_func p2led_kn_grp[] =3D { + FUNC("jtag", 3, 32, 1), + FUNC("utif", 2, 32, 1), + FUNC("gpio", 1, 32, 1), + FUNC("p2led_kn", 0, 32, 1), +}; + +static struct ralink_pmx_func p1led_kn_grp[] =3D { + FUNC("jtag", 3, 33, 1), + FUNC("utif", 2, 33, 1), + FUNC("gpio", 1, 33, 1), + FUNC("p1led_kn", 0, 33, 1), +}; + +static struct ralink_pmx_func p0led_kn_grp[] =3D { + FUNC("jtag", 3, 34, 1), + FUNC("rsvd", 2, 34, 1), + FUNC("gpio", 1, 34, 1), + FUNC("p0led_kn", 0, 34, 1), +}; + +static struct ralink_pmx_func wled_kn_grp[] =3D { + FUNC("rsvd", 3, 35, 1), + FUNC("rsvd", 2, 35, 1), + FUNC("gpio", 1, 35, 1), + FUNC("wled_kn", 0, 35, 1), +}; + +static struct ralink_pmx_func p4led_an_grp[] =3D { + FUNC("jtag", 3, 39, 1), + FUNC("utif", 2, 39, 1), + FUNC("gpio", 1, 39, 1), + FUNC("p4led_an", 0, 39, 1), +}; + +static struct ralink_pmx_func p3led_an_grp[] =3D { + FUNC("jtag", 3, 40, 1), + FUNC("utif", 2, 40, 1), + FUNC("gpio", 1, 40, 1), + FUNC("p3led_an", 0, 40, 1), +}; + +static struct ralink_pmx_func p2led_an_grp[] =3D { + FUNC("jtag", 3, 41, 1), + FUNC("utif", 2, 41, 1), + FUNC("gpio", 1, 41, 1), + FUNC("p2led_an", 0, 41, 1), +}; + +static struct ralink_pmx_func p1led_an_grp[] =3D { + FUNC("jtag", 3, 42, 1), + FUNC("utif", 2, 42, 1), + FUNC("gpio", 1, 42, 1), + FUNC("p1led_an", 0, 42, 1), +}; + +static struct ralink_pmx_func p0led_an_grp[] =3D { + FUNC("jtag", 3, 43, 1), + FUNC("rsvd", 2, 43, 1), + FUNC("gpio", 1, 43, 1), + FUNC("p0led_an", 0, 43, 1), +}; + +static struct ralink_pmx_func wled_an_grp[] =3D { + FUNC("rsvd", 3, 44, 1), + FUNC("rsvd", 2, 44, 1), + FUNC("gpio", 1, 44, 1), + FUNC("wled_an", 0, 44, 1), +}; + +static struct ralink_pmx_group mt76x8_pinmux_data[] =3D { + GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM1), + GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM0), + GRP_G("uart2", uart2_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART2), + GRP_G("uart1", uart1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART1), + GRP_G("i2c", i2c_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2C), + GRP("refclk", refclk_grp, 1, MT76X8_GPIO_MODE_REFCLK), + GRP("perst", perst_grp, 1, MT76X8_GPIO_MODE_PERST), + GRP("wdt", wdt_grp, 1, MT76X8_GPIO_MODE_WDT), + GRP("spi", spi_grp, 1, MT76X8_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SDMODE), + GRP_G("uart0", uart0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART0), + GRP_G("i2s", i2s_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2S), + GRP_G("spi cs1", spi_cs1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_CS1), + GRP_G("spis", spis_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SPIS), + GRP_G("gpio", gpio_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_GPIO), + GRP_G("wled_an", wled_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_AN), + GRP_G("p0led_an", p0led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_AN), + GRP_G("p1led_an", p1led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_AN), + GRP_G("p2led_an", p2led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_AN), + GRP_G("p3led_an", p3led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_AN), + GRP_G("p4led_an", p4led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_AN), + GRP_G("wled_kn", wled_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_KN), + GRP_G("p0led_kn", p0led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_KN), + GRP_G("p1led_kn", p1led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_KN), + GRP_G("p2led_kn", p2led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_KN), + GRP_G("p3led_kn", p3led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_KN), + GRP_G("p4led_kn", p4led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_KN), + { 0 } +}; + +static int mt76x8_pinctrl_probe(struct platform_device *pdev) +{ + return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); +} + +static const struct of_device_id mt76x8_pinctrl_match[] =3D { + { .compatible =3D "ralink,mt76x8-pinctrl" }, + { .compatible =3D "ralink,mt7620-pinctrl" }, + { .compatible =3D "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, mt76x8_pinctrl_match); + +static struct platform_driver mt76x8_pinctrl_driver =3D { + .probe =3D mt76x8_pinctrl_probe, + .driver =3D { + .name =3D "mt76x8-pinctrl", + .of_match_table =3D mt76x8_pinctrl_match, + }, +}; + +static int __init mt76x8_pinctrl_init(void) +{ + return platform_driver_register(&mt76x8_pinctrl_driver); +} +core_initcall_sync(mt76x8_pinctrl_init); --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3263CC74A5B for ; Fri, 17 Mar 2023 21:30:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230371AbjCQVax (ORCPT ); Fri, 17 Mar 2023 17:30:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230370AbjCQVas (ORCPT ); Fri, 17 Mar 2023 17:30:48 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7822D2ED51; Fri, 17 Mar 2023 14:30:28 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id z21so25475095edb.4; Fri, 17 Mar 2023 14:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KtP3CYZqCoxnhcWZCbPGOqEwUbLALR7W0MvpQx3b5ww=; b=C7+82QpE3EIyw72HBU0r26J0ZPWwrsfFmXUMgQCXL8Y7UhtJenZookJDFk/DSmyyRa jSKIDic2PAjh9i9hj5n3F1TwhCUobBM2bGxJbXkzUeg4KCirPPUWpU2eXO6Qd0rr7FS6 EYeGR7VRMqfWTyYbn9+iV3BtSi9nEmRjup206dF75wT3QQT5udF62D6YVu/PmND35gkE LIcIUI3Pf7VaRnUJ4+cb/Y+AeLLAiM9ip4pqY2jyIqHR4fMlExL368V+lrxGdOsacRJw T1R2fIwnGrWSOZiLe4fkVFe82/aljTtQH/kdjv9AUtKYkckfwpMXtk7ddjxBTzM5g6Vk 6Cyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KtP3CYZqCoxnhcWZCbPGOqEwUbLALR7W0MvpQx3b5ww=; b=PGrHE0CIhq3F8FNVZyj9+W86MtsLZOeepM01ZIP5ZbK64t8v3AGASZVKPUvLnX1vpr 6SctmFwa/ErlaEt6gpcJfPPgtLDz1U6N1gJawRAtU502mvEjBC2E86R1UO0XRKJYKtRO S+JY/71+itnCMZU7VXtiUce/tuUMBIywApTl0X9Wdc/0cvD3T4P6o/xcwCB2a6zEYYAm AyIb6jTcg3a0bj/5klRWD2hSTzUMrLnsEOpvKid6aUh42hti3CD4o0GKV9A9uBaiiXtG A9oAOx45zqgu+M5Gp3UDnfBBKTkogmXrUulAPkwy+tYSpgs+tPdBrbBwSD+THoWS+Op4 fK7Q== X-Gm-Message-State: AO0yUKVV+chfPMvW0t++aHYizufBn2GVxcbYMDFeKI/9L+PWCVzznyVT aVWv0J6ucRKtMewR1wnK3A0= X-Google-Smtp-Source: AK7set9VuJqUkU6CtewQ/bAW5DA6G7CZsZbBXkRupJFSutlGGgNMvqQAxAQdk6+LSftNudkb59MFoQ== X-Received: by 2002:aa7:c0ca:0:b0:4fb:54b7:50ea with SMTP id j10-20020aa7c0ca000000b004fb54b750eamr4951350edp.21.1679088626648; Fri, 17 Mar 2023 14:30:26 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:26 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 04/21] pinctrl: ralink: move to mediatek as mtmips Date: Sat, 18 Mar 2023 00:29:54 +0300 Message-Id: <20230317213011.13656-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek introduced new SoCs which utilise this platform. Move the driver to mediatek pinctrl directory. Rename the ralink core driver to mtmips. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/pinctrl/Kconfig | 1 - drivers/pinctrl/Makefile | 1 - drivers/pinctrl/mediatek/Kconfig | 51 ++++++++++- drivers/pinctrl/mediatek/Makefile | 63 +++++++------ .../{ralink =3D> mediatek}/pinctrl-mt7620.c | 34 +++---- .../{ralink =3D> mediatek}/pinctrl-mt7621.c | 30 +++---- .../{ralink =3D> mediatek}/pinctrl-mt76x8.c | 60 ++++++------- .../pinctrl-mtmips.c} | 90 +++++++++---------- .../pinctrl-mtmips.h} | 16 ++-- .../{ralink =3D> mediatek}/pinctrl-rt2880.c | 20 ++--- .../{ralink =3D> mediatek}/pinctrl-rt305x.c | 44 ++++----- .../{ralink =3D> mediatek}/pinctrl-rt3883.c | 28 +++--- drivers/pinctrl/ralink/Kconfig | 40 --------- drivers/pinctrl/ralink/Makefile | 9 -- 14 files changed, 246 insertions(+), 241 deletions(-) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-mt7620.c (81%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-mt7621.c (80%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-mt76x8.c (81%) rename drivers/pinctrl/{ralink/pinctrl-ralink.c =3D> mediatek/pinctrl-mtmi= ps.c} (74%) rename drivers/pinctrl/{ralink/pinctrl-ralink.h =3D> mediatek/pinctrl-mtmi= ps.h} (75%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-rt2880.c (71%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-rt305x.c (75%) rename drivers/pinctrl/{ralink =3D> mediatek}/pinctrl-rt3883.c (80%) delete mode 100644 drivers/pinctrl/ralink/Kconfig delete mode 100644 drivers/pinctrl/ralink/Makefile diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 694f47fe6d11..e2a24d668e41 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -538,7 +538,6 @@ source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" -source "drivers/pinctrl/ralink/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c40397af024b..413b1e6b6933 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -67,7 +67,6 @@ obj-y +=3D nuvoton/ obj-y +=3D nxp/ obj-$(CONFIG_PINCTRL_PXA) +=3D pxa/ obj-$(CONFIG_ARCH_QCOM) +=3D qcom/ -obj-$(CONFIG_PINCTRL_RALINK) +=3D ralink/ obj-$(CONFIG_PINCTRL_RENESAS) +=3D renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) +=3D samsung/ obj-$(CONFIG_PINCTRL_SPEAR) +=3D spear/ diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kc= onfig index f20c28334bcb..ba21a599953c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "MediaTek pinctrl drivers" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST =20 config EINT_MTK tristate "MediaTek External Interrupt Support" @@ -22,6 +22,12 @@ config PINCTRL_MTK config PINCTRL_MTK_V2 tristate =20 +config PINCTRL_MTK_MTMIPS + bool + depends on RALINK + select PINMUX + select GENERIC_PINCONF + config PINCTRL_MTK_MOORE bool depends on OF @@ -43,6 +49,49 @@ config PINCTRL_MTK_PARIS select OF_GPIO select PINCTRL_MTK_V2 =20 +# For MIPS SoCs +config PINCTRL_MT7620 + bool "MediaTek MT7620 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT7621 + bool "MediaTek MT7621 pin control" + depends on SOC_MT7621 || COMPILE_TEST + depends on RALINK + default SOC_MT7621 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT76X8 + bool "MediaTek MT76X8 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT2880 + bool "Ralink RT2880 pin control" + depends on SOC_RT288X || COMPILE_TEST + depends on RALINK + default SOC_RT288X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT305X + bool "Ralink RT305X pin control" + depends on SOC_RT305X || COMPILE_TEST + depends on RALINK + default SOC_RT305X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT3883 + bool "Ralink RT3883 pin control" + depends on SOC_RT3883 || COMPILE_TEST + depends on RALINK + default SOC_RT3883 + select PINCTRL_MTK_MTMIPS + # For ARMv7 SoCs config PINCTRL_MT2701 bool "Mediatek MT2701 pin control" diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/M= akefile index 44d197af516a..680f7e8526e0 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -1,32 +1,39 @@ # SPDX-License-Identifier: GPL-2.0 # Core -obj-$(CONFIG_EINT_MTK) +=3D mtk-eint.o -obj-$(CONFIG_PINCTRL_MTK) +=3D pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_V2) +=3D pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) +=3D pinctrl-moore.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) +=3D pinctrl-paris.o +obj-$(CONFIG_EINT_MTK) +=3D mtk-eint.o +obj-$(CONFIG_PINCTRL_MTK) +=3D pinctrl-mtk-common.o +obj-$(CONFIG_PINCTRL_MTK_V2) +=3D pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MTMIPS) +=3D pinctrl-mtmips.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) +=3D pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) +=3D pinctrl-paris.o =20 # SoC Drivers -obj-$(CONFIG_PINCTRL_MT2701) +=3D pinctrl-mt2701.o -obj-$(CONFIG_PINCTRL_MT2712) +=3D pinctrl-mt2712.o -obj-$(CONFIG_PINCTRL_MT8135) +=3D pinctrl-mt8135.o -obj-$(CONFIG_PINCTRL_MT8127) +=3D pinctrl-mt8127.o -obj-$(CONFIG_PINCTRL_MT6765) +=3D pinctrl-mt6765.o -obj-$(CONFIG_PINCTRL_MT6779) +=3D pinctrl-mt6779.o -obj-$(CONFIG_PINCTRL_MT6795) +=3D pinctrl-mt6795.o -obj-$(CONFIG_PINCTRL_MT6797) +=3D pinctrl-mt6797.o -obj-$(CONFIG_PINCTRL_MT7622) +=3D pinctrl-mt7622.o -obj-$(CONFIG_PINCTRL_MT7623) +=3D pinctrl-mt7623.o -obj-$(CONFIG_PINCTRL_MT7629) +=3D pinctrl-mt7629.o -obj-$(CONFIG_PINCTRL_MT7981) +=3D pinctrl-mt7981.o -obj-$(CONFIG_PINCTRL_MT7986) +=3D pinctrl-mt7986.o -obj-$(CONFIG_PINCTRL_MT8167) +=3D pinctrl-mt8167.o -obj-$(CONFIG_PINCTRL_MT8173) +=3D pinctrl-mt8173.o -obj-$(CONFIG_PINCTRL_MT8183) +=3D pinctrl-mt8183.o -obj-$(CONFIG_PINCTRL_MT8186) +=3D pinctrl-mt8186.o -obj-$(CONFIG_PINCTRL_MT8188) +=3D pinctrl-mt8188.o -obj-$(CONFIG_PINCTRL_MT8192) +=3D pinctrl-mt8192.o -obj-$(CONFIG_PINCTRL_MT8195) +=3D pinctrl-mt8195.o -obj-$(CONFIG_PINCTRL_MT8365) +=3D pinctrl-mt8365.o -obj-$(CONFIG_PINCTRL_MT8516) +=3D pinctrl-mt8516.o -obj-$(CONFIG_PINCTRL_MT6397) +=3D pinctrl-mt6397.o +obj-$(CONFIG_PINCTRL_MT7620) +=3D pinctrl-mt7620.o +obj-$(CONFIG_PINCTRL_MT7621) +=3D pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) +=3D pinctrl-mt76x8.o +obj-$(CONFIG_PINCTRL_RT2880) +=3D pinctrl-rt2880.o +obj-$(CONFIG_PINCTRL_RT305X) +=3D pinctrl-rt305x.o +obj-$(CONFIG_PINCTRL_RT3883) +=3D pinctrl-rt3883.o +obj-$(CONFIG_PINCTRL_MT2701) +=3D pinctrl-mt2701.o +obj-$(CONFIG_PINCTRL_MT2712) +=3D pinctrl-mt2712.o +obj-$(CONFIG_PINCTRL_MT8135) +=3D pinctrl-mt8135.o +obj-$(CONFIG_PINCTRL_MT8127) +=3D pinctrl-mt8127.o +obj-$(CONFIG_PINCTRL_MT6765) +=3D pinctrl-mt6765.o +obj-$(CONFIG_PINCTRL_MT6779) +=3D pinctrl-mt6779.o +obj-$(CONFIG_PINCTRL_MT6795) +=3D pinctrl-mt6795.o +obj-$(CONFIG_PINCTRL_MT6797) +=3D pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT7622) +=3D pinctrl-mt7622.o +obj-$(CONFIG_PINCTRL_MT7623) +=3D pinctrl-mt7623.o +obj-$(CONFIG_PINCTRL_MT7629) +=3D pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT7981) +=3D pinctrl-mt7981.o +obj-$(CONFIG_PINCTRL_MT7986) +=3D pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT8167) +=3D pinctrl-mt8167.o +obj-$(CONFIG_PINCTRL_MT8173) +=3D pinctrl-mt8173.o +obj-$(CONFIG_PINCTRL_MT8183) +=3D pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8186) +=3D pinctrl-mt8186.o +obj-$(CONFIG_PINCTRL_MT8188) +=3D pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8192) +=3D pinctrl-mt8192.o +obj-$(CONFIG_PINCTRL_MT8195) +=3D pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8365) +=3D pinctrl-mt8365.o +obj-$(CONFIG_PINCTRL_MT8516) +=3D pinctrl-mt8516.o +obj-$(CONFIG_PINCTRL_MT6397) +=3D pinctrl-mt6397.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/medi= atek/pinctrl-mt7620.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt7620.c rename to drivers/pinctrl/mediatek/pinctrl-mt7620.c index 3f6ffccc6882..d2624b9b5bc4 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define MT7620_GPIO_MODE_UART0_SHIFT 2 #define MT7620_GPIO_MODE_UART0_MASK 0x7 @@ -52,20 +52,20 @@ #define MT7620_GPIO_MODE_EPHY 15 #define MT7620_GPIO_MODE_PA 20 =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; -static struct ralink_pmx_func mdio_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), }; -static struct ralink_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 24, 12)= }; -static struct ralink_pmx_func refclk_grp[] =3D { FUNC("spi refclk", 0, 37,= 3) }; -static struct ralink_pmx_func ephy_grp[] =3D { FUNC("ephy", 0, 40, 5) }; -static struct ralink_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 60, 12)= }; -static struct ralink_pmx_func wled_grp[] =3D { FUNC("wled", 0, 72, 1) }; -static struct ralink_pmx_func pa_grp[] =3D { FUNC("pa", 0, 18, 4) }; -static struct ralink_pmx_func uartf_grp[] =3D { +static struct mtmips_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 24, 12)= }; +static struct mtmips_pmx_func refclk_grp[] =3D { FUNC("spi refclk", 0, 37,= 3) }; +static struct mtmips_pmx_func ephy_grp[] =3D { FUNC("ephy", 0, 40, 5) }; +static struct mtmips_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 60, 12)= }; +static struct mtmips_pmx_func wled_grp[] =3D { FUNC("wled", 0, 72, 1) }; +static struct mtmips_pmx_func pa_grp[] =3D { FUNC("pa", 0, 18, 4) }; +static struct mtmips_pmx_func uartf_grp[] =3D { FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), @@ -74,20 +74,20 @@ static struct ralink_pmx_func uartf_grp[] =3D { FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func wdt_grp[] =3D { +static struct mtmips_pmx_func wdt_grp[] =3D { FUNC("wdt rst", 0, 17, 1), FUNC("wdt refclk", 0, 17, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] =3D { +static struct mtmips_pmx_func pcie_rst_grp[] =3D { FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) }; -static struct ralink_pmx_func nd_sd_grp[] =3D { +static struct mtmips_pmx_func nd_sd_grp[] =3D { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; =20 -static struct ralink_pmx_group mt7620a_pinmux_data[] =3D { +static struct mtmips_pmx_group mt7620a_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, MT7620_GPIO_MODE_UART0_SHIFT), @@ -112,7 +112,7 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = =3D { =20 static int mt7620_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7620a_pinmux_data); } =20 static const struct of_device_id mt7620_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/medi= atek/pinctrl-mt7621.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-mt7621.c rename to drivers/pinctrl/mediatek/pinctrl-mt7621.c index fb5824922e78..b18c1a47bbeb 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define MT7621_GPIO_MODE_UART1 1 #define MT7621_GPIO_MODE_I2C 2 @@ -34,40 +34,40 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 =20 -static struct ralink_pmx_func uart1_grp[] =3D { FUNC("uart1", 0, 1, 2) }; -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 3, 2) }; -static struct ralink_pmx_func uart3_grp[] =3D { +static struct mtmips_pmx_func uart1_grp[] =3D { FUNC("uart1", 0, 1, 2) }; +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 3, 2) }; +static struct mtmips_pmx_func uart3_grp[] =3D { FUNC("uart3", 0, 5, 4), FUNC("i2s", 2, 5, 4), FUNC("spdif3", 3, 5, 4), }; -static struct ralink_pmx_func uart2_grp[] =3D { +static struct mtmips_pmx_func uart2_grp[] =3D { FUNC("uart2", 0, 9, 4), FUNC("pcm", 2, 9, 4), FUNC("spdif2", 3, 9, 4), }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 13, 5) }; -static struct ralink_pmx_func wdt_grp[] =3D { +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 13, 5) }; +static struct mtmips_pmx_func wdt_grp[] =3D { FUNC("wdt rst", 0, 18, 1), FUNC("wdt refclk", 2, 18, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] =3D { +static struct mtmips_pmx_func pcie_rst_grp[] =3D { FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 20, 2) }; -static struct ralink_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 22, 12)= }; -static struct ralink_pmx_func spi_grp[] =3D { +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 20, 2) }; +static struct mtmips_pmx_func rgmii2_grp[] =3D { FUNC("rgmii2", 0, 22, 12)= }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 34, 7), FUNC("nand1", 2, 34, 7), }; -static struct ralink_pmx_func sdhci_grp[] =3D { +static struct mtmips_pmx_func sdhci_grp[] =3D { FUNC("sdhci", 0, 41, 8), FUNC("nand2", 2, 41, 8), }; -static struct ralink_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 49, 12)= }; +static struct mtmips_pmx_func rgmii1_grp[] =3D { FUNC("rgmii1", 0, 49, 12)= }; =20 -static struct ralink_pmx_group mt7621_pinmux_data[] =3D { +static struct mtmips_pmx_group mt7621_pinmux_data[] =3D { GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group mt7621_pinmux_data[] =3D { =20 static int mt7621_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7621_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7621_pinmux_data); } =20 static const struct of_device_id mt7621_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/medi= atek/pinctrl-mt76x8.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt76x8.c rename to drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 4283a54d2db0..e7d6ad2f62e4 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define MT76X8_GPIO_MODE_MASK 0x3 =20 @@ -35,173 +35,173 @@ #define MT76X8_GPIO_MODE_SPIS 2 #define MT76X8_GPIO_MODE_GPIO 0 =20 -static struct ralink_pmx_func pwm1_grp[] =3D { +static struct mtmips_pmx_func pwm1_grp[] =3D { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; =20 -static struct ralink_pmx_func pwm0_grp[] =3D { +static struct mtmips_pmx_func pwm0_grp[] =3D { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; =20 -static struct ralink_pmx_func uart2_grp[] =3D { +static struct mtmips_pmx_func uart2_grp[] =3D { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; =20 -static struct ralink_pmx_func uart1_grp[] =3D { +static struct mtmips_pmx_func uart1_grp[] =3D { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; =20 -static struct ralink_pmx_func i2c_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; =20 -static struct ralink_pmx_func refclk_grp[] =3D { FUNC("refclk", 0, 37, 1) = }; -static struct ralink_pmx_func perst_grp[] =3D { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_grp[] =3D { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 7, 4) }; +static struct mtmips_pmx_func refclk_grp[] =3D { FUNC("refclk", 0, 37, 1) = }; +static struct mtmips_pmx_func perst_grp[] =3D { FUNC("perst", 0, 36, 1) }; +static struct mtmips_pmx_func wdt_grp[] =3D { FUNC("wdt", 0, 38, 1) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 7, 4) }; =20 -static struct ralink_pmx_func sd_mode_grp[] =3D { +static struct mtmips_pmx_func sd_mode_grp[] =3D { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; =20 -static struct ralink_pmx_func uart0_grp[] =3D { +static struct mtmips_pmx_func uart0_grp[] =3D { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; =20 -static struct ralink_pmx_func i2s_grp[] =3D { +static struct mtmips_pmx_func i2s_grp[] =3D { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; =20 -static struct ralink_pmx_func spi_cs1_grp[] =3D { +static struct mtmips_pmx_func spi_cs1_grp[] =3D { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; =20 -static struct ralink_pmx_func spis_grp[] =3D { +static struct mtmips_pmx_func spis_grp[] =3D { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; =20 -static struct ralink_pmx_func gpio_grp[] =3D { +static struct mtmips_pmx_func gpio_grp[] =3D { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; =20 -static struct ralink_pmx_func p4led_kn_grp[] =3D { +static struct mtmips_pmx_func p4led_kn_grp[] =3D { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; =20 -static struct ralink_pmx_func p3led_kn_grp[] =3D { +static struct mtmips_pmx_func p3led_kn_grp[] =3D { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; =20 -static struct ralink_pmx_func p2led_kn_grp[] =3D { +static struct mtmips_pmx_func p2led_kn_grp[] =3D { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; =20 -static struct ralink_pmx_func p1led_kn_grp[] =3D { +static struct mtmips_pmx_func p1led_kn_grp[] =3D { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; =20 -static struct ralink_pmx_func p0led_kn_grp[] =3D { +static struct mtmips_pmx_func p0led_kn_grp[] =3D { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; =20 -static struct ralink_pmx_func wled_kn_grp[] =3D { +static struct mtmips_pmx_func wled_kn_grp[] =3D { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; =20 -static struct ralink_pmx_func p4led_an_grp[] =3D { +static struct mtmips_pmx_func p4led_an_grp[] =3D { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; =20 -static struct ralink_pmx_func p3led_an_grp[] =3D { +static struct mtmips_pmx_func p3led_an_grp[] =3D { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; =20 -static struct ralink_pmx_func p2led_an_grp[] =3D { +static struct mtmips_pmx_func p2led_an_grp[] =3D { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; =20 -static struct ralink_pmx_func p1led_an_grp[] =3D { +static struct mtmips_pmx_func p1led_an_grp[] =3D { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; =20 -static struct ralink_pmx_func p0led_an_grp[] =3D { +static struct mtmips_pmx_func p0led_an_grp[] =3D { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; =20 -static struct ralink_pmx_func wled_an_grp[] =3D { +static struct mtmips_pmx_func wled_an_grp[] =3D { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), FUNC("wled_an", 0, 44, 1), }; =20 -static struct ralink_pmx_group mt76x8_pinmux_data[] =3D { +static struct mtmips_pmx_group mt76x8_pinmux_data[] =3D { GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM1), GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, @@ -257,7 +257,7 @@ static struct ralink_pmx_group mt76x8_pinmux_data[] =3D= { =20 static int mt76x8_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); + return mtmips_pinctrl_init(pdev, mt76x8_pinmux_data); } =20 static const struct of_device_id mt76x8_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.c b/drivers/pinctrl/medi= atek/pinctrl-mtmips.c similarity index 74% rename from drivers/pinctrl/ralink/pinctrl-ralink.c rename to drivers/pinctrl/mediatek/pinctrl-mtmips.c index 770862f45b3f..efd77b6c56a1 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c @@ -19,23 +19,23 @@ #include #include =20 -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #include "../core.h" #include "../pinctrl-utils.h" =20 #define SYSC_REG_GPIO_MODE 0x60 #define SYSC_REG_GPIO_MODE2 0x64 =20 -struct ralink_priv { +struct mtmips_priv { struct device *dev; =20 struct pinctrl_pin_desc *pads; struct pinctrl_desc *desc; =20 - struct ralink_pmx_func **func; + struct mtmips_pmx_func **func; int func_count; =20 - struct ralink_pmx_group *groups; + struct mtmips_pmx_group *groups; const char **group_names; int group_count; =20 @@ -43,27 +43,27 @@ struct ralink_priv { int max_pins; }; =20 -static int ralink_get_group_count(struct pinctrl_dev *pctrldev) +static int mtmips_get_group_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return p->group_count; } =20 -static const char *ralink_get_group_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_get_group_name(struct pinctrl_dev *pctrldev, unsigned int group) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return (group >=3D p->group_count) ? NULL : p->group_names[group]; } =20 -static int ralink_get_group_pins(struct pinctrl_dev *pctrldev, +static int mtmips_get_group_pins(struct pinctrl_dev *pctrldev, unsigned int group, const unsigned int **pins, unsigned int *num_pins) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 if (group >=3D p->group_count) return -EINVAL; @@ -74,35 +74,35 @@ static int ralink_get_group_pins(struct pinctrl_dev *pc= trldev, return 0; } =20 -static const struct pinctrl_ops ralink_pctrl_ops =3D { - .get_groups_count =3D ralink_get_group_count, - .get_group_name =3D ralink_get_group_name, - .get_group_pins =3D ralink_get_group_pins, +static const struct pinctrl_ops mtmips_pctrl_ops =3D { + .get_groups_count =3D mtmips_get_group_count, + .get_group_name =3D mtmips_get_group_name, + .get_group_pins =3D mtmips_get_group_pins, .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, .dt_free_map =3D pinconf_generic_dt_free_map, }; =20 -static int ralink_pmx_func_count(struct pinctrl_dev *pctrldev) +static int mtmips_pmx_func_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return p->func_count; } =20 -static const char *ralink_pmx_func_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_pmx_func_name(struct pinctrl_dev *pctrldev, unsigned int func) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 return p->func[func]->name; } =20 -static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_get_groups(struct pinctrl_dev *pctrldev, unsigned int func, const char * const **groups, unsigned int * const num_groups) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 if (p->func[func]->group_count =3D=3D 1) *groups =3D &p->group_names[p->func[func]->groups[0]]; @@ -114,10 +114,10 @@ static int ralink_pmx_group_get_groups(struct pinctrl= _dev *pctrldev, return 0; } =20 -static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_enable(struct pinctrl_dev *pctrldev, unsigned int func, unsigned int group) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); u32 mode =3D 0; u32 reg =3D SYSC_REG_GPIO_MODE; int i; @@ -158,11 +158,11 @@ static int ralink_pmx_group_enable(struct pinctrl_dev= *pctrldev, return 0; } =20 -static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrld= ev, +static int mtmips_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrld= ev, struct pinctrl_gpio_range *range, unsigned int pin) { - struct ralink_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p =3D pinctrl_dev_get_drvdata(pctrldev); =20 if (!p->gpio[pin]) { dev_err(p->dev, "pin %d is not set to gpio mux\n", pin); @@ -172,28 +172,28 @@ static int ralink_pmx_group_gpio_request_enable(struc= t pinctrl_dev *pctrldev, return 0; } =20 -static const struct pinmux_ops ralink_pmx_group_ops =3D { - .get_functions_count =3D ralink_pmx_func_count, - .get_function_name =3D ralink_pmx_func_name, - .get_function_groups =3D ralink_pmx_group_get_groups, - .set_mux =3D ralink_pmx_group_enable, - .gpio_request_enable =3D ralink_pmx_group_gpio_request_enable, +static const struct pinmux_ops mtmips_pmx_group_ops =3D { + .get_functions_count =3D mtmips_pmx_func_count, + .get_function_name =3D mtmips_pmx_func_name, + .get_function_groups =3D mtmips_pmx_group_get_groups, + .set_mux =3D mtmips_pmx_group_enable, + .gpio_request_enable =3D mtmips_pmx_group_gpio_request_enable, }; =20 -static struct pinctrl_desc ralink_pctrl_desc =3D { +static struct pinctrl_desc mtmips_pctrl_desc =3D { .owner =3D THIS_MODULE, - .name =3D "ralink-pinctrl", - .pctlops =3D &ralink_pctrl_ops, - .pmxops =3D &ralink_pmx_group_ops, + .name =3D "mtmips-pinctrl", + .pctlops =3D &mtmips_pctrl_ops, + .pmxops =3D &mtmips_pmx_group_ops, }; =20 -static struct ralink_pmx_func gpio_func =3D { +static struct mtmips_pmx_func gpio_func =3D { .name =3D "gpio", }; =20 -static int ralink_pinctrl_index(struct ralink_priv *p) +static int mtmips_pinctrl_index(struct mtmips_priv *p) { - struct ralink_pmx_group *mux =3D p->groups; + struct mtmips_pmx_group *mux =3D p->groups; int i, j, c =3D 0; =20 /* count the mux functions */ @@ -248,7 +248,7 @@ static int ralink_pinctrl_index(struct ralink_priv *p) return 0; } =20 -static int ralink_pinctrl_pins(struct ralink_priv *p) +static int mtmips_pinctrl_pins(struct mtmips_priv *p) { int i, j; =20 @@ -313,10 +313,10 @@ static int ralink_pinctrl_pins(struct ralink_priv *p) return 0; } =20 -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data) +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data) { - struct ralink_priv *p; + struct mtmips_priv *p; struct pinctrl_dev *dev; int err; =20 @@ -324,23 +324,23 @@ int ralink_pinctrl_init(struct platform_device *pdev, return -ENOTSUPP; =20 /* setup the private data */ - p =3D devm_kzalloc(&pdev->dev, sizeof(struct ralink_priv), GFP_KERNEL); + p =3D devm_kzalloc(&pdev->dev, sizeof(struct mtmips_priv), GFP_KERNEL); if (!p) return -ENOMEM; =20 p->dev =3D &pdev->dev; - p->desc =3D &ralink_pctrl_desc; + p->desc =3D &mtmips_pctrl_desc; p->groups =3D data; platform_set_drvdata(pdev, p); =20 /* init the device */ - err =3D ralink_pinctrl_index(p); + err =3D mtmips_pinctrl_index(p); if (err) { dev_err(&pdev->dev, "failed to load index\n"); return err; } =20 - err =3D ralink_pinctrl_pins(p); + err =3D mtmips_pinctrl_pins(p); if (err) { dev_err(&pdev->dev, "failed to load pins\n"); return err; diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.h b/drivers/pinctrl/medi= atek/pinctrl-mtmips.h similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-ralink.h rename to drivers/pinctrl/mediatek/pinctrl-mtmips.h index e6037be1e153..a7c3dd724431 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.h @@ -3,8 +3,8 @@ * Copyright (C) 2012 John Crispin */ =20 -#ifndef _PINCTRL_RALINK_H__ -#define _PINCTRL_RALINK_H__ +#ifndef _PINCTRL_MTMIPS_H__ +#define _PINCTRL_MTMIPS_H__ =20 #define FUNC(name, value, pin_first, pin_count) \ { name, value, pin_first, pin_count } @@ -19,9 +19,9 @@ .func =3D _func, .gpio =3D _gpio, \ .func_count =3D ARRAY_SIZE(_func) } =20 -struct ralink_pmx_group; +struct mtmips_pmx_group; =20 -struct ralink_pmx_func { +struct mtmips_pmx_func { const char *name; const char value; =20 @@ -35,7 +35,7 @@ struct ralink_pmx_func { int enabled; }; =20 -struct ralink_pmx_group { +struct mtmips_pmx_group { const char *name; int enabled; =20 @@ -43,11 +43,11 @@ struct ralink_pmx_group { const char mask; const char gpio; =20 - struct ralink_pmx_func *func; + struct mtmips_pmx_func *func; int func_count; }; =20 -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data); +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data); =20 #endif diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/medi= atek/pinctrl-rt2880.c similarity index 71% rename from drivers/pinctrl/ralink/pinctrl-rt2880.c rename to drivers/pinctrl/mediatek/pinctrl-rt2880.c index d7a65fcc7755..e0366721a515 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -4,7 +4,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define RT2880_GPIO_MODE_I2C BIT(0) #define RT2880_GPIO_MODE_UART0 BIT(1) @@ -15,15 +15,15 @@ #define RT2880_GPIO_MODE_SDRAM BIT(6) #define RT2880_GPIO_MODE_PCI BIT(7) =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 7, = 8) }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func pci_grp[] =3D { FUNC("pci", 0, 40, 32) }; +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 7, = 8) }; +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func pci_grp[] =3D { FUNC("pci", 0, 40, 32) }; =20 -static struct ralink_pmx_group rt2880_pinmux_data_act[] =3D { +static struct mtmips_pmx_group rt2880_pinmux_data_act[] =3D { GRP("i2c", i2c_grp, 1, RT2880_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT2880_GPIO_MODE_SPI), GRP("uartlite", uartlite_grp, 1, RT2880_GPIO_MODE_UART0), @@ -36,7 +36,7 @@ static struct ralink_pmx_group rt2880_pinmux_data_act[] = =3D { =20 static int rt2880_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt2880_pinmux_data_act); + return mtmips_pinctrl_init(pdev, rt2880_pinmux_data_act); } =20 static const struct of_device_id rt2880_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/medi= atek/pinctrl-rt305x.c similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-rt305x.c rename to drivers/pinctrl/mediatek/pinctrl-rt305x.c index fa3743c7680f..77bd4d1f6122 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -5,7 +5,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define RT305X_GPIO_MODE_UART0_SHIFT 2 #define RT305X_GPIO_MODE_UART0_MASK 0x7 @@ -31,9 +31,9 @@ #define RT3352_GPIO_MODE_LNA 18 #define RT3352_GPIO_MODE_PA 20 =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] =3D { FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), @@ -42,28 +42,28 @@ static struct ralink_pmx_func uartf_grp[] =3D { FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func rt5350_led_grp[] =3D { FUNC("led", 0, 22, 5)= }; -static struct ralink_pmx_func rt5350_cs1_grp[] =3D { +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func rt5350_led_grp[] =3D { FUNC("led", 0, 22, 5)= }; +static struct mtmips_pmx_func rt5350_cs1_grp[] =3D { FUNC("spi_cs1", 0, 27, 1), FUNC("wdg_cs1", 1, 27, 1), }; -static struct ralink_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func rt3352_rgmii_grp[] =3D { +static struct mtmips_pmx_func sdram_grp[] =3D { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func rt3352_rgmii_grp[] =3D { FUNC("rgmii", 0, 24, 12) }; -static struct ralink_pmx_func rgmii_grp[] =3D { FUNC("rgmii", 0, 40, 12) }; -static struct ralink_pmx_func rt3352_lna_grp[] =3D { FUNC("lna", 0, 36, 2)= }; -static struct ralink_pmx_func rt3352_pa_grp[] =3D { FUNC("pa", 0, 38, 2) }; -static struct ralink_pmx_func rt3352_led_grp[] =3D { FUNC("led", 0, 40, 5)= }; -static struct ralink_pmx_func rt3352_cs1_grp[] =3D { +static struct mtmips_pmx_func rgmii_grp[] =3D { FUNC("rgmii", 0, 40, 12) }; +static struct mtmips_pmx_func rt3352_lna_grp[] =3D { FUNC("lna", 0, 36, 2)= }; +static struct mtmips_pmx_func rt3352_pa_grp[] =3D { FUNC("pa", 0, 38, 2) }; +static struct mtmips_pmx_func rt3352_led_grp[] =3D { FUNC("led", 0, 40, 5)= }; +static struct mtmips_pmx_func rt3352_cs1_grp[] =3D { FUNC("spi_cs1", 0, 45, 1), FUNC("wdg_cs1", 1, 45, 1), }; =20 -static struct ralink_pmx_group rt3050_pinmux_data[] =3D { +static struct mtmips_pmx_group rt3050_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -76,7 +76,7 @@ static struct ralink_pmx_group rt3050_pinmux_data[] =3D { { 0 } }; =20 -static struct ralink_pmx_group rt3352_pinmux_data[] =3D { +static struct mtmips_pmx_group rt3352_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group rt3352_pinmux_data[] =3D { { 0 } }; =20 -static struct ralink_pmx_group rt5350_pinmux_data[] =3D { +static struct mtmips_pmx_group rt5350_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -107,11 +107,11 @@ static struct ralink_pmx_group rt5350_pinmux_data[] = =3D { static int rt305x_pinctrl_probe(struct platform_device *pdev) { if (soc_is_rt5350()) - return ralink_pinctrl_init(pdev, rt5350_pinmux_data); + return mtmips_pinctrl_init(pdev, rt5350_pinmux_data); else if (soc_is_rt305x() || soc_is_rt3350()) - return ralink_pinctrl_init(pdev, rt3050_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3050_pinmux_data); else if (soc_is_rt3352()) - return ralink_pinctrl_init(pdev, rt3352_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3352_pinmux_data); else return -EINVAL; } diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/medi= atek/pinctrl-rt3883.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-rt3883.c rename to drivers/pinctrl/mediatek/pinctrl-rt3883.c index 5f766d76bafa..eeaf344c3647 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" =20 #define RT3883_GPIO_MODE_UART0_SHIFT 2 #define RT3883_GPIO_MODE_UART0_MASK 0x7 @@ -39,9 +39,9 @@ #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 #define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_L= NA_G_MASK) =20 -static struct ralink_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] =3D { +static struct mtmips_pmx_func i2c_grp[] =3D { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] =3D { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] =3D { FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), @@ -50,21 +50,21 @@ static struct ralink_pmx_func uartf_grp[] =3D { FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; -static struct ralink_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func lna_a_grp[] =3D { FUNC("lna a", 0, 32, 3) }; -static struct ralink_pmx_func lna_g_grp[] =3D { FUNC("lna g", 0, 35, 3) }; -static struct ralink_pmx_func pci_grp[] =3D { +static struct mtmips_pmx_func uartlite_grp[] =3D { FUNC("uartlite", 0, 15,= 2) }; +static struct mtmips_pmx_func jtag_grp[] =3D { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] =3D { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func lna_a_grp[] =3D { FUNC("lna a", 0, 32, 3) }; +static struct mtmips_pmx_func lna_g_grp[] =3D { FUNC("lna g", 0, 35, 3) }; +static struct mtmips_pmx_func pci_grp[] =3D { FUNC("pci-dev", 0, 40, 32), FUNC("pci-host2", 1, 40, 32), FUNC("pci-host1", 2, 40, 32), FUNC("pci-fnc", 3, 40, 32) }; -static struct ralink_pmx_func ge1_grp[] =3D { FUNC("ge1", 0, 72, 12) }; -static struct ralink_pmx_func ge2_grp[] =3D { FUNC("ge2", 0, 84, 12) }; +static struct mtmips_pmx_func ge1_grp[] =3D { FUNC("ge1", 0, 72, 12) }; +static struct mtmips_pmx_func ge2_grp[] =3D { FUNC("ge2", 0, 84, 12) }; =20 -static struct ralink_pmx_group rt3883_pinmux_data[] =3D { +static struct mtmips_pmx_group rt3883_pinmux_data[] =3D { GRP("i2c", i2c_grp, 1, RT3883_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT3883_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT3883_GPIO_MODE_UART0_MASK, @@ -83,7 +83,7 @@ static struct ralink_pmx_group rt3883_pinmux_data[] =3D { =20 static int rt3883_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt3883_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3883_pinmux_data); } =20 static const struct of_device_id rt3883_pinctrl_match[] =3D { diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig deleted file mode 100644 index c5fe4c31aaea..000000000000 --- a/drivers/pinctrl/ralink/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menu "Ralink pinctrl drivers" - depends on RALINK - -config PINCTRL_RALINK - bool "Ralink pinctrl driver" - select PINMUX - select GENERIC_PINCONF - -config PINCTRL_MT7620 - bool "MT7620 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_MT7621 - bool "MT7621 pinctrl subdriver" - depends on RALINK && SOC_MT7621 - select PINCTRL_RALINK - -config PINCTRL_MT76X8 - bool "MT76X8 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_RT2880 - bool "RT2880 pinctrl subdriver" - depends on RALINK && SOC_RT288X - select PINCTRL_RALINK - -config PINCTRL_RT305X - bool "RT305X pinctrl subdriver" - depends on RALINK && SOC_RT305X - select PINCTRL_RALINK - -config PINCTRL_RT3883 - bool "RT3883 pinctrl subdriver" - depends on RALINK && SOC_RT3883 - select PINCTRL_RALINK - -endmenu diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makef= ile deleted file mode 100644 index be9acf2e27fd..000000000000 --- a/drivers/pinctrl/ralink/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_RALINK) +=3D pinctrl-ralink.o - -obj-$(CONFIG_PINCTRL_MT7620) +=3D pinctrl-mt7620.o -obj-$(CONFIG_PINCTRL_MT7621) +=3D pinctrl-mt7621.o -obj-$(CONFIG_PINCTRL_MT76X8) +=3D pinctrl-mt76x8.o -obj-$(CONFIG_PINCTRL_RT2880) +=3D pinctrl-rt2880.o -obj-$(CONFIG_PINCTRL_RT305X) +=3D pinctrl-rt305x.o -obj-$(CONFIG_PINCTRL_RT3883) +=3D pinctrl-rt3883.o --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C423BC76196 for ; Fri, 17 Mar 2023 21:31:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230397AbjCQVa6 (ORCPT ); Fri, 17 Mar 2023 17:30:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230332AbjCQVat (ORCPT ); Fri, 17 Mar 2023 17:30:49 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0011DCC2E; Fri, 17 Mar 2023 14:30:30 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id ek18so25428718edb.6; Fri, 17 Mar 2023 14:30:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gB9wsR/QejWKnTpjqpalvhn0ClVxLzlxnCNLg5LJDYI=; b=DeEVrrd12HU2BAG6cPFbACSL4/hWSMKzky1XNI+Efkafor07HEaRDFq/E128YGgf2C zNjp4F2Ls3MSXdI4ClYk2mXmcL04SPTUNpQH/xFA3c4RM8Yt2LdS0/zLfv4c2HMBUkXD z5ha+4wbHknDdoU69qzbdpMwQIoQrKIHUR4yWFaSv+sgQWSjkEJWk03aj/CfkF6Rpniw wOm90IAoZ2aD7TVsfb1dAfmL5R67VyTgKfIYUnnAQZzkyLHZDcGc/oLpUj4b2X+xQNdd ecuMxnMIBf2zX+HNIU4LTCTg7VbtZ0ABEoOWWhVtyZ3zRiAU5LbxfmgpK+BfBVwAuzLy ftjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gB9wsR/QejWKnTpjqpalvhn0ClVxLzlxnCNLg5LJDYI=; b=JfedRP5j401mzqyEHJbqeScBXkU8eIgBMByoPC3kNbNUrNd1UwrNVwKhBhAcCbrXUw rVFiFwUuXXRx2+lBZmoHQQ8aAtbTg4Ui7xZY2yD6Nz1qYN+slV01GoSI124JPt+ZVLti tXt/dUfGdG0gihnPFJbeN0mMO5jHrnKj/c9ebtf8jZKHyX6plAcCfA7GDB7CSaY8Wjpf +qZPVpAjiLJk+kZ3w3QBOEg6Zy2dBo0tA7baqttCCAgn161XRK4qMysQfQ1YolmWnkAs OMn5km/Ja6WDeaj+7GDI05azD+1AjSVkhoJSt0JXkhsV8kQEQjPuYgQzKoWW3gewgHwH DfKQ== X-Gm-Message-State: AO0yUKVC+03pZxMZISlX0zJbg3hHON+dvtaqjlwo7knmV2AxIpcrrbhL RJOOI7hRQbC85pNMB0mTsE4= X-Google-Smtp-Source: AK7set9ZDd1hJkSDFx7yupS27zfy8fGrjwhkV7qA9C6gFSRh6OVgFYg7DSrCVPDblSg/8gD6iJ6iFw== X-Received: by 2002:a17:907:31cd:b0:8e1:12b6:a8fc with SMTP id xf13-20020a17090731cd00b008e112b6a8fcmr954836ejb.4.1679088629209; Fri, 17 Mar 2023 14:30:29 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:28 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 05/21] pinctrl: mediatek: remove OF_GPIO as reverse dependency Date: Sat, 18 Mar 2023 00:29:55 +0300 Message-Id: <20230317213011.13656-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The OF_GPIO option is enabled by default when GPIOLIB is enabled, and cannot be disabled. Remove it as a reverse dependency where GPIOLIB is also set as a reverse dependency. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Sergio Paracuellos Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kc= onfig index ba21a599953c..ee04b1af36dd 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -17,7 +17,6 @@ config PINCTRL_MTK select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO =20 config PINCTRL_MTK_V2 tristate @@ -35,7 +34,6 @@ config PINCTRL_MTK_MOORE select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GPIOLIB - select OF_GPIO select EINT_MTK select PINCTRL_MTK_V2 =20 @@ -46,7 +44,6 @@ config PINCTRL_MTK_PARIS select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO select PINCTRL_MTK_V2 =20 # For MIPS SoCs --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B355C74A5B for ; Fri, 17 Mar 2023 21:31:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230490AbjCQVbG (ORCPT ); Fri, 17 Mar 2023 17:31:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230395AbjCQVau (ORCPT ); Fri, 17 Mar 2023 17:30:50 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AE0D47835; Fri, 17 Mar 2023 14:30:33 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id r11so25443266edd.5; Fri, 17 Mar 2023 14:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hanRZ+so1ArYmepo5CCKfRMoCoks9bBU/s/2qIAgcfA=; b=ROtgY41T1mOUeAcWsz3h2hwpWmqmsiAYvHi8MtcsIKwe9n1jmGo5bS4Ztw1lJ5GSuo wt7WpnMJZNM8bht2BbO28u2/ck60OCTwmy1UEQg3ZmsHu74i/fEWwO5RAAcNurb6xgSe G3wahpAR4MrUMoEmlwNtW+7KOMdYey9JnJkI2pdILB71svg6WvEom+Ive++MLl2VHwGs uyz9CY3+FWgTj4SjLn0jW4WHONkK3X7GhHP1ZcWxHnySP5dIi/kDeg2pt+Ls5Cf+wV62 +NxAXlkNs370AvC6NdOpayuUruHNaqQHPGpnDXoqtPVUsnYRUX458Vc7M4TBzPFKPiqu km4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hanRZ+so1ArYmepo5CCKfRMoCoks9bBU/s/2qIAgcfA=; b=uMYaLYaN+RRoLYk0PoF2Kar/AJK2rXiabMzc+D3frWVStDfYvND07rPcUWNTVocsju HUaBz0yDYr5nX9c9sc1d2UtGFzQDUZVa9jYBWfUnQWGwmsdaaY+3rFab0INWYfRTWo0G 4jS8dGmE4tTvRnvMXSeiSTYPtdkpAAIGDrPOJsifHVRgqZskwJy8ClXSAhfDdTrE5YNP GhW7PqEMHg57kXRqgRnOs0rizJRTLkNYCyrMV6Kv6kc4+3TGpWFDCdJhqy0+Gu381fMe u2xNQgUAbml42CSXaUUqaKUcI31llthEay1HLBQUn9lM6Xdrvs3lHb/TkBS/6fl2WLKl Ue0g== X-Gm-Message-State: AO0yUKWFEgGBPgoZdmJFcTRBITyJu2eM9ttb1jK4fR1fdjRICwqqG8EY guiuZA1E+9YXBwVBYx6uUWLL8A1/ZiaYnISJ X-Google-Smtp-Source: AK7set9DUcJ6esYQL+HblhXNZcVXi9BWwPw82pZ6p5dHNh8f5Q2liYaFJQnTMyg1nF/Hika2gJc5jg== X-Received: by 2002:aa7:d4d6:0:b0:4ea:a9b0:a511 with SMTP id t22-20020aa7d4d6000000b004eaa9b0a511mr4986552edr.37.1679088631693; Fri, 17 Mar 2023 14:30:31 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:31 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 06/21] dt-bindings: pinctrl: ralink: move additionalProperties to top Date: Sat, 18 Mar 2023 00:29:56 +0300 Message-Id: <20230317213011.13656-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Move additionalProperties to the top. It's easier to read than after a long indented section. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 7 +++---- .../devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml | 7 +++---- 5 files changed, 15 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.ya= ml index 1e63ea34146a..b25e0db77cb3 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false =20 properties: function: @@ -632,10 +635,6 @@ patternProperties: groups: enum: [i2c, spi cs1, uart0] =20 - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.ya= ml index 1b1d37b981d9..60f6273930f5 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false =20 properties: function: @@ -236,10 +239,6 @@ patternProperties: groups: enum: [wdt] =20 - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.ya= ml index 7fd0df880a76..4f3e0af7d18f 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false =20 properties: function: @@ -116,10 +119,6 @@ patternProperties: groups: enum: [pci] =20 - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.ya= ml index 4d66ca752a30..9e45d851def6 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -23,11 +23,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false =20 properties: function: @@ -249,10 +252,6 @@ patternProperties: groups: enum: [spi_cs1] =20 - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.ya= ml index 008d93181aea..4bea19d4ad7b 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -22,11 +22,14 @@ properties: patternProperties: '-pins$': type: object + additionalProperties: false + patternProperties: '^(.*-)?pinmux$': type: object description: node for pinctrl. $ref: pinmux-node.yaml# + additionalProperties: false =20 properties: function: @@ -236,10 +239,6 @@ patternProperties: groups: enum: [uartlite] =20 - additionalProperties: false - - additionalProperties: false - allOf: - $ref: "pinctrl.yaml#" =20 --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D28BC6FD1D for ; Fri, 17 Mar 2023 21:31:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230482AbjCQVbD (ORCPT ); Fri, 17 Mar 2023 17:31:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230392AbjCQVau (ORCPT ); Fri, 17 Mar 2023 17:30:50 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 903A1E20C1; Fri, 17 Mar 2023 14:30:35 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id eg48so25308637edb.13; Fri, 17 Mar 2023 14:30:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=imSdKESnCC1MBR2YzRMTFgBDDXfRknOlbZyCB5yh06c=; b=JpHfGble1mO+xcp/MJMztTDj9xhTtiLor+bYEdLI2j+CbiKfj6pQZajunr6s9uU9ud 424aZrWQEiuUogLWsrw5kil7ZmeNWSuElQDYEFMwguMZs3/3auF6REcyjMSklXet3NHl bU4o8xEQCn3uXkOBxVLjSek+90M2CfqE7CWQZ8zuieX2lcrpU0mqWpB3IPR0et2ch0TW L55HOaHsPn+R8lQoEFI64bua6fYLJEk6jYpASKKQ19H/1WbEATMffqTal+IQDxMn1Ql9 NHdskLK+huMK8f/opAunI1XLOsEGXXpGSGgSvea4UunYov3kOEAkgWL7Vy6Uan8zOxxM UO5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088634; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=imSdKESnCC1MBR2YzRMTFgBDDXfRknOlbZyCB5yh06c=; b=41Oi9GIjry+p/FjUaBfMn6Nrd8O7oQW8RBSZEAxQemtQm2gNKUeOp1iWmPTzSuKN4g 2jYWLNgxKYZOGEgu9IjM8eBHYF09RN3HgV5iAMaXn2OjkusmxLEIZVbLuaNbMnTomjuG KWEwNvycTQvNLU+p0uER4Cxqyho8MhogskQku9PejJ8h15jvxePrXCOgjA7c6MR+YIZC CbuE4qxSeUlIvYG3Q2CIkSRFUYMYxyWGUo67RvlHVKr/kgiFJxOIOb4ZDII0yyY6dKar SbanFk/2mVGhhAe5h5l0hr20kMgJwDzQ5USTKnThVkJvovWSsb4MqMNBBWU7IWWMAXfy MJvg== X-Gm-Message-State: AO0yUKUmB3KePcXubodi9INV8Xk3bK40N71xWXQtRAiezpnLWuyVRVcN R/kNqCvAKG9B3/qc/TN1t90= X-Google-Smtp-Source: AK7set82qp1rlYyl24drBNGiPpp0eT3ew+aSiuh+pteB/kV4CuKFvgRKtmCOw/3Y7DBorEs2QKSR+Q== X-Received: by 2002:a17:906:4704:b0:84d:4e4f:1f85 with SMTP id y4-20020a170906470400b0084d4e4f1f85mr638914ejq.59.1679088634214; Fri, 17 Mar 2023 14:30:34 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:33 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 07/21] dt-bindings: pinctrl: ralink: drop quotes from referred schemas Date: Sat, 18 Mar 2023 00:29:57 +0300 Message-Id: <20230317213011.13656-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Drop the quotes from the referred schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.ya= ml index b25e0db77cb3..cde6de77e228 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -636,7 +636,7 @@ patternProperties: enum: [i2c, spi cs1, uart0] =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.ya= ml index 60f6273930f5..fb8c5459ea93 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -240,7 +240,7 @@ patternProperties: enum: [wdt] =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.ya= ml index 4f3e0af7d18f..e51667316b2e 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -120,7 +120,7 @@ patternProperties: enum: [pci] =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.ya= ml index 9e45d851def6..8b1256af09c3 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -253,7 +253,7 @@ patternProperties: enum: [spi_cs1] =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.ya= ml index 4bea19d4ad7b..adc4f42a175d 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -240,7 +240,7 @@ patternProperties: enum: [uartlite] =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42801C76195 for ; Fri, 17 Mar 2023 21:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230446AbjCQVbN (ORCPT ); Fri, 17 Mar 2023 17:31:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230410AbjCQVaw (ORCPT ); Fri, 17 Mar 2023 17:30:52 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBF43E4C41; Fri, 17 Mar 2023 14:30:37 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id z21so25476360edb.4; Fri, 17 Mar 2023 14:30:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=831eezpQQ1y/Bza6SFUBg+0j0MfEOywRdTuqRTBfi2A=; b=FZP2v4NhwY9EMcMyXAOB/4mR5Uaqqjjjo/eSIVX3nNmoMsoG3W3WauJzviFMQdrPuv r0ax7LrM9Dk5vxnQ1buyq5JGDDbJBGz8Frn/iuIKVRm3sOlZ3lfkjUKfYgdj1uE5CEWP 247fcpcKXb1cjGcN3Z03xaBrwA/YnYLqP0DZDL9FlKU+W3AQajMzHi1b/aUMthaIy03g iVK9ykoOZKd2+krO7312/Cgopejv7cSGOuFQ4Fd9/ldnfMlUGgoohOE3eRPDjABBgl5m 34AkRUg08tKXJuWes5+KJmO7dbZbehsxCSJslayDahtQneaAkjheCgw3ROMuDJ8Qasry 04Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=831eezpQQ1y/Bza6SFUBg+0j0MfEOywRdTuqRTBfi2A=; b=LXBkETVPNwL5IFOg/MDwOsxUkq00L4LVilIMtTQgjgftDi4i8/p9oDwNT28E7Wi1/M M9M+S2kiewV/IymH4dlQusZb44aC8FTZINbVmAw5uwb2uKefPD7W9RikSeBuiLWLMWiB 64E7vYewpgzeqoeWnlYt/CRkGnLuuPkky8sH57+xaILywMi/QgIiBqBM0oKwgV+AdJyB 48d411zpfudYNz+87DMqBK1vDu4kbeoWR+n9fnADUDZMv+bZOGfn6MlJfxB48zIDrDty GR30/bS5aPRqwHdNeAla4EUuCT9NeFXJhu0lCxOPbYv67OYUuSS1tjxISWtc0wDf/1l8 7ohA== X-Gm-Message-State: AO0yUKVTAM4RDnK4vT6bOKjhvGfF/VaFePdvlBizyPcHVuFGA2wvmYmF 7XPa3aCjXuZKEZP31a4xbnCs0lPVB3d+CgsF X-Google-Smtp-Source: AK7set9JPZMCF+E0gStn6M7piSEshol9kTKXaImBhSCtm+waAogNmPksEqhtUxggIfKyH7peDZgUJA== X-Received: by 2002:a17:906:51d0:b0:92f:c6b5:de08 with SMTP id v16-20020a17090651d000b0092fc6b5de08mr711214ejk.76.1679088636688; Fri, 17 Mar 2023 14:30:36 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:36 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 08/21] dt-bindings: pinctrl: ralink: add new compatible strings Date: Sat, 18 Mar 2023 00:29:58 +0300 Message-Id: <20230317213011.13656-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add the new compatible strings for mt7620, mt76x8, and rt305x to be able to properly document the pin muxing information of each SoC, or SoCs that use the same pinmux data. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 4 +++- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 5 ++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.ya= ml index cde6de77e228..09ebb8ac22ac 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -17,7 +17,9 @@ description: =20 properties: compatible: - const: ralink,mt7620-pinctrl + enum: + - ralink,mt7620-pinctrl + - ralink,mt76x8-pinctrl =20 patternProperties: '-pins$': diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.ya= ml index 8b1256af09c3..23fb82f9959c 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -18,7 +18,10 @@ description: =20 properties: compatible: - const: ralink,rt305x-pinctrl + enum: + - ralink,rt305x-pinctrl + - ralink,rt3352-pinctrl + - ralink,rt5350-pinctrl =20 patternProperties: '-pins$': --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B22D8C7619A for ; Fri, 17 Mar 2023 21:31:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230500AbjCQVbW (ORCPT ); Fri, 17 Mar 2023 17:31:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43010 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230492AbjCQVbH (ORCPT ); Fri, 17 Mar 2023 17:31:07 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71E6D60D41; Fri, 17 Mar 2023 14:30:41 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id z21so25476710edb.4; Fri, 17 Mar 2023 14:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g3sp6QmVh7Rvu6BYvs/4TvtXukT0lH08BB5qr/XfDtE=; b=GdqMRlbbMdqy6mBryn6qXANvu20qLcsphW6f1CwS2ByufSCoUvCno/NyxPCmjwTkvl H1TqqmMvztp/DMucW1PN7pMx9B2Ufue7tAApNNk8OzbjkwUc9sizLC29NBeXchmO5R8z T8A/ouG2DUMLdZw13luqQ9wv2z5xKY+xJN0dXpvOEjmv4uSW1dRVaWkcYfR7IkoShKJm lcT/MZAVPZr0XcFp3tTJZZSDa6i6M/nQSsqWVOqQcqe/YeaqalcfBw8ZuKkCVd/0RKjN wTtbAB8n+DZIJe3G/Shq0GdMO4ymTpRPYgkkm9/jLHJ8ZzZhamNfQBhV/JJf4SklK1zu x/Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g3sp6QmVh7Rvu6BYvs/4TvtXukT0lH08BB5qr/XfDtE=; b=T9/N71WAx5p6sUVwO+QB82Fejm+NlnvDsTHaNkhF6Rfh+J34rcwvMf4k4hJ+KEHipF niOel0H7/bY/QLf/y+TpfcDb9EEcl+RpqkjRWRf+kZXnimi1K2iVJWiAKexhvuzxg9vB pKet+rsuc9aKiLPpFRZMZWTBoh4ohZw+3hJipSapjfs1+uRfFlCBzqrf6aU9WzDYowkd BfMeAcQPb6nL+9H2GwLsZNv6H8TKdUYh9aICaqyl3DMeUMK86/gknmtH+CmQWBOT5R7Z N98y+6VCcND+shzprR0Wz+sdgbj+fhrvbCr1XOv6Ppo3ZE5V5WlGM0SCPi0E9spZjETy iCPw== X-Gm-Message-State: AO0yUKV+Kn4IyA/atV4hwOuA8vpPmET08cp4dZ5fRk7N7NbdMmz9V21d FiDPNNHJljm/UUZkJPVgaSg= X-Google-Smtp-Source: AK7set/9K2BNiDB/LyvS/AlwDYgBXQTTnanfENeD02BnpjOWxSsJ3zmb4GYZB96xyu/KaC775A3WmQ== X-Received: by 2002:a17:906:2a51:b0:87f:5d0a:c610 with SMTP id k17-20020a1709062a5100b0087f5d0ac610mr774374eje.32.1679088639122; Fri, 17 Mar 2023 14:30:39 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:38 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 09/21] dt-bindings: pinctrl: ralink: {mt7620,mt7621}: rename to mediatek Date: Sat, 18 Mar 2023 00:29:59 +0300 Message-Id: <20230317213011.13656-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename schemas of pin controllers for MediaTek MT7620 and MT7621 SoCs to be on par with other pin controllers for MediaTek SoCs. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- ...ink,mt7620-pinctrl.yaml =3D> mediatek,mt7620-pinctrl.yaml} | 6 +++--- ...ink,mt7621-pinctrl.yaml =3D> mediatek,mt7621-pinctrl.yaml} | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7620-pinctrl.ya= ml =3D> mediatek,mt7620-pinctrl.yaml} (98%) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7621-pinctrl.ya= ml =3D> mediatek,mt7621-pinctrl.yaml} (97%) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.= yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl= .yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl= .yaml index 09ebb8ac22ac..0dcdc3788e66 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Ralink MT7620 Pin Controller +title: MediaTek MT7620 Pin Controller =20 maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 description: - Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.= yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl= .yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl= .yaml index fb8c5459ea93..32506c538459 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Ralink MT7621 Pin Controller +title: MediaTek MT7621 Pin Controller =20 maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 description: - Ralink MT7621 pin controller for MT7621 SoC. + MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B25C0C74A5B for ; Fri, 17 Mar 2023 21:31:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231153AbjCQVb0 (ORCPT ); Fri, 17 Mar 2023 17:31:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230402AbjCQVbK (ORCPT ); Fri, 17 Mar 2023 17:31:10 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CB7A145B66; Fri, 17 Mar 2023 14:30:43 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id r11so25444788edd.5; Fri, 17 Mar 2023 14:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088642; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WT6hzu0DmgFDhxzzLNhQjlkkdnwsxET9D8SPDLbHKjA=; b=UEYfnjckvyeT4ff+QOXYlCo1x0vkS+97iJsTIz5oFMWcTba0RcyN4rXJ8vPaUYhG6l v67MSNk2sy7ml1YgGgv1ccNs9CY0pslZzfhAeBYfi0mUbOFP202jj3/QA2rLxgA05uwA 6W6fiyoeyELDX67v47zpoeSYm+2fLsjeR2mYkcMEJJQGMMfeGV0XjFi9WnWq0P2JF7xE 5DB+gaaBd/7M3h473Ea4Xhfp706z2NyX+9ILn3URTmuvJLpDGklt2+1tJINvH75aoSrO /yISzzEN6WNm33sDxOxS7JU6vm2Krh9bJ4ZtiAmznusxeIb61o60mMuNVsV6zT3Ki18M Hsig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088642; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WT6hzu0DmgFDhxzzLNhQjlkkdnwsxET9D8SPDLbHKjA=; b=NjwZ3bpSZcLhNKg3ryCIMf97XoUbmi5UoaXGVMqRGtMjJTOgMDucEmoDiNmJBCh3lK /WJOpGveyxwxVYOBcuajg6oqdRBwJLY6mOfhBYAsw9vVA3V4bFdn6spp73QfUQwDue6N HJ0DclGbCzq5pWrtGMms8g5Bcxf/iXqKjOUOHluKZLFiW0a80SYqiYB4vZQ4wmx8SEHp +b3tfO5ptFiDnw2VQsKPWb9jH0Xf/lKTdzi0XYCptRBXfNd+jn5FeIju55fU3cnFFsQZ Hjodd9OEiluI/r64CXqSRVv4X/1HTMX1vcX5YazOsjGC5JRn9uQ2Gc+5PbkjMT+1wgzU AGSQ== X-Gm-Message-State: AO0yUKUl7NiX7hrlz6SQVe9cuAaeIXh+NQj2hIPl0F//pg5N+SkLLCZa xsigKoCSb9zOm1zwh+AKJak= X-Google-Smtp-Source: AK7set9o7vfI9g2tW01l5H0yRVqz8bipCXXGTjL299vsol3YqeirzwA6JaKCs9+IdMWE6xdzPmV/5g== X-Received: by 2002:a17:906:c2d5:b0:92f:d900:9c66 with SMTP id ch21-20020a170906c2d500b0092fd9009c66mr899947ejb.10.1679088641575; Fri, 17 Mar 2023 14:30:41 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:41 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 10/21] dt-bindings: pinctrl: mediatek: mt6795: rename to mediatek,mt6795-pinctrl Date: Sat, 18 Mar 2023 00:30:00 +0300 Message-Id: <20230317213011.13656-11-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename mediatek,pinctrl-mt6795.yaml to mediatek,mt6795-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- ...ediatek,pinctrl-mt6795.yaml =3D> mediatek,mt6795-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{mediatek,pinctrl-mt6795.= yaml =3D> mediatek,mt6795-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6= 795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctr= l.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt67= 95.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl= .yaml index 9399e0215526..c5131f053b61 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT6795 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFE27C77B61 for ; Fri, 17 Mar 2023 21:31:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231171AbjCQVbj (ORCPT ); Fri, 17 Mar 2023 17:31:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230410AbjCQVbO (ORCPT ); Fri, 17 Mar 2023 17:31:14 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C81F2F04D; Fri, 17 Mar 2023 14:30:47 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id eh3so25369701edb.11; Fri, 17 Mar 2023 14:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F8438bEydUlrPZrkVMSwHAqPRPD9BxspbjMsnayfq+s=; b=BKQ1OiJAvSoi6GkGS20VepyAZM2aTwKrXTe4Ydz1TSkodfhZrKh8lT9EDNJDHEjOmU UWH8sM+IvQ5tGgoLfe8AcROvIYDEi/blCyXacpL+2Y2fry6S19VwnxFlmGn7c9tfE0LU VRQwJLXqxH2xf2VXLFnngDReFs0Gi3upAk3JGMDOBIw4x6BXA8Nv3W48+gR3vX7y1a88 W65qEaKoMl0650ce4rzfomFy7ZhPkSOKRNwj1sspUl9SeG1SDGBhqfDVsL14WcCfYKrp 2mWAyyLceE4zFuozksoNNhqpeQw/GsHLliaIuvyqNXfeMd0Nv85/JQoQAZp0fBoe8ldJ 1emA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F8438bEydUlrPZrkVMSwHAqPRPD9BxspbjMsnayfq+s=; b=PEz6iYLJ+8IU9kSmOKdUY24/aoZYCAB9NnROEtrzToJVJNzVBt3uNpkS2mPgR5K69C s5Zcki1EIc2b75nYXleMcbwVqMqlSMJ0Gckq3AIPVU/Y3WK1Slv6BaOsFaC85U2KbpYK JsWdZbzeGKqBdjJgOFZMuuYu7g6juBouRnlYS3N+j9k8l6g4d/VPU3Tgfa36KSwvMhQb wVR+fAhJIiMAE5OL2xevOXI/WVOnTFJeTIfh+58GIGU3cG1B9Q710+TCQmx5yl3JTBW/ w3hDOzxtfqjDstIRerQBSucbMUxgX4ZHKD/6qF9uxhv1Q4Bun3PUq76qdrTcbFt/id96 jIXQ== X-Gm-Message-State: AO0yUKU4jDB8gAY4BmWKVUYRn8/fK12GdQXw1lzhKxhICa/UhorMAvP3 AfgTL3t5WpfptLpknK9LHRc= X-Google-Smtp-Source: AK7set9WdDW37amJ7JOELl+SoaTQ+kMULS23MCFyTGLUsyOVdgPMIEeQ75qrnhAz2a9GQMdJyXcBVA== X-Received: by 2002:a17:907:a04f:b0:931:51c0:7300 with SMTP id gz15-20020a170907a04f00b0093151c07300mr665581ejc.77.1679088644180; Fri, 17 Mar 2023 14:30:44 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:43 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 11/21] dt-bindings: pinctrl: mediatek: mt8186: rename to mediatek,mt8186-pinctrl Date: Sat, 18 Mar 2023 00:30:01 +0300 Message-Id: <20230317213011.13656-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename pinctrl-mt8186.yaml to mediatek,mt8186-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../{pinctrl-mt8186.yaml =3D> mediatek,mt8186-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8186.yaml =3D>= mediatek,mt8186-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml = b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl= .yaml index 26573a793b57..32d64416eb16 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT8186 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DB49C74A5B for ; Fri, 17 Mar 2023 21:31:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231219AbjCQVbq (ORCPT ); Fri, 17 Mar 2023 17:31:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230450AbjCQVbR (ORCPT ); Fri, 17 Mar 2023 17:31:17 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AD0A2F054; Fri, 17 Mar 2023 14:30:48 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id w9so25496795edc.3; Fri, 17 Mar 2023 14:30:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jBoLaLgAfnzJMOco92w0PZhMXyCzsUA5lEBWwlGN0ao=; b=c/rn5V3gsaXFcP0ZsLg66GCLxi7bukAkbNoDtS44ArFLEtbqAIKSL4OEf2Do8hQ7Qg s/spPfzoPZrR9GXdgQEJ1/GI+PVdnshVibG40gVzbL5vxFsz/KuJoJjzQ9KZeHfoHKnw uJy5qoB0B35k0ndW2nJAVy/iijmT9wQePF4leu2DibuCqRtOA5d2KlTUa6cDxLqtxkVL kxJXJxZ+yAsMsmF2WR2Y/FLrmcc6tvZAN0c/wafC7ynTEvGmUBxO8jn1lRLmnLKo/MDV Quq2vUREm7PYDhXDFJNzqDzUqVAeSeMnArc1iM3ofkzZITEJtfyTcRxsIGyBua8qldID 7S1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jBoLaLgAfnzJMOco92w0PZhMXyCzsUA5lEBWwlGN0ao=; b=pGFSoHtGYcOajpSLOQkXtkjkIP/OKqruJfFNP43L99TkA6kcZsr9JeKzrsQ3uUtHIg 2cTkGfJFMm6gDKzgSpwNunOFO6FKoymqC9Qj/DPyQaRItAPOzzTLuNOXEYsFnmbbCVdL rmX/fwGYqGhy6n7uWv2VwrAk6xDWu/9jjRBiwXVDteLAtwhfcERMnxgzxc6AefxnB89p HToCNJ9UQLNsSoBfLYW4n8yoszwFp7VK1Fo0NlrF7sPHHeL55DYIsrRZG1S5wDYGPhTa Nk0Pb68Q/0jW30/eql5wxP99rOO8IpzB3auUL9yk61Z1SkMhASPvq0Ag+lFhw4nfc2Nw FnAw== X-Gm-Message-State: AO0yUKWBaQcDM1MOpq4e3AaFYtX4Nc9nlb8ELJRXyJ257yUuOO6TwSu6 rjoCMud0SkSzu2y4ANrRJQQ= X-Google-Smtp-Source: AK7set+OQPuC4DWsozzV9ZDx0KyTGxxvuHxSGkd8klGTQvLrDpud4gQhsGXkpPv+kraHJ7a+HxgL1g== X-Received: by 2002:a17:906:c183:b0:92f:17d:4438 with SMTP id g3-20020a170906c18300b0092f017d4438mr969149ejz.47.1679088646676; Fri, 17 Mar 2023 14:30:46 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:46 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 12/21] dt-bindings: pinctrl: mediatek: mt8192: rename to mediatek,mt8192-pinctrl Date: Sat, 18 Mar 2023 00:30:02 +0300 Message-Id: <20230317213011.13656-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename pinctrl-mt8192.yaml to mediatek,mt8192-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../{pinctrl-mt8192.yaml =3D> mediatek,mt8192-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8192.yaml =3D>= mediatek,mt8192-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml = b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl= .yaml index e0e943e5b874..e764cb0f8c1a 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT8192 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A837C76195 for ; Fri, 17 Mar 2023 21:31:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231181AbjCQVbn (ORCPT ); Fri, 17 Mar 2023 17:31:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230370AbjCQVbP (ORCPT ); Fri, 17 Mar 2023 17:31:15 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1B7122797; Fri, 17 Mar 2023 14:30:49 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id ek18so25431553edb.6; Fri, 17 Mar 2023 14:30:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S1EO681NLLyGQFHGfJf2gv1cVQUWKJ2bHIXepwv2glw=; b=Nj/yv883NrbobitzXaKxcYWACXTNOv5IeesF3v8/SYibxX7Grd0zQqBqRo4aCNf69P qs7cv6Z2pLjSi7PElPIjTE4yFfkXsoSfNvHxfySPguyzaLHoH642t208C/4SVMfSeWF0 oh9gqCBMXwmn9zU/HJae0O6YN1pLywu5otcUDIceCk6Xv/lmDfMeXwqOFhhVdwCo5Noy VoCNAgl5EY/ijB6idyAoam0qDGZl7K4riAk/4VQrja4PiHsvvcwYyMRom5cjQNHCpdfN x80AsQxCu1At9LqN3Z8sI9eig9SOocDcs8Nl8gK1CvesJeQvCKFNRX9CDsl4THoATuAs 1NSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S1EO681NLLyGQFHGfJf2gv1cVQUWKJ2bHIXepwv2glw=; b=scb/ZBOY59hi2BWEzU1pEFoxvcAhixM8epOhIwIdS78DkCq//Sgqjx1azOX0kgO1rI FyDegi1fQ6yZaqoEHHSZgRpsYDiCjH7Wkdc/Jp1EgeclLy+xa3wdY0hfus+iLEPtssxg qBqTiKNQ554Koul/YcVgxRstd9l7UmAaQ7BQPYBnsccHRHRGKZxuFIR6vBMEsm49S4r3 AwBvwogaKvt98cozoWTlrD60zVgr7PSgnt2YpRP9N28T+NuGfxGo3x+GOCfY1CihRg6q jiNu+bXxDDcX/g5bTjc8L+NIrpqF2NPWzN/r4TXfJIX5zUwgMokTYD9aZLXd253FtHY9 1IBw== X-Gm-Message-State: AO0yUKWpcPKK8OCM3TWDScFxCZfmJk0+kFQSHDCiH6UutcNHkyKfr7JT /P+QUfq0XA2QyaWRtlCQqBc= X-Google-Smtp-Source: AK7set8exkSeTiGGFVcm4bMaCRqAh37sCsa47AQqZCcy7GGsu7JIZnViKmVXS1DpDenp0lpJfstl0A== X-Received: by 2002:a05:6402:7c3:b0:4fa:4b1c:5ea3 with SMTP id u3-20020a05640207c300b004fa4b1c5ea3mr4692669edy.23.1679088649113; Fri, 17 Mar 2023 14:30:49 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:48 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 13/21] dt-bindings: pinctrl: mediatek: mt8195: rename to mediatek,mt8195-pinctrl Date: Sat, 18 Mar 2023 00:30:03 +0300 Message-Id: <20230317213011.13656-14-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Rename pinctrl-mt8195.yaml to mediatek,mt8195-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../{pinctrl-mt8195.yaml =3D> mediatek,mt8195-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8195.yaml =3D>= mediatek,mt8195-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml = b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl= .yaml index 66fe17e9e4d3..7b3dfc14eedc 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Mediatek MT8195 Pin Controller --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84F2DC74A5B for ; Fri, 17 Mar 2023 21:31:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231144AbjCQVbt (ORCPT ); Fri, 17 Mar 2023 17:31:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230462AbjCQVbU (ORCPT ); Fri, 17 Mar 2023 17:31:20 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EC432F066; Fri, 17 Mar 2023 14:30:54 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id y4so25506177edo.2; Fri, 17 Mar 2023 14:30:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b9p6wOBW5PQerq1HTDlv49KWPwyL5YVG4dkYohadujA=; b=Y1q8QX8fRYbHlhtBrofBLj8DHlx58qpzQNb2sU660jMYBN0Cvcu2wiBXRKD5v14jDQ MoUm3JyBSMR2hueHrlm5SE1/rdc0uv0lGM/vKflFx7Ur7VpNmepcnOoaZV9aEZifZzn3 VwZAU+zKUBLPUsJplSTaT/hJRbDwRRrXvO6YHcKsHb6UxcczqDtWb6dY1DPkuVq93dHX EotKsaotbGWLuGzxPKFwmJGWlL9E8EAQpfGLWEpfpXXdyDk2xBuMY3J3SviRfoZj9VqD AqVyCWZ8fg0AblH035+Jiin60j4ZUtLPz85nHU1L1oWQ30kS6CoZsVNftsXd3y7nCfOU HrpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b9p6wOBW5PQerq1HTDlv49KWPwyL5YVG4dkYohadujA=; b=7BChCISIDIJ5dN9eXe4JLbkrjGo5fpCQ8ZoJr4Je2OrFB40sFxLNHDJaVnd5t0x+DM Tk1ZUcTSrHXcBUhMrdQNw73rUM5VmfWE4L17prbeU6xOS2knQG1iFeM4FoGUCcQwYPDy y4ygfYEBB2ZM2k9S8/ue56MevFwj+pyw5xEOewnSY/1Mc8owLhQmf7HcD2D8abJdatZa rNbqOCZ2cHQfMCKYUrxaSnEKzLvJimUOElf33r0JPuitLYmbmqsWd+I6lpKBCPfrJUon r84+WoTUzZkUkKBb560pPFflrTww6VZrX27pNMVO/9G9OKUSY4raAbCNocOm5b1fuPZ/ BUog== X-Gm-Message-State: AO0yUKVJuIKYpKK++YtR6NETAuuTrCat+fJKIyXbLh0lgPbb8sKHsjPT o+FM+8AAtpPTvVQM+oAbaDY= X-Google-Smtp-Source: AK7set+IGDu520sNWxrl5Nt2zELXj95368h87QzdpUDuEjvmJBAAH0mYRZTkmUFEZDIUfOSMgwKOkg== X-Received: by 2002:a17:907:7f87:b0:925:6bcb:4796 with SMTP id qk7-20020a1709077f8700b009256bcb4796mr951351ejc.38.1679088651611; Fri, 17 Mar 2023 14:30:51 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:51 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 14/21] dt-bindings: pinctrl: mediatek: fix naming inconsistency Date: Sat, 18 Mar 2023 00:30:04 +0300 Message-Id: <20230317213011.13656-15-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Some schemas include "MediaTek", some "Mediatek". Rename all to "MediaTek" to address the naming inconsistency. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml | 4 ++-- .../devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml | 2 +- 11 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctr= l.yaml index a55c8e4ff26e..77b1b52f5799 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT65xx Pin Controller +title: MediaTek MT65xx Pin Controller =20 maintainers: - Sean Wang =20 description: |+ - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT65xx Pin controller is used to control SoC pins. =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctr= l.yaml index a2141eb0854e..c2fea29fa02f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT6779 Pin Controller +title: MediaTek MT6779 Pin Controller =20 maintainers: - Andy Teng diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctr= l.yaml index c5131f053b61..a78df32e6c39 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT6795 Pin Controller +title: MediaTek MT6795 Pin Controller =20 maintainers: - AngeloGioacchino Del Regno - Sean Wang =20 description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT6795 Pin controller is used to control SoC pins. =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctr= l.yaml index ac93eb8f01a6..3531b63ca4bf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7622 Pin Controller +title: MediaTek MT7622 Pin Controller =20 maintainers: - Sean Wang diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctr= l.yaml index 74c66fbcb2ae..c3373290a8a1 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7981 Pin Controller +title: MediaTek MT7981 Pin Controller =20 maintainers: - Daniel Golle diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctr= l.yaml index 216b356cd519..71033831d03d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT7986 Pin Controller +title: MediaTek MT7986 Pin Controller =20 maintainers: - Sean Wang diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctr= l.yaml index c30cd0d010dd..3e34b03e11fc 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8183 Pin Controller +title: MediaTek MT8183 Pin Controller =20 maintainers: - Sean Wang diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctr= l.yaml index 32d64416eb16..a0519acc92fe 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8186 Pin Controller +title: MediaTek MT8186 Pin Controller =20 maintainers: - Sean Wang =20 description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT8186 Pin controller is used to control SoC pins. =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctr= l.yaml index e764cb0f8c1a..3c3dd142a989 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8192 Pin Controller +title: MediaTek MT8192 Pin Controller =20 maintainers: - Sean Wang =20 description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT8192 Pin controller is used to control SoC pins. =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctr= l.yaml index 7b3dfc14eedc..d4d5357cdd1d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8195 Pin Controller +title: MediaTek MT8195 Pin Controller =20 maintainers: - Sean Wang =20 description: | - The Mediatek's Pin controller is used to control SoC pins. + The MediaTek's MT8195 Pin controller is used to control SoC pins. =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctr= l.yaml index 4b96884a1afc..42964dfa9fdb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Mediatek MT8365 Pin Controller +title: MediaTek MT8365 Pin Controller =20 maintainers: - Zhiyong Tao --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCC4EC7618B for ; Fri, 17 Mar 2023 21:32:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231137AbjCQVcF (ORCPT ); Fri, 17 Mar 2023 17:32:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230419AbjCQVbf (ORCPT ); Fri, 17 Mar 2023 17:31:35 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F3932F07C; Fri, 17 Mar 2023 14:30:57 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id eg48so25311475edb.13; Fri, 17 Mar 2023 14:30:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C+Cbog22+6j+VeMCe1DOeI/RCKtalEeyJ2KLFOjeE24=; b=BximcnbpdSRuuS88COyoeeqbC3tBRXhEqTRpHldbjH1ZfoA5lN76Xzp7No9fEPLJjz ZBYvjHE7Auk+uuh1dipfWUyZnKWpOEXztr/8vOtoGKxgKRXuawprcXJS2MQWoOBb4989 fptJleglrrnq51uBcXZdt6UehL7cViLqcvbuBtb4rJ4bDxeBqe5juT5A9qyMQfuvcTSl 21WJV90azhdfEh3UgM3xvdRIPSPYCbYMJuIb8O4/3ECdCU0OQl01QqBXOjqMySoenhyW vjLOD0ZYDqNWeth6gPubQywwmtYmJkJnzk/XpAZRxME9aaKT4l6M188Ri6iyxJr3M/tj CK6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C+Cbog22+6j+VeMCe1DOeI/RCKtalEeyJ2KLFOjeE24=; b=k3qEY0xbY9SyNuI3O835ktuYyhXWUrTKemv4CcshhODgSwX/m/Z6mvmSdTeByYAPwt 4TEO/YM5cbpM0z74cnJ8IEHqWSikf+87n8eIKuUlLkQZZQuX+aylT/uT6d53j2IzKM+G I/pKPDMrZQqLbEa9mJ4yBe1H9TQLXI6oQJFlLRUJxVp8tATPK2k6ewjrELVkcG70DqAD jSi6Y9pMoyLB+TpstlRZcniz6NBziwW3wQmDQ02fC/DNn9WMb9bIR82QY1QJxLrW54u/ b0nTWxmVF+N7xOrHNtd+QmGmBdJ0KoW1AIe8PKXvqt+SBENZLDepQ4zSjjcTuvjDkp57 raOA== X-Gm-Message-State: AO0yUKVOz6KeZ9r7lNvC+6/WZf+cXx0g/Uzq6NidhO6gF3nJ21ppr4su /OThkBQoLc3H1jfOymsNmnY= X-Google-Smtp-Source: AK7set+IepPc2a8TznbC1ZVXswq+bHqZM81zMzV0a40YrvcG32iL6GZZ686SKAmBy6MZlwSfxV+95A== X-Received: by 2002:a17:906:5645:b0:932:e9c7:c32 with SMTP id v5-20020a170906564500b00932e9c70c32mr853224ejr.59.1679088654459; Fri, 17 Mar 2023 14:30:54 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:54 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 15/21] dt-bindings: pinctrl: {mediatek,ralink}: fix formatting Date: Sat, 18 Mar 2023 00:30:05 +0300 Message-Id: <20230317213011.13656-16-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Change the style of description properties to plain style where there's no need to preserve the line endings, and vice versa. Fix capitalisation and indentation. Fit the schemas to 80 columns for each line. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 22 +++--- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt6795-pinctrl.yaml | 41 +++++----- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7621-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7622-pinctrl.yaml | 26 +++---- .../pinctrl/mediatek,mt7981-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt7986-pinctrl.yaml | 68 ++++++++--------- .../pinctrl/mediatek,mt8183-pinctrl.yaml | 26 ++++--- .../pinctrl/mediatek,mt8186-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8188-pinctrl.yaml | 74 ++++++++++--------- .../pinctrl/mediatek,mt8192-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8195-pinctrl.yaml | 41 +++++----- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 28 +++---- .../pinctrl/ralink,rt2880-pinctrl.yaml | 2 +- .../pinctrl/ralink,rt305x-pinctrl.yaml | 2 +- .../pinctrl/ralink,rt3883-pinctrl.yaml | 2 +- 17 files changed, 258 insertions(+), 238 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctr= l.yaml index 77b1b52f5799..5e80621800a9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT65xx Pin Controller maintainers: - Sean Wang =20 -description: |+ +description: The MediaTek's MT65xx Pin controller is used to control SoC pins. =20 properties: @@ -30,7 +30,7 @@ properties: =20 pins-are-numbered: $ref: /schemas/types.yaml#/definitions/flag - description: | + description: Specify the subnodes are using numbered pinmux to specify pins. (UNU= SED) deprecated: true =20 @@ -38,10 +38,10 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 mediatek,pctl-regmap: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -49,7 +49,7 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. =20 interrupt-controller: true @@ -77,7 +77,7 @@ patternProperties: '(^pins|pins?$)': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer @@ -88,14 +88,14 @@ patternProperties: properties: pinmux: description: - integer array, represents gpio pin number and mux setting. + Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are defined as macros in -pinfunc.h directly. =20 bias-disable: true =20 bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pul= l up settings for 2 pull resistors, R0 and R1. User can configure= those special pins. Some macros have been defined for this usage, = such @@ -117,7 +117,7 @@ patternProperties: input-schmitt-disable: true =20 drive-strength: - description: | + description: Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE= _6mA, etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctr= l.yaml index c2fea29fa02f..1d038f6f8971 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -11,8 +11,8 @@ maintainers: - Sean Wang =20 description: - The MediaTek pin controller on MT6779 is used to control pin - functions, pull up/down resistance and drive strength options. + The MediaTek pin controller on MT6779 is used to control pin functions, = pull + up/down resistance and drive strength options. =20 properties: compatible: @@ -29,22 +29,22 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. =20 interrupt-controller: true =20 interrupts: maxItems: 1 - description: | + description: Specifies the summary IRQ. =20 "#interrupt-cells": @@ -118,19 +118,20 @@ patternProperties: patternProperties: '-pins*$': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and= input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. $ref: "/schemas/pinctrl/pincfg-node.yaml" =20 properties: pinmux: description: - integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and = are defined - as macros in boot/dts/-pinfunc.h directly. + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in boot/dts/-pinfunc.h directly. =20 bias-disable: true =20 @@ -159,7 +160,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -170,7 +172,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctr= l.yaml index a78df32e6c39..c3bf98749fa4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - AngeloGioacchino Del Regno - Sean Wang =20 -description: | +description: The MediaTek's MT6795 Pin controller is used to control SoC pins. =20 properties: @@ -20,10 +20,10 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: @@ -32,7 +32,7 @@ properties: =20 reg: description: - Physical address base for gpio base and eint registers. + Physical address base for GPIO base and eint registers. minItems: 2 =20 reg-names: @@ -65,8 +65,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -86,11 +86,10 @@ patternProperties: =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -100,20 +99,20 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull down PUPD/R0/R1 type define value. - description: | - For normal pull down type, it is not necessary to specify R= 1R0 - values; When pull down type is PUPD/R0/R1, adding R1R0 defi= nes - will set different resistance values. + description: + For normal pull down type, it is not necessary to specify R1= R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defin= es + will set different resistance values. =20 bias-pull-up: oneOf: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull up PUPD/R0/R1 type define value. - description: | - For normal pull up type, it is not necessary to specify R1R0 - values; When pull up type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. + description: + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines= will + set different resistance values. =20 bias-disable: true =20 @@ -132,7 +131,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -143,7 +143,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctr= l.yaml index 0dcdc3788e66..808dd8bd276f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctr= l.yaml index 32506c538459..e568b9c13727 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctr= l.yaml index 3531b63ca4bf..38dc41c735eb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT7622 Pin Controller maintainers: - Sean Wang =20 -description: |+ +description: The MediaTek's MT7622 Pin controller is used to control SoC pins. =20 properties: @@ -29,10 +29,10 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 interrupt-controller: true =20 @@ -68,18 +68,18 @@ patternProperties: '^mux(-|$)': type: object additionalProperties: false - description: | + description: pinmux configuration nodes. $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the g= roup. enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, s= d, spi, tdm, uart, watchdog, wifi] =20 groups: - description: | + description: An array of strings. Each string contains the name of a grou= p. =20 drive-strength: @@ -247,18 +247,18 @@ patternProperties: '^conf(-|$)': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" =20 properties: groups: - description: | + description: An array of strings. Each string contains the name of a grou= p. Valid values are the same as the pinmux node. =20 pins: - description: | + description: An array of strings. Each string contains the name of a pin. enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, = TXD0, RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SP= I_CS, @@ -315,14 +315,14 @@ patternProperties: enum: [0, 1] =20 mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arg= uments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 =20 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty= cycle when asserted (high pulse width adjustment). Valid arguments= are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctr= l.yaml index c3373290a8a1..10717cee9058 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -37,7 +37,7 @@ properties: =20 "#gpio-cells": const: 2 - description: > + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, the amount of cells must be specified as 2. See the below mentioned = gpio binding representation for description of particular cells. @@ -111,7 +111,9 @@ patternProperties: "watchdog1" "watchdog" 13 "udi" "udi" 9, 10, 11, 12, 13 "drv_vbus" "usb" 14 - "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 2= 2, 23, 24, 25 + "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 2= 2, 23, + 24, 25 + "snfi" "flash" 16, 17, 18, 19, 20, 21 "spi0" "spi" 16, 17, 18, 19 "spi0_wp_hold" "spi" 20, 21 @@ -148,7 +150,7 @@ patternProperties: "wf5g_led0" "led" 31 "wf5g_led1" "led" 35 "mt7531_int" "eth" 38 - "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 2= 1, 22 + "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 2= 1, 22, 23, 24, 25, 34, 35 =20 $ref: /schemas/pinctrl/pinmux-node.yaml @@ -256,7 +258,8 @@ patternProperties: then: properties: groups: - enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_le= d0, wf5g_led1] + enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_le= d0, + wf5g_led1] - if: properties: function: @@ -275,7 +278,8 @@ patternProperties: properties: groups: items: - enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_= wp_hold] + enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, + spi2_wp_hold] maxItems: 4 - if: properties: @@ -332,13 +336,14 @@ patternProperties: JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTR= ST_N, WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTC= LK, WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, - SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI= 1_MOSI, - SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, S= PI2_CS, - SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_RE= Q, - PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET, - WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK, - WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0, - WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_= HB10] + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MD= IO, + GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB, + WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, W= F_HB3, + WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_= HB8, + WF_HB9, WF_HB10] maxItems: 57 =20 bias-disable: true @@ -348,7 +353,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 @@ -357,7 +362,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctr= l.yaml index 71033831d03d..7157500a7f81 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT7986 Pin Controller maintainers: - Sean Wang =20 -description: |+ +description: The MediaTek's MT7986 Pin controller is used to control SoC pins. =20 properties: @@ -37,15 +37,15 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. =20 interrupt-controller: true @@ -81,7 +81,7 @@ patternProperties: The following table shows the effective values of "group", "func= tion" properties and chip pinout pins =20 - groups function pins (in pin#) + groups function pins (in pin#) ----------------------------------------------------------------= ----- "watchdog" "watchdog" 0 "wifi_led" "led" 1, 2 @@ -97,8 +97,9 @@ patternProperties: "pwm1_0" "pwm" 22, "snfi" "flash" 23, 24, 25, 26, 27, 28 "spi1_2" "spi" 29, 30, 31, 32 - "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30= , 31, + 32 + "spi1_1" "spi" 23, 24, 25, 26 "uart1_2_rx_tx" "uart" 29, 30 "uart1_2_cts_rts" "uart" 31, 32 @@ -115,8 +116,9 @@ patternProperties: "pcie_pereset" "pcie" 41 "uart1" "uart" 42, 43, 44, 45 "uart2" "uart" 46, 47, 48, 49 - "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 57, - 59, 60, 61 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58= , 59, + 60, 61 + "pcm" "audio" 62, 63, 64, 65 "i2s" "audio" 62, 63, 64, 65 "switch_int" "eth" 66 @@ -129,18 +131,17 @@ patternProperties: $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the g= roup. There is no "audio", "pcie" functions on mt7986b, you can on= ly use those functions on mt7986a. enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart, watchdog, wifi] groups: - description: | + description: An array of strings. Each string contains the name of a grou= p. - There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm= ", - and "i2s" groups on mt7986b, you can only use those groups on - mt7986a. + There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm= ", and + "i2s" groups on mt7986b, you can only use those groups on mt= 7986a. required: - function - groups @@ -258,29 +259,30 @@ patternProperties: '.*conf.*': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" =20 properties: pins: - description: | - An array of strings. Each string contains the name of a pin. - There is no PIN 41 to PIN 65 above on mt7686b, you can only = use - those pins on mt7986a. + description: + An array of strings. Each string contains the name of a pin.= There + is no PIN 41 to PIN 65 above on mt7686b, you can only use th= ose + pins on mt7986a. items: enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, G= PIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_= 7, - GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, G= PIO_14, - GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, = SPI0_CS, - SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, S= PI1_CS, - SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, S= PI2_WP, - UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART= 1_TXD, - UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, - UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, - EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, - EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, = PCM_DTX, - PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MD= IO, + GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, + GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART= 1_CTS, + UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, + EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3, + EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7, + EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_= DRX, + PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_C= LK, WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0= _HB0, WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB= 9, @@ -297,7 +299,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 @@ -306,7 +308,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines= in dt-bindings/pinctrl/mt65xx.h. =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctr= l.yaml index 3e34b03e11fc..372a3aefa937 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8183 Pin Controller maintainers: - Sean Wang =20 -description: |+ +description: The MediaTek's MT8183 Pin controller is used to control SoC pins. =20 properties: @@ -37,15 +37,15 @@ properties: =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. =20 interrupt-controller: true @@ -74,7 +74,7 @@ patternProperties: '^pins': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer @@ -85,7 +85,7 @@ patternProperties: properties: pinmux: description: - integer array, represents gpio pin number and mux setting. + Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are defined as macros in -pinfunc.h directly. =20 @@ -139,7 +139,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -150,7 +151,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -159,14 +161,14 @@ patternProperties: enum: [0, 1, 2, 3] =20 mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arg= uments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 =20 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty= cycle when asserted (high pulse width adjustment). Valid arguments= are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctr= l.yaml index a0519acc92fe..eb6a5cdecc6c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8186 Pin Controller maintainers: - Sean Wang =20 -description: | +description: The MediaTek's MT8186 Pin controller is used to control SoC pins. =20 properties: @@ -19,10 +19,10 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: @@ -31,14 +31,14 @@ properties: gpio-line-names: true =20 reg: - description: | - Physical address base for gpio base registers. There are 8 different= GPIO + description: + Physical address base for GPIO base registers. There are 8 different= GPIO physical address base in mt8186. maxItems: 8 =20 reg-names: - description: | - Gpio base register names. + description: + GPIO base register names. items: - const: iocfg0 - const: iocfg_lt @@ -60,9 +60,9 @@ properties: =20 mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support= RSEL + define or si unit value(ohm) to set different resistance. =20 # PIN CONFIGURATION NODES patternProperties: @@ -77,8 +77,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -98,11 +98,10 @@ patternProperties: =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -129,10 +128,10 @@ patternProperties: For pull down type is RSEL, it can add RSEL define & resista= nce value(ohm) to set different resistance by identifying proper= ty "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "75000" & "5000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "75000" & = "5000" + in mt8186. An example of using RSEL define: pincontroller { i2c0_pin { @@ -174,10 +173,10 @@ patternProperties: For pull up type is RSEL, it can add RSEL define & resistance value(ohm) to set different resistance by identifying proper= ty "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "1000" & "5000" & "10000" & "75000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "1000" & "= 5000" + & "10000" & "75000" in mt8186. An example of using si unit resistance value(ohm): &pio { mediatek,rsel-resistance-in-si-unit; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctr= l.yaml index 7e750f1e643d..51b3d1247614 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8188 Pin Controller maintainers: - Hui Liu =20 -description: | +description: The MediaTek's MT8188 Pin controller is used to control SoC pins. =20 properties: @@ -19,10 +19,10 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | - Number of cells in GPIO specifier, should be two. The first cell - is the pin number, the second cell is used to specify optional - parameters which are defined in . + description: + Number of cells in GPIO specifier, should be two. The first cell is = the + pin number, the second cell is used to specify optional parameters w= hich + are defined in . const: 2 =20 gpio-ranges: @@ -59,10 +59,11 @@ properties: =20 mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - We provide two methods to select the resistance for I2C when pull up= or pull down. - The first is by RSEL definition value, another one is by resistance = value(ohm). - This flag is used to identify if the method is resistance(si unit) v= alue. + description: + We provide two methods to select the resistance for I2C when pull up= or + pull down. The first is by RSEL definition value, another one is by + resistance value(ohm). This flag is used to identify if the method is + resistance(si unit) value. =20 # PIN CONFIGURATION NODES patternProperties: @@ -75,16 +76,16 @@ patternProperties: type: object $ref: "/schemas/pinctrl/pincfg-node.yaml" additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing = the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are defined as macros in dt-bindings/pinctrl/mediatek,-pinf= unc.h @@ -106,18 +107,21 @@ patternProperties: - enum: [75000, 5000] description: mt8188 pull down RSEL type si unit value(ohm). description: | - For pull down type is normal, it doesn't need add RSEL & R1R= 0 define - and resistance value. + For pull down type is normal, it doesn't need add RSEL & R1R0 + define and resistance value. For pull down type is PUPD/R0/R1 type, it can add R1R0 defin= e to set different resistance. It can support "MTK_PUPD_SET_R1R0_= 00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_= SET_R1R0_11" - define in mt8188. - For pull down type is RSEL, it can add RSEL define & resista= nce value(ohm) - to set different resistance by identifying property "mediate= k,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_P= ULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_P= ULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) = "75000" & "5000" in mt8188. + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull down type is RSEL, it can add RSEL define & resista= nce + value(ohm) to set different resistance by identifying proper= ty + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "75000" & = "5000" + in mt8188. =20 bias-pull-up: oneOf: @@ -131,17 +135,19 @@ patternProperties: description: | For pull up type is normal, it don't need add RSEL & R1R0 de= fine and resistance value. - For pull up type is PUPD/R0/R1 type, it can add R1R0 define = to - set different resistance. It can support "MTK_PUPD_SET_R1R0_= 00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_= SET_R1R0_11" - define in mt8188. - For pull up type is RSEL, it can add RSEL define & resistanc= e value(ohm) - to set different resistance by identifying property "mediate= k,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_= 001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_P= ULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_P= ULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000= " & "75000" in mt8188. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define = to set + different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying proper= ty + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "1000" & "= 1500" + & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in m= t8188. =20 bias-disable: true =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctr= l.yaml index 3c3dd142a989..8cca1ce40f25 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8192 Pin Controller maintainers: - Sean Wang =20 -description: | +description: The MediaTek's MT8192 Pin controller is used to control SoC pins. =20 properties: @@ -19,27 +19,27 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: - description: gpio valid number range. + description: GPIO valid number range. maxItems: 1 =20 gpio-line-names: true =20 reg: - description: | - Physical address base for gpio base registers. There are 11 GPIO - physical address base in mt8192. + description: + Physical address base for GPIO base registers. There are 11 GPIO phy= sical + address base in mt8192. maxItems: 11 =20 reg-names: - description: | - Gpio base register names. + description: + GPIO base register names. maxItems: 11 =20 interrupt-controller: true @@ -59,25 +59,26 @@ patternProperties: patternProperties: '^pins': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. $ref: "pinmux-node.yaml" =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and = are defined - as macros in dt-bindings/pinctrl/-pinfunc.h directly. + Supported pin number and mux varies for different SoCs, and = are + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 drive-strength: - description: | - It can support some arguments, such as MTK_DRIVE_4mA, MTK_DR= IVE_6mA, etc. See - dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10= /12/14/16mA in mt8192. + description: + It can support some arguments, such as MTK_DRIVE_4mA, + MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. It can= only + support 2/4/6/8/10/12/14/16mA in mt8192. enum: [2, 4, 6, 8, 10, 12, 14, 16] =20 drive-strength-microamp: @@ -91,8 +92,8 @@ patternProperties: description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R= 1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull down type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ d= efines + in dt-bindings/pinctrl/mt65xx.h. =20 bias-pull-up: oneOf: @@ -102,8 +103,8 @@ patternProperties: description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R= 0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull up type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ def= ines + in dt-bindings/pinctrl/mt65xx.h. =20 bias-disable: true =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctr= l.yaml index d4d5357cdd1d..b8ba260d74cd 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8195 Pin Controller maintainers: - Sean Wang =20 -description: | +description: The MediaTek's MT8195 Pin controller is used to control SoC pins. =20 properties: @@ -19,27 +19,27 @@ properties: gpio-controller: true =20 '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is= used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular = cells. + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. const: 2 =20 gpio-ranges: - description: gpio valid number range. + description: GPIO valid number range. maxItems: 1 =20 gpio-line-names: true =20 reg: - description: | - Physical address base for gpio base registers. There are 8 GPIO - physical address base in mt8195. + description: + Physical address base for GPIO base registers. There are 8 GPIO phys= ical + address base in mt8195. maxItems: 8 =20 reg-names: - description: | - Gpio base register names. + description: + GPIO base register names. maxItems: 8 =20 interrupt-controller: true @@ -53,9 +53,9 @@ properties: =20 mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support= RSEL + define or si unit value(ohm) to set different resistance. =20 # PIN CONFIGURATION NODES patternProperties: @@ -70,8 +70,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing= the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and= input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -91,11 +91,10 @@ patternProperties: =20 properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -174,9 +173,9 @@ patternProperties: & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8195. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000= " & - "75000" in mt8195. + define in mt8195. It can also support resistance value(ohm) = "1000" + & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75= 000" + in mt8195. An example of using RSEL define: pincontroller { i2c0-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctr= l.yaml index 42964dfa9fdb..5aa8ba4cb547 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Zhiyong Tao - Bernhard Rosenkr=C3=A4nzer =20 -description: | +description: The MediaTek's MT8365 Pin controller is used to control SoC pins. =20 properties: @@ -26,17 +26,17 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. =20 gpio-controller: true =20 "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the= below - mentioned gpio binding representation for description of particular = cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. =20 interrupt-controller: true =20 @@ -54,7 +54,7 @@ patternProperties: "pins$": type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing = the pinctrl groups available on the machine. Each subnode will list = the pins it needs, and how they should be configured, with regard to= muxer @@ -65,14 +65,14 @@ patternProperties: properties: pinmux: description: - integer array, represents gpio pin number and mux setting. + Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are defined as macros in -pinfunc.h directly. =20 bias-disable: true =20 bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pul= l up settings for 2 pull resistors, R0 and R1. User can configure= those special pins. @@ -120,7 +120,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -131,7 +132,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described = as below: + configure those special pins. Valid arguments are described = as + below: 0: (R1, R0) =3D (0, 0) which means R1 disabled and R0 disabl= ed. 1: (R1, R0) =3D (0, 1) which means R1 disabled and R0 enable= d. 2: (R1, R0) =3D (1, 0) which means R1 enabled and R0 disable= d. @@ -140,14 +142,14 @@ patternProperties: enum: [0, 1, 2, 3] =20 mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arg= uments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 =20 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty= cycle when asserted (high pulse width adjustment). Valid arguments= are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.ya= ml index e51667316b2e..43b33dbf115b 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | Ralink RT2880 pin controller for RT2880 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.ya= ml index 23fb82f9959c..55c6f9826e76 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT53= 50 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.ya= ml index adc4f42a175d..8d14e525b25e 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Ar=C4=B1n=C3=A7 =C3=9CNAL - Sergio Paracuellos =20 -description: +description: | Ralink RT3883 pin controller for RT3883 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D81F9C77B60 for ; Fri, 17 Mar 2023 21:32:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231130AbjCQVcB (ORCPT ); Fri, 17 Mar 2023 17:32:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230385AbjCQVbf (ORCPT ); Fri, 17 Mar 2023 17:31:35 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC5FA2F793; Fri, 17 Mar 2023 14:31:00 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id cy23so25349146edb.12; Fri, 17 Mar 2023 14:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=277v3QDHxGQ1e2vDSHNJ1RgrCQUtqjYsBl0P+spQaKY=; b=AKZeqzQtnCUfHf+sC2z6FujqATaMDElVe1Kb7asiqi2gApeooDYo+dvNc18Yi1rnaC 1vzmZ//1f4NHby7q8Imaq7/tO3LMrIp45cKpL2wo466wrDA7wX6rQiPdWNgztj+59QwC OgwCOtJfLbmTScN4eySQ0Uu+fGls2BB6afCCIYzyZeqaP1BwFGCe+IVy2NSdZCJnYDwv /6Q22L8kwHDYAGEj8fwePcOXZsQqI3Es/o7xX2TB7Y+W+0hgsap8voTvZt4F6vDxNpzO iV5XgWUyGF6rs4pf45z5M5Eqfa5PTm+DzXL8alzLyJsJ5pOxdfcVGWvSqa1RfmsgJCg/ PyQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088657; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=277v3QDHxGQ1e2vDSHNJ1RgrCQUtqjYsBl0P+spQaKY=; b=qbJ4sle2ZCO3qSq2fCRX9gkmFhuEDiTJ2z2SAqmgp4EGPPjAPNpC3eBMg+vhcJWVd6 ylhAA102hMHdpBbPT02+8roy8WMydURmZYEcw+YVmD+ev8h7kWzGt5FxTRXcP1rdmWWQ RGdujb3V0PbHqp3QIA2XSZfi/ffGgVVijEwZAtJ9/9lRRBdZCnsIFh6iUj+us18G9M62 pXAOL7+Qdujf+FuGTSI0QpqrR8CJUCY0LfX68JMRSKqQcQ9IMRHU4L4iEZcBOUZwcAd6 8nzuM57CayB2+DzryuxLR7rkN8SpWVcygnvdAUbil52CrUN76MvjULS1fHSyTXXmDZa1 iZ3A== X-Gm-Message-State: AO0yUKXDIPoYpRrum6ioYnnK63IB3BfWdcqdnybhJ6rd7FMJcOjg0YZD tw39M0niCs5Z0ZEt3nZ82WU= X-Google-Smtp-Source: AK7set8J5Y0Ip/HTJOArW+lQprOCLQawHAUMxX8XoeiqqznMShgkzJGiK4AMIN4ygknSUFodhayigg== X-Received: by 2002:aa7:d6c8:0:b0:4fa:785d:121 with SMTP id x8-20020aa7d6c8000000b004fa785d0121mr4391276edr.16.1679088657090; Fri, 17 Mar 2023 14:30:57 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:56 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 16/21] dt-bindings: pinctrl: mediatek: fix pinmux header location Date: Sat, 18 Mar 2023 00:30:06 +0300 Message-Id: <20230317213011.13656-17-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Fix the location of the pinmux header files mentioned on the schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 2 +- .../devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctr= l.yaml index 5e80621800a9..3b3d59140073 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -90,7 +90,7 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in -pinfunc.h directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 bias-disable: true =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctr= l.yaml index 1d038f6f8971..e5e7143674b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -131,7 +131,7 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in boot/dts/-pinfunc.h directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h dir= ectly. =20 bias-disable: true =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctr= l.yaml index 51b3d1247614..028146fb173f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -88,8 +88,8 @@ patternProperties: description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and = are - defined as macros in dt-bindings/pinctrl/mediatek,-pinf= unc.h - directly. + defined as macros in dt-bindings/pinctrl/mediatek,mt8188-pin= func.h + directly, for this SoC. =20 drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CFC7C74A5B for ; Fri, 17 Mar 2023 21:32:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231266AbjCQVcI (ORCPT ); Fri, 17 Mar 2023 17:32:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230387AbjCQVbh (ORCPT ); Fri, 17 Mar 2023 17:31:37 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8553647835; Fri, 17 Mar 2023 14:31:02 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id x13so25489336edd.1; Fri, 17 Mar 2023 14:31:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRRRjQq3YR+UffmCBrvj5g0GLFd9Ga+6nn8JCLDb/LY=; b=gd7/k2Dsv3cvSTMDoIhJiW+kYCEnvSwtq3EhasiCnlb8kdELNv3Yku+pkcoPbQW9Yv bWRTaXjlNaFwbdgalWz7ZwT/oqaLrgDVIpBHwAIhN+s5NZRo391aSb4g4X7xbgcELdrH oomojyX4lmS8BLqNcCwSHj8BzyaCXGMtFGrCtLFkhGGdwR+COApf2RVlDjLm6Pt9J2YM zGUO4GrFy4HvY/1jkaUvct3Mnwg4tHFVl39iy2pQGVjlXi0+xLQSQIxuBuKYncQoVoWV whSRoMX3RE7qckKUDUFGAW2hMgSFe3mZIQw27AuaM2Yi8bUbXHIOWLG7EVcBJ4vNaI4Q prIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRRRjQq3YR+UffmCBrvj5g0GLFd9Ga+6nn8JCLDb/LY=; b=Fb6CRJzzQvUu3pPZadN1wzpsGZjqDy4aLWfodAjU11zN2TSlzUQwbWGzPW797MmXhR Ac+4MJ+8KoE3deUp2LpU82+BA1GjWHwVB7LgwO0Up+wwP0K0jlK+4Vo7aRQikQQt6Ltz i0yrdeEBdVnaq8f6B7H+YxEtSnWY/XERPWfgvvhL4PASXolLTAUithpMwQfGzaAGNztr FTTGnTOEJaGFGRHzBKquzozq1jDX/KilQmc8NV26VFqbOPQbyt9OuatuDGOlChnScbu9 H1YQgsVqcxUZRkL8CxsPax1yLutFCNetwhKe2SGf3bJQ7VwrVT04NQ4d6ZlFncp9NU1o NfYQ== X-Gm-Message-State: AO0yUKUgaVTnI8vQPTW7RIKNPjojMXCOdbK7Yr82nw0SWlICKs1Ju/BB c4HUAdCFzA9CrOiIE1Qw2nU= X-Google-Smtp-Source: AK7set/wLlTE2egESzRiiLAbGob9reK+bCtPzcpYCbbRURE3vgs3lFuaz+ljmGw5GJFnbMJTZoOQsA== X-Received: by 2002:a17:906:37d4:b0:922:78e2:7680 with SMTP id o20-20020a17090637d400b0092278e27680mr797923ejc.52.1679088659557; Fri, 17 Mar 2023 14:30:59 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:30:59 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 17/21] dt-bindings: pinctrl: mediatek: drop quotes from referred schemas Date: Sat, 18 Mar 2023 00:30:07 +0300 Message-Id: <20230317213011.13656-18-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Drop the quotes from the referred schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt6795-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt7622-pinctrl.yaml | 6 +++--- .../bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 6 +++--- .../bindings/pinctrl/mediatek,mt8183-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt8186-pinctrl.yaml | 2 +- .../bindings/pinctrl/mediatek,mt8188-pinctrl.yaml | 2 +- .../bindings/pinctrl/mediatek,mt8192-pinctrl.yaml | 4 ++-- .../bindings/pinctrl/mediatek,mt8195-pinctrl.yaml | 4 ++-- 10 files changed, 20 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctr= l.yaml index 3b3d59140073..bccff08a5ba3 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -67,7 +67,7 @@ required: - "#gpio-cells" =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 patternProperties: 'pins$': @@ -83,7 +83,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to= muxer configuration, pullups, drive strength, input enable/disable and= input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml =20 properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctr= l.yaml index e5e7143674b5..7f0e2d6cd6d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -58,7 +58,7 @@ required: - "#gpio-cells" =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# - if: properties: compatible: @@ -124,7 +124,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to= muxer configuration, pullups, drive strength, input enable/disable and= input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml =20 properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctr= l.yaml index c3bf98749fa4..601d86aecdd4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -82,7 +82,7 @@ patternProperties: } }; }; - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml =20 properties: pinmux: @@ -156,7 +156,7 @@ patternProperties: - pinmux =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctr= l.yaml index 38dc41c735eb..bd72a326e6e0 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -43,7 +43,7 @@ properties: const: 2 =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible @@ -70,7 +70,7 @@ patternProperties: additionalProperties: false description: pinmux configuration nodes. - $ref: "/schemas/pinctrl/pinmux-node.yaml" + $ref: /schemas/pinctrl/pinmux-node.yaml properties: function: description: @@ -249,7 +249,7 @@ patternProperties: additionalProperties: false description: pinconf configuration nodes. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml =20 properties: groups: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctr= l.yaml index 7157500a7f81..31c36689438c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -57,7 +57,7 @@ properties: const: 2 =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible @@ -128,7 +128,7 @@ patternProperties: "wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82= , 83, 84, 85 =20 - $ref: "/schemas/pinctrl/pinmux-node.yaml" + $ref: /schemas/pinctrl/pinmux-node.yaml properties: function: description: @@ -261,7 +261,7 @@ patternProperties: additionalProperties: false description: pinconf configuration nodes. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml =20 properties: pins: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctr= l.yaml index 372a3aefa937..bf67d4672455 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -57,7 +57,7 @@ properties: const: 2 =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible @@ -80,7 +80,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to= muxer configuration, pullups, drive strength, input enable/disable and= input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml =20 properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctr= l.yaml index eb6a5cdecc6c..69136ddd0bbc 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -94,7 +94,7 @@ patternProperties: } }; }; - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml =20 properties: pinmux: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctr= l.yaml index 028146fb173f..e994b0c70dbf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -74,7 +74,7 @@ patternProperties: patternProperties: '^pins': type: object - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: /schemas/pinctrl/pincfg-node.yaml additionalProperties: false description: A pinctrl node should contain at least one subnode representing = the diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctr= l.yaml index 8cca1ce40f25..c43338cafd61 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -65,7 +65,7 @@ patternProperties: pins it needs, and how they should be configured, with regard to= muxer configuration, pullups, drive strength, input enable/disable and= input schmitt. - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml =20 properties: pinmux: @@ -126,7 +126,7 @@ patternProperties: additionalProperties: false =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctr= l.yaml index b8ba260d74cd..33cb71775db9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -87,7 +87,7 @@ patternProperties: } }; }; - $ref: "pinmux-node.yaml" + $ref: pinmux-node.yaml =20 properties: pinmux: @@ -216,7 +216,7 @@ patternProperties: - pinmux =20 allOf: - - $ref: "pinctrl.yaml#" + - $ref: pinctrl.yaml# =20 required: - compatible --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEBB5C76196 for ; Fri, 17 Mar 2023 21:32:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231216AbjCQVcS (ORCPT ); Fri, 17 Mar 2023 17:32:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231199AbjCQVbo (ORCPT ); Fri, 17 Mar 2023 17:31:44 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4327064848; Fri, 17 Mar 2023 14:31:11 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id w9so25498783edc.3; Fri, 17 Mar 2023 14:31:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c5OtwbUxmcTKUcw9nCm7KvLn2T2yQoHX2fxmIgn1joc=; b=k5HsOmpP6ocKUMcjWKrrBBicP5UP1XV0pgXiowNDsc8efI8SjF8Ug8j+PlzoizDdCN TJXVDLEFe2+yBx7YMqylpFiZYc1hLL8VE8uh7GmQAzjkaBOQWWOBDjAfBHvpqJ3TrzUs k75WwOjgSqSnCUaurN2DOiATz7dYdqiqiF7PoklCyXJjjVEwT4TviLtOQwmoFfgphtRX 95f7pL99JgGaSGKa14DzIbTe/I3iUQ8i3dXvMQtsNG8kaSzJG2eQSqAV5k97W1Bydrmx xAahyDiV0s7RWznH1dju4uMZRmF/3eIWoY3j9E2POBe1trABTHRKGuqbp0Heozm1JkUg Rudw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c5OtwbUxmcTKUcw9nCm7KvLn2T2yQoHX2fxmIgn1joc=; b=e/ELa50Nn29YBKHU5EaEy0nhlckqIO6rq5xUG+A4BOkSR83yCX9rc4PZPAhzlSkDCv j9aOr7fiLNU4R/DvniemH/32psN927hFhj/z8XtBE2GzIYqwHM9pHIYus44rxg/CvVP/ 3YZeTydEJYoOrFBNgwVAR2c+BvVGzJolzyjbCDjnmrEEFTLtq/MnXcIHcfR4UvVCsRA1 S+301c1+CTqVwJmokdKqhs0ozo4+XAa5AVxY2feiXrqAyP38WtylXJl0GdYhyeUyBy/Z LUznm2Fg+UY2HCWIb7rD/cy+ATcuUJcDZX4E6djy+YeBBRQqYE/5J7zYDZn2NTBXVdpw ZCyA== X-Gm-Message-State: AO0yUKVFiOBY6wPtOpjB9jKwl6wyGueIcOBe/Cys+YaMat87riI4g9JD X8Y00V/8m/mBQVjtTlKvNDE= X-Google-Smtp-Source: AK7set8dxol7s9TtQUQkUVdpCaiNcAKLEikKSgZOp+3/1rG7qVY0TV37G3jWDSdtBvXKUvmRn4xEcQ== X-Received: by 2002:a17:906:810:b0:8f0:143d:ee34 with SMTP id e16-20020a170906081000b008f0143dee34mr844693ejd.1.1679088661990; Fri, 17 Mar 2023 14:31:01 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.30.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:31:01 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 18/21] dt-bindings: pinctrl: mediatek: mt7986: fix patternProperties regex Date: Sat, 18 Mar 2023 00:30:08 +0300 Message-Id: <20230317213011.13656-19-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Set second level patternProperties to '^.*mux.*$' and '^.*conf.*$' on mediatek,mt7986-pinctrl.yaml to be on par with other schemas. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- .../devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctr= l.yaml index 31c36689438c..0f615ada290a 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -72,7 +72,7 @@ patternProperties: additionalProperties: false =20 patternProperties: - '.*mux.*': + '^.*mux.*$': type: object additionalProperties: false description: | @@ -256,7 +256,7 @@ patternProperties: items: enum: [wf_2g, wf_5g, wf_dbdc] maxItems: 3 - '.*conf.*': + '^.*conf.*$': type: object additionalProperties: false description: --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70481C76196 for ; Fri, 17 Mar 2023 21:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230241AbjCQVcU (ORCPT ); Fri, 17 Mar 2023 17:32:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230403AbjCQVbs (ORCPT ); Fri, 17 Mar 2023 17:31:48 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 695532F042; Fri, 17 Mar 2023 14:31:14 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id o12so25382189edb.9; Fri, 17 Mar 2023 14:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8yu8jx+Bn0uWS9+tZTglcUL4SPeA/bfBOXrCTgW/Wh8=; b=NCH49KH2VkHoh831KGaAOFlseyHE3VCIXNcClKuzOAwnzCuK9IDHNy/okJHMGbuqqe iUJeo5btO3kz/xFM7Z2k+Xo3lJyo8PB/49N8vNLF9D37EONx3lHvA04OmQfLjeR7BbtU XYVrKZDf675Agr6C2qHmJPSEuoxJYSGRPlwa5v+GRUogygtO+A9Vz2KpDywXPS+ZLBny sBoftZdbLj0xmqgykSlfgxPXjpzoLKyLP3K0hKhMWD3ZiiErs+TaNSJudXm9ed+xKMWl YOZ/8kCQ7DOfhFsJ+zYyxTKo2DfsQs4zHaklXGW+l9JmfbnyUTUMvBwyAjP2+U1Vu/b6 /P3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8yu8jx+Bn0uWS9+tZTglcUL4SPeA/bfBOXrCTgW/Wh8=; b=C04EOTUM2LBCZwX5pfyKqb7j7ap1Hf+Gckq31Xv92Xh01gBANtJyugWE4Avye1VrYP QCExRC7kytnQ6sOaP7IZQVspBrXp3100ELvJrC3KPQoPas2bw7M4/fczYTAk1NrjEtpv 0RjqRb1m6LDmGzyjFn/Spyg2es9x4vp4qeRbHIYZmJjUyYcU4NAVQ2G3PHY0SBjQYd1o WwgtTVFTcFzHF0tCBI5mWGSezFNN9YAnkiufjE0r4d/SgVCWpxgvfGHBzKKCKXdLyHdo fRcKOhfdd0bqj9EWwWRDND1KvDFNtSjk33evZi2uR6117AKH/ogSpSxHhvBm4dFKnGkb o4AQ== X-Gm-Message-State: AO0yUKVBqLx4716V8UYfznfnT/ZJzWptEgHnog+plKd5G5tqxqx/vx0x XGir2hIwZ3btQbz0jIXPpcg= X-Google-Smtp-Source: AK7set+XWrvn/B2c82lPXMjGRfcClzfOs4Wo1ND1mkunRJMAvsfAC6nfbVm8A1au4PCBEBGAenKWhg== X-Received: by 2002:a17:906:118e:b0:930:6db6:39c0 with SMTP id n14-20020a170906118e00b009306db639c0mr901706eja.61.1679088664479; Fri, 17 Mar 2023 14:31:04 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:31:04 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 19/21] dt-bindings: pinctrl: ralink: rt305x: split binding Date: Sat, 18 Mar 2023 00:30:09 +0300 Message-Id: <20230317213011.13656-20-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The RT3352 and RT5350 SoCs each contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to ralink,rt3352-pinctrl.yaml and ralink,rt5350-pinctrl.yaml. Remove ralink,rt3352-pinctrl and ralink,rt5350-pinctrl from rt305x. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- .../pinctrl/ralink,rt305x-pinctrl.yaml | 83 +----- .../pinctrl/ralink,rt3352-pinctrl.yaml | 243 ++++++++++++++++++ .../pinctrl/ralink,rt5350-pinctrl.yaml | 206 +++++++++++++++ 3 files changed, 455 insertions(+), 77 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt3352= -pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt5350= -pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.ya= ml index 55c6f9826e76..95a904273009 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -11,17 +11,13 @@ maintainers: - Sergio Paracuellos =20 description: | - Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT53= 50 - SoCs. + Ralink RT305X pin controller for RT3050, RT3052, and RT3350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 properties: compatible: - enum: - - ralink,rt305x-pinctrl - - ralink,rt3352-pinctrl - - ralink,rt5350-pinctrl + const: ralink,rt305x-pinctrl =20 patternProperties: '-pins$': @@ -39,21 +35,9 @@ patternProperties: function: description: A string containing the name of the function to mux to the g= roup. - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, m= dio, - pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, ua= rtf, - uartlite] - - - description: For RT3352 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, l= ed, - lna, mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii,= spi, - spi_cs1, uartf, uartlite, wdg_cs1] - - - description: For RT5350 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, l= ed, - pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, - uartlite, wdg_cs1] + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, + pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, + uartlite] =20 groups: description: @@ -72,17 +56,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, - uartlite] - - - description: For RT3352 SoC - enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, sp= i_cs1, - uartf, uartlite] - - - description: For RT5350 SoC - enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartli= te] =20 - if: properties: @@ -129,24 +103,6 @@ patternProperties: groups: enum: [jtag] =20 - - if: - properties: - function: - const: led - then: - properties: - groups: - enum: [led] - - - if: - properties: - function: - const: lna - then: - properties: - groups: - enum: [lna] - - if: properties: function: @@ -156,15 +112,6 @@ patternProperties: groups: enum: [mdio] =20 - - if: - properties: - function: - const: pa - then: - properties: - groups: - enum: [pa] - - if: properties: function: @@ -219,15 +166,6 @@ patternProperties: groups: enum: [spi] =20 - - if: - properties: - function: - const: spi_cs1 - then: - properties: - groups: - enum: [spi_cs1] - - if: properties: function: @@ -246,15 +184,6 @@ patternProperties: groups: enum: [uartlite] =20 - - if: - properties: - function: - const: wdg_cs1 - then: - properties: - groups: - enum: [spi_cs1] - allOf: - $ref: pinctrl.yaml# =20 diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.ya= ml new file mode 100644 index 000000000000..c9bc6cfd834c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt3352-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT3352 Pin Controller + +maintainers: + - Ar=C4=B1n=C3=A7 =C3=9CNAL + - Sergio Paracuellos + +description: | + Ralink RT3352 pin controller for RT3352 SoC. + The pin controller can only set the muxing of pin groups. Muxing individ= ual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt3352-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the g= roup. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, = lna, + mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi= _cs1, + uartf, uartlite, wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a grou= p. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs= 1, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: lna + then: + properties: + groups: + enum: [lna] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible =3D "ralink,rt3352-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups =3D "i2c"; + function =3D "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.ya= ml new file mode 100644 index 000000000000..f248202ce866 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt5350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT5350 Pin Controller + +maintainers: + - Ar=C4=B1n=C3=A7 =C3=9CNAL + - Sergio Paracuellos + +description: | + Ralink RT5350 pin controller for RT5350 SoC. + The pin controller can only set the muxing of pin groups. Muxing individ= ual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt5350-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the g= roup. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, uart= lite, + wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a grou= p. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible =3D "ralink,rt5350-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups =3D "i2c"; + function =3D "i2c"; + }; + }; + }; --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DF07C74A5B for ; Fri, 17 Mar 2023 21:32:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231302AbjCQVc0 (ORCPT ); Fri, 17 Mar 2023 17:32:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231231AbjCQVbu (ORCPT ); Fri, 17 Mar 2023 17:31:50 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33488B6D3C; Fri, 17 Mar 2023 14:31:17 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id w9so25499431edc.3; Fri, 17 Mar 2023 14:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W0VhD6TWwJqs+7/MwqgfsHWYoMGA/MgmyVTpHFe9EaI=; b=cVflFt8JOb2TkDnZzV2H7jv58vmV4KqxYyXKORJ1N7Bw/GFpY9qBm+khXVVOHyJUfM y+hhYpRqYLnW5nW/JGJLZlrptNmkWtJVJROx4pnz4wv2+nrSpoSjuabTVqXt0Fi3jfyC lChWAbCaS3eAKP0cXU7sZS0JbGV2klERxGVbfyrWNkjlnhKVforA8gcOq4LZ6kjWV/IZ qyS4iTcZpbfJv1Z5BHB7cOrm/Fqpx7hS8Ak32B7AGjyriwpe17+kqxR8BlhPhEFA1N7f 5asI8b0kjnXu8pZScn05ASP3K4X31yNbrMDplS1ZR+kXoNcf2h7BQd1tW48io7MsbUFa y4AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W0VhD6TWwJqs+7/MwqgfsHWYoMGA/MgmyVTpHFe9EaI=; b=Ncl5dLMezyF7TC2u5tGFTnE9bw7Ecw8dgUA7goBkzyoGiZ+oSYuldJxCiz6ORtNAU+ 4Bw2kC5RPS6AY3VC7LW6SQZdAgHzVMDsQBDAR3nqAQfLMkIpaY4hAnUw0KRyFbVaiD9G Kk7/Q1l8xOdOap/kc/tuyx9jUTGsrwUcT+llz2UWdzr8LKkMxTgfxWCwdzesH2v8f7vo dGBC2HotNOEawZFOcrmfinLcm+2RNtp4v0/SjcejpyT7g3hUSw2tIKuK6vfKb/ZNW3a4 D3IHcJuk8soSBeZCV9w4xCpMQLFM+cc2tb3xq5US0WzmFIJFSrO2wM4Ks9TnHAn7suoQ DYnw== X-Gm-Message-State: AO0yUKWnU5VXHE5A0c2HrLfJTHnx51nFjH8HZtsPjVyAub4Nlcuv6L02 vPLxJ6xt00Uz+MN3NI7dXj4= X-Google-Smtp-Source: AK7set+bS6MuHR5h08NZKukD2yRpT4F2I/UXrRCHKNAhQ++gJbrsukm5FrI8wOF6Ivhjodb753L7yQ== X-Received: by 2002:a17:906:af10:b0:8b1:7ae9:647 with SMTP id lx16-20020a170906af1000b008b17ae90647mr567714ejb.76.1679088666948; Fri, 17 Mar 2023 14:31:06 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:31:06 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Rob Herring , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Sergio Paracuellos , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 20/21] dt-bindings: pinctrl: mediatek: mt7620: split binding Date: Sat, 18 Mar 2023 00:30:10 +0300 Message-Id: <20230317213011.13656-21-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The MT7628 and MT7688 SoCs contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to mediatek,mt76x8-pinctrl.yaml. Remove mediatek,mt76x8-pinctrl from mt7620. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Rob Herring --- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 379 +-------------- .../pinctrl/mediatek,mt76x8-pinctrl.yaml | 450 ++++++++++++++++++ 2 files changed, 459 insertions(+), 370 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt76= x8-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctr= l.yaml index 808dd8bd276f..591bc0664ec6 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -11,15 +11,13 @@ maintainers: - Sergio Paracuellos =20 description: | - MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620 SoC. The pin controller can only set the muxing of pin groups. Muxing individ= ual pins is not supported. There is no pinconf support. =20 properties: compatible: - enum: - - ralink,mt7620-pinctrl - - ralink,mt76x8-pinctrl + const: ralink,mt7620-pinctrl =20 patternProperties: '-pins$': @@ -37,19 +35,10 @@ patternProperties: function: description: A string containing the name of the function to mux to the g= roup. - anyOf: - - description: For MT7620 SoC - enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, m= dio, nand, pa, - pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf= , refclk, - rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlit= e, wdt refclk, - wdt rst, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0l= ed_kn, - p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p= 3led_kn, - p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pw= m1, pwm_uart2, - refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, s= pi, spi cs1, - spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an= , wled_kn, -] + enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio,= nand, + pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, + refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uar= tlite, + wdt refclk, wdt rst, wled] =20 groups: description: @@ -61,24 +50,6 @@ patternProperties: - function =20 allOf: - - if: - properties: - function: - const: antenna - then: - properties: - groups: - enum: [i2s] - - - if: - properties: - function: - const: debug - then: - properties: - groups: - enum: [i2c] - - if: properties: function: @@ -95,17 +66,8 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgm= ii2, - spi, spi refclk, uartf, uartlite, wdt, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, - p1led_kn, p2led_an, p2led_kn, p3led_an, p3led= _kn, - p4led_an, p4led_kn, perst, pwm0, pwm1, refclk, - sdmode, spi, spi cs1, spis, uart0, uart1, uar= t2, - wdt, wled_an, wled_kn] + enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2,= spi, + spi refclk, uartf, uartlite, wdt, wled] =20 - if: properties: @@ -134,15 +96,6 @@ patternProperties: groups: enum: [i2c] =20 - - if: - properties: - function: - const: i2s - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -152,17 +105,6 @@ patternProperties: groups: enum: [uartf] =20 - - if: - properties: - function: - const: jtag - then: - properties: - groups: - enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, - p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, - sdmode] - - if: properties: function: @@ -181,96 +123,6 @@ patternProperties: groups: enum: [nd_sd] =20 - - if: - properties: - function: - const: p0led_an - then: - properties: - groups: - enum: [p0led_an] - - - if: - properties: - function: - const: p0led_kn - then: - properties: - groups: - enum: [p0led_kn] - - - if: - properties: - function: - const: p1led_an - then: - properties: - groups: - enum: [p1led_an] - - - if: - properties: - function: - const: p1led_kn - then: - properties: - groups: - enum: [p1led_kn] - - - if: - properties: - function: - const: p2led_an - then: - properties: - groups: - enum: [p2led_an] - - - if: - properties: - function: - const: p2led_kn - then: - properties: - groups: - enum: [p2led_kn] - - - if: - properties: - function: - const: p3led_an - then: - properties: - groups: - enum: [p3led_an] - - - if: - properties: - function: - const: p3led_kn - then: - properties: - groups: - enum: [p3led_kn] - - - if: - properties: - function: - const: p4led_an - then: - properties: - groups: - enum: [p4led_an] - - - if: - properties: - function: - const: p4led_kn - then: - properties: - groups: - enum: [p4led_kn] - - if: properties: function: @@ -280,15 +132,6 @@ patternProperties: groups: enum: [pa] =20 - - if: - properties: - function: - const: pcie - then: - properties: - groups: - enum: [gpio] - - if: properties: function: @@ -307,15 +150,6 @@ patternProperties: groups: enum: [pcie] =20 - - if: - properties: - function: - const: pcm - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -343,51 +177,6 @@ patternProperties: groups: enum: [uartf] =20 - - if: - properties: - function: - const: perst - then: - properties: - groups: - enum: [perst] - - - if: - properties: - function: - const: pwm - then: - properties: - groups: - enum: [uart1, uart2] - - - if: - properties: - function: - const: pwm0 - then: - properties: - groups: - enum: [pwm0] - - - if: - properties: - function: - const: pwm1 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: pwm_uart2 - then: - properties: - groups: - enum: [spis] - - if: properties: function: @@ -395,12 +184,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [mdio] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, refclk, spi cs1] + enum: [mdio] =20 - if: properties: @@ -420,15 +204,6 @@ patternProperties: groups: enum: [rgmii2] =20 - - if: - properties: - function: - const: rsvd - then: - properties: - groups: - enum: [p0led_an, p0led_kn, wled_an, wled_kn] - - if: properties: function: @@ -438,42 +213,6 @@ patternProperties: groups: enum: [nd_sd] =20 - - if: - properties: - function: - const: sdxc - then: - properties: - groups: - enum: [sdmode] - - - if: - properties: - function: - const: sdxc d5 d4 - then: - properties: - groups: - enum: [uart2] - - - if: - properties: - function: - const: sdxc d6 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: sdxc d7 - then: - properties: - groups: - enum: [pwm0] - - if: properties: function: @@ -483,15 +222,6 @@ patternProperties: groups: enum: [spi] =20 - - if: - properties: - function: - const: spi cs1 - then: - properties: - groups: - enum: [spi cs1] - - if: properties: function: @@ -501,51 +231,6 @@ patternProperties: groups: enum: [spi refclk] =20 - - if: - properties: - function: - const: spis - then: - properties: - groups: - enum: [spis] - - - if: - properties: - function: - const: sw_r - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart0 - then: - properties: - groups: - enum: [uart0] - - - if: - properties: - function: - const: uart1 - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart2 - then: - properties: - groups: - enum: [uart2] - - if: properties: function: @@ -564,25 +249,6 @@ patternProperties: groups: enum: [uartlite] =20 - - if: - properties: - function: - const: utif - then: - properties: - groups: - enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, - p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode,= spis] - - - if: - properties: - function: - const: wdt - then: - properties: - groups: - enum: [wdt] - - if: properties: function: @@ -610,33 +276,6 @@ patternProperties: groups: enum: [wled] =20 - - if: - properties: - function: - const: wled_an - then: - properties: - groups: - enum: [wled_an] - - - if: - properties: - function: - const: wled_kn - then: - properties: - groups: - enum: [wled_kn] - - - if: - properties: - function: - const: "-" - then: - properties: - groups: - enum: [i2c, spi cs1, uart0] - allOf: - $ref: pinctrl.yaml# =20 diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctr= l.yaml new file mode 100644 index 000000000000..31849dd5940b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml @@ -0,0 +1,450 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT76X8 Pin Controller + +maintainers: + - Ar=C4=B1n=C3=A7 =C3=9CNAL + - Sergio Paracuellos + +description: | + MediaTek MT76X8 pin controller for MT7628 and MT7688 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individ= ual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt76x8-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the g= roup. + enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_k= n, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led= _kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, + pwm_uart2, refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdx= c d7, + spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wd= t, + wled_an, wled_kn, -] + + groups: + description: + An array of strings. Each string contains the name of a grou= p. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: antenna + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: debug + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1l= ed_kn, + p2led_an, p2led_kn, p3led_an, p3led_kn, p4led_an, + p4led_kn, perst, pwm0, pwm1, refclk, sdmode, spi, + spi cs1, spis, uart0, uart1, uart2, wdt, wled_an, + wled_kn] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, + sdmode] + + - if: + properties: + function: + const: p0led_an + then: + properties: + groups: + enum: [p0led_an] + + - if: + properties: + function: + const: p0led_kn + then: + properties: + groups: + enum: [p0led_kn] + + - if: + properties: + function: + const: p1led_an + then: + properties: + groups: + enum: [p1led_an] + + - if: + properties: + function: + const: p1led_kn + then: + properties: + groups: + enum: [p1led_kn] + + - if: + properties: + function: + const: p2led_an + then: + properties: + groups: + enum: [p2led_an] + + - if: + properties: + function: + const: p2led_kn + then: + properties: + groups: + enum: [p2led_kn] + + - if: + properties: + function: + const: p3led_an + then: + properties: + groups: + enum: [p3led_an] + + - if: + properties: + function: + const: p3led_kn + then: + properties: + groups: + enum: [p3led_kn] + + - if: + properties: + function: + const: p4led_an + then: + properties: + groups: + enum: [p4led_an] + + - if: + properties: + function: + const: p4led_kn + then: + properties: + groups: + enum: [p4led_kn] + + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [gpio] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: perst + then: + properties: + groups: + enum: [perst] + + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [uart1, uart2] + + - if: + properties: + function: + const: pwm0 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: pwm1 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: pwm_uart2 + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + enum: [gpio, refclk, spi cs1] + + - if: + properties: + function: + const: rsvd + then: + properties: + groups: + enum: [p0led_an, p0led_kn, wled_an, wled_kn] + + - if: + properties: + function: + const: sdxc + then: + properties: + groups: + enum: [sdmode] + + - if: + properties: + function: + const: sdxc d5 d4 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: sdxc d6 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: sdxc d7 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi cs1 + then: + properties: + groups: + enum: [spi cs1] + + - if: + properties: + function: + const: spis + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: sw_r + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart0 + then: + properties: + groups: + enum: [uart0] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: utif + then: + properties: + groups: + enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, + p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode,= spis] + + - if: + properties: + function: + const: wdt + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled_an + then: + properties: + groups: + enum: [wled_an] + + - if: + properties: + function: + const: wled_kn + then: + properties: + groups: + enum: [wled_kn] + + - if: + properties: + function: + const: "-" + then: + properties: + groups: + enum: [i2c, spi cs1, uart0] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible =3D "ralink,mt76x8-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups =3D "i2c"; + function =3D "i2c"; + }; + }; + }; --=20 2.37.2 From nobody Thu Nov 14 07:14:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BE98C6FD1D for ; Fri, 17 Mar 2023 21:32:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231297AbjCQVcX (ORCPT ); Fri, 17 Mar 2023 17:32:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231149AbjCQVbu (ORCPT ); Fri, 17 Mar 2023 17:31:50 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0319BE1939; Fri, 17 Mar 2023 14:31:19 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id x3so25370210edb.10; Fri, 17 Mar 2023 14:31:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679088669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gA3EusZCOhK627Wk0FirSH/GwKNGmUqwf4ijzEsCNuk=; b=SzjAbA2qsawtxmUxI1XuRk4mZffC5q2hSDgqbFtLfE49cZ3+PZdeenZnNp7Y0SBOll gYrqyca7M465hBdEXzA2swDdCSxwjoQGx16kwpodEGCMXhItidBxbQIdeDd+m68DL6IN KY413kGA430d3GTBArcfyP+B84Ar+FhdVcHpujv5QISjot37GImrKvG+B5RDPFYTtIXh TSPaSyo6kcV+TfMngTjm4bL6p/nbNf+Gb0ihJiz/nUqReMQG03I+/2myV/yfVspGEls+ 8fCOtkdytqKI0nxCMFe34xpIO+Sx/kwa3OAL1sUBGA3AHy/259Um2vaW/ny9E4AzeyCI OvBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679088669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gA3EusZCOhK627Wk0FirSH/GwKNGmUqwf4ijzEsCNuk=; b=u7wjs6O3SMBFmI7TH3Fo72X9Ees3AtKp5njAPqBgmheyL0E+oDyMAFV9iZi/Se/Aow u3ztwJcnkQQkRele4OEIT8URxL/8zj28DCuibwk7YXirT2E1ULqPgnVJSjO/OH5U2jDw s9cUkBh6r9sy/WMS2EnfqG8i7PZkHxPPZMKGKHJavuoZ98/fuc+PgfHDLDj3lNbbnbhb hlb26yld4RFawLPwSfHhL5ePJpNfFsyvFh4mH7Ql4xVeI0ptOypd34mVwNbNXpvY+eJi jhi7zEZnhtDq/iR5+2Q3C5xZzJ1mvv3ZMFMaPE+QWs8XJs5+M0FgD7MB7Y274jT4Vi6q 4gWg== X-Gm-Message-State: AO0yUKWzfErOeWsgV/aV2ryVkAyzioRdWDRYA7iM7AzeSJFl7kTfcdih rR+Mhxr+twxy19/3puNhy7c= X-Google-Smtp-Source: AK7set/PsH37vV26HFz0DUNVPwUSw8kToM24rwlbs1ygRWWocDwys742MwLTFeeRwnWp9Vpfbez3bA== X-Received: by 2002:a17:906:5017:b0:92a:3709:e872 with SMTP id s23-20020a170906501700b0092a3709e872mr859654ejj.19.1679088669349; Fri, 17 Mar 2023 14:31:09 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id v19-20020a17090651d300b0092b86d41dbasm1404683ejk.114.2023.03.17.14.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:31:09 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Sergio Paracuellos , William Dean , Sean Wang , Andy Teng , Del Regno , Daniel Golle , Hui Liu , Zhiyong Tao , =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com, Matthias Brugger , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@vger.kernel.org Subject: [PATCH v3 21/21] MAINTAINERS: move ralink pinctrl to mediatek mips pinctrl Date: Sat, 18 Mar 2023 00:30:11 +0300 Message-Id: <20230317213011.13656-22-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317213011.13656-1-arinc.unal@arinc9.com> References: <20230317213011.13656-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The Ralink pinctrl driver is now under the name of MediaTek MIPS pin controller. Move the maintainer information accordingly. Add dt-binding schema files. Add linux-mediatek@lists.infradead.org as an associated mailing list. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Sergio Paracuellos --- MAINTAINERS | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 6048bbe0e672..f4ee11dab1ab 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16521,6 +16521,28 @@ F: Documentation/devicetree/bindings/pinctrl/media= tek,mt7622-pinctrl.yaml F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml F: drivers/pinctrl/mediatek/ =20 +PIN CONTROLLER - MEDIATEK MIPS +M: Ar=C4=B1n=C3=A7 =C3=9CNAL +M: Sergio Paracuellos +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml +F: drivers/pinctrl/mediatek/pinctrl-mt7620.c +F: drivers/pinctrl/mediatek/pinctrl-mt7621.c +F: drivers/pinctrl/mediatek/pinctrl-mt76x8.c +F: drivers/pinctrl/mediatek/pinctrl-mtmips.* +F: drivers/pinctrl/mediatek/pinctrl-rt2880.c +F: drivers/pinctrl/mediatek/pinctrl-rt305x.c +F: drivers/pinctrl/mediatek/pinctrl-rt3883.c + PIN CONTROLLER - MICROCHIP AT91 M: Ludovic Desroches L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -17496,13 +17518,6 @@ L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/boot/dts/ralink/mt7621* =20 -RALINK PINCTRL DRIVER -M: Ar=C4=B1n=C3=A7 =C3=9CNAL -M: Sergio Paracuellos -L: linux-mips@vger.kernel.org -S: Maintained -F: drivers/pinctrl/ralink/ - RALINK RT2X00 WIRELESS LAN DRIVER M: Stanislaw Gruszka M: Helmut Schaa --=20 2.37.2