From nobody Tue Feb 10 23:00:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78AE6C6FD1D for ; Fri, 17 Mar 2023 11:57:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230131AbjCQL5z (ORCPT ); Fri, 17 Mar 2023 07:57:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230028AbjCQL5u (ORCPT ); Fri, 17 Mar 2023 07:57:50 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6D514B856D for ; Fri, 17 Mar 2023 04:57:35 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F38751480; Fri, 17 Mar 2023 04:58:18 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1D4BE3F885; Fri, 17 Mar 2023 04:57:34 -0700 (PDT) From: Suzuki K Poulose To: coresight@lists.linaro.org Cc: mike.leach@linaro.org, james.clark@arm.com, anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Suzuki K Poulose , Steve Clevenger Subject: [PATCH] coresight: etm4x: Do not access TRCIDR1 for identification Date: Fri, 17 Mar 2023 11:57:28 +0000 Message-Id: <20230317115728.1358368-1-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CoreSight ETM4x architecture clearly provides ways to identify a device via registers in the "Management" class, TRCDEVARCH and TRCDEVTYPE. These registers can be accessed without the Trace domain being powered on. We additionally added TRCIDR1 as fallback in order to cover for any ETMs that may not have implemented TRCDEVARCH. So far, nobody has reported hitting a WARNING we placed to catch such systems. Also, more importantly it is problematic to access TRCIDR1, which is a "Tra= ce" register via MMIO access, without clearing the OSLK. But we cannot mess with the OSLK until we know for sure that this is an ETMv4 device. Thus, this kind of creates a chicken and egg problem unnecessarily for syst= ems "which are compliant" to the ETMv4 architecture. Let us remove the TRCIDR1 fall back check and rely only on TRCDEVARCH. Reported-by: Steve Clevenger Link: https://lore.kernel.org/all/143540e5623d4c7393d24833f2b80600d8d745d2.= 1677881753.git.scclevenger@os.amperecomputing.com/ Cc: Mike Leach Cc: James Clark Fixes: 8b94db1edaee ("coresight: etm4x: Use TRCDEVARCH for component discov= ery") Signed-off-by: Suzuki K Poulose Reviewed-by: Mike Leach --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 104333c2c8a3..c1b72d892d7d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1070,25 +1070,17 @@ static bool etm4_init_iomem_access(struct etmv4_drv= data *drvdata, struct csdev_access *csa) { u32 devarch =3D readl_relaxed(drvdata->base + TRCDEVARCH); - u32 idr1 =3D readl_relaxed(drvdata->base + TRCIDR1); =20 /* * All ETMs must implement TRCDEVARCH to indicate that - * the component is an ETMv4. To support any broken - * implementations we fall back to TRCIDR1 check, which - * is not really reliable. + * the component is an ETMv4 */ - if ((devarch & ETM_DEVARCH_ID_MASK) =3D=3D ETM_DEVARCH_ETMv4x_ARCH) { - drvdata->arch =3D etm_devarch_to_arch(devarch); - } else { - pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCID= R1\n", - smp_processor_id(), devarch); - - if (ETM_TRCIDR1_ARCH_MAJOR(idr1) !=3D ETM_TRCIDR1_ARCH_ETMv4) - return false; - drvdata->arch =3D etm_trcidr_to_arch(idr1); + if ((devarch & ETM_DEVARCH_ID_MASK) !=3D ETM_DEVARCH_ETMv4x_ARCH) { + pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n"); + return false; } =20 + drvdata->arch =3D etm_devarch_to_arch(devarch); *csa =3D CSDEV_ACCESS_IOMEM(drvdata->base); return true; } --=20 2.34.1